TWI808511B - Memory peripheral circuit with three-dimensional transistors and its manufacturing method thereof - Google Patents

Abstract

A memory device includes a memory cell array and a plurality of peripheral circuits coupled to the memory cell array and configured to control the memory cell array. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor. The first 3D transistor includes a 3D semiconductor body and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode comprises metal, and the gate dielectric has a thickness between 1.8 nm and 10 nm.

Description

Memory peripheral circuit with three-dimensional transistor and method for forming the same

The present disclosure relates to memory devices and methods of manufacturing the same.

Scale planar memory cells to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the memory density of planar memory cells approaches an upper limit.

Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array.

In one aspect, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. The first peripheral circuit of the plurality of peripheral circuits includes a first 3D transistor. The first 3D transistor includes a 3D semiconductor body and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode consists of metal, and the gate dielectric has a 1.8nm and thickness between 10nm.

In another aspect, a memory device includes an array of memory cells and input/output (I/O) circuitry coupled to the array of memory cells and configured to interface the array of memory cells with a memory controller. The I/O circuit includes 3D transistors.

In yet another aspect, a system includes a memory element configured to store data. The memory element includes an array of memory cells and I/O circuitry coupled to the array of memory cells and configured to interface the array of memory cells with a memory controller. The I/O circuit includes 3D transistors. The system also includes a memory controller coupled to the memory element and configured to control the array of memory cells through the I/O circuit.

100:3D memory components

101:3D memory components

102: The first semiconductor structure

104: Second semiconductor structure

106: Bonding interface

200: memory components

201: memory cell array

202: Peripheral circuit

204: block 204

208: 3D NAND memory string

210: Source select gate (SSG), SSG transistor

212: drain selection gate (DSG), DSG transistor

213: DSG line

214: source line (SL), source line

215: SSG line

216: bit line

218: character line

220: column

304: page buffer

306: row decoder/bit line driver

308: column decoder / word line driver

310: voltage generator

312: control logic

314: register

316: Interface (I/F)

318: data bus

400: planar transistor

402: base

404: Trench isolation

406: Source and drain

408:Gate structure

410: channel

500:3D Transistor

502: base

504: Trench isolation

505: Semiconductor body

506: source and drain

508:Gate structure

602: Gate dielectric

604: gate electrode

800:3D memory components

801: 3D memory components

802: The first semiconductor structure

803:Second semiconductor structure

804: Second semiconductor structure

805: First semiconductor structure

806: Bonding interface

807: Bonding interface

808: base

809: base

810: component layer

811: memory stack

812: The first peripheral circuit

813: conductive layer

814: The second peripheral circuit

815: dielectric layer

816:Transistor

817:3D NAND memory string

818:transistor

820: interconnect layer

822: Bonding layer

824: Bonding contacts

826: Bonding layer

827:Interconnect layer

828: Bonding contacts

829: Bonding layer

830: Interconnect layer

832:Memory stack

833: Semiconductor layer

834: conductive layer

835: The first peripheral circuit

836: dielectric layer

837: peripheral circuit

838:3D NAND memory string

839: 3D Transistor

841: planar transistor

843:Pad output interconnection layer

845: contact pad

847: contact

848:Semiconductor layer

850:Pad output interconnection layer

852: Contact pad

853: Bonding contacts

854: contact

855: Bonding contacts

857:Interconnect layer

860: Trench isolation

861: Trench isolation

862: Trench isolation

863: Trench isolation

880: bit line

882: public plate

886:DRAM selection transistor

888:capacitor

890: DRAM cell

899: 3D memory components

901: Low Low Voltage (LLV) Source, LLV Source

903: Low Voltage (LV) Source, LV Source

905: High voltage (HV) source, HV source

1100: 3D Transistor

1102: base

1103: trench isolation

1104: 3D Semiconductor Body

1106: source and drain

1107: gate dielectric

1108:Gate structure

1109: gate electrode

1200: planar transistor

1202: base

1203: Trench isolation

1206: source and drain

1207: planar gate dielectric

1208:Gate structure

1209: gate electrode

1402: Subpage buffer circuit

1404:Serial driver

1406: Local character line

1502: plane

1900: 3D memory components

1902: First semiconductor structure

1904: Second semiconductor structure

1905: character line

1906: Memory stack

1907: Dielectric layer

1908: Ladder structure

1910: 3D NAND memory string

1912: word line contacts

1914: Serial Driver

1915: Bonding interface

2000: 3D Transistor

2002: Base

2003: Trench isolation

2004: 3D semiconductor body

2006: Source and sink

2007: Gate dielectric

2008:Gate structure

2009: Gate electrode

2100: 3D Transistor

2102: base

2104: 3D Semiconductor Body

2106: source and drain

2107: gate dielectric

2108:Gate structure

2109: gate electrode

2110: Drift Zone

2201: The first area

2202: Silicon substrate

2203: Second area

2204: Trench isolation

2205: The third area

2206: sacrificial layer

2208: 3D semiconductor body

2209: Groove

2210: gate dielectric layer

2211: gate dielectric layer

2212: gate electrode layer

2214: gate electrode

2215: gate electrode

2217: source and drain

2219: 3D Semiconductor Body

2300: method

2302: Operation

2304: Operation

2306: Operation

2308: Operation

2310: Operation

2312: Operation

2314: Operation

2400: method

2401: method

2402: Operation

2403: Operation

2405: Operation

2406: Operation

2408: Operation

2410: Operation

The drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one of ordinary skill in the relevant art to make and use the disclosure.

1A shows a schematic diagram of a cross-section of a 3D memory element according to some aspects of the present disclosure.

FIG. 1B shows a schematic diagram of a cross-section of another 3D memory element according to some aspects of the present disclosure.

2 shows a schematic circuit diagram of a memory element including peripheral circuitry, according to some aspects of the present disclosure.

3 illustrates a block diagram of a memory element including an array of memory cells and peripheral circuitry, according to some aspects of the present disclosure.

4 illustrates a perspective view of a planar transistor according to some aspects of the present disclosure.

5 illustrates a perspective view of a 3D transistor according to some aspects of the present disclosure.

6A and 6B illustrate side views of two cross-sections of the 3D transistor in FIG. 5, according to some aspects of the present disclosure.

7A-7I illustrate side views of cross-sections of various 3D transistors according to various aspects of the present disclosure.

8A shows a side view of a cross section of a 3D memory element according to some aspects of the present disclosure.

8B shows a side view of a cross-section of another 3D memory element according to some aspects of the present disclosure.

8C shows a side view of a cross-section of yet another 3D memory element according to some aspects of the present disclosure.

9 shows a block diagram of peripheral circuits supplied with various voltages, according to some aspects of the present disclosure.

10 illustrates a block diagram of a memory element including input/output (I/O) circuitry in accordance with some aspects of the present disclosure.

11A and 11B illustrate perspective and side views, respectively, of a 3D transistor in the I/O circuit of FIG. 10 in accordance with some aspects of the present disclosure.

12A and 12B show a perspective view and a side view, respectively, of a planar transistor.

13 shows a block diagram of a memory element including a word line driver and a page buffer in accordance with some aspects of the present disclosure.

FIG. 14 shows a schematic circuit diagram of the word line driver and page buffer in FIG. 13 according to some aspects of the present disclosure.

15 shows a schematic plan view of a memory element with a plurality of planes and page buffers, according to some aspects of the present disclosure.

FIG. 16 illustrates a memory cell array with a page cache Schematic plan view of the memory elements of the peripheral circuits of the puncher and word line driver.

Figure 17 shows the design layout of planar transistors in word line drivers or page buffers.

FIG. 18 illustrates a design layout of 3D transistors in the word line driver or page buffer in FIG. 13 according to some aspects of the present disclosure.

19 illustrates a side view of a cross-section of a 3D memory element including a string driver with 3D transistors, according to some aspects of the present disclosure.

20A and 20B illustrate perspective and side views, respectively, of a 3D transistor in the page buffer of FIG. 13 in accordance with some aspects of the present disclosure.

21A and 21B illustrate a perspective view and a side view, respectively, of a 3D transistor in the word line driver of FIG. 13 in accordance with some aspects of the present disclosure.

22A-22J illustrate a fabrication process for forming a 3D transistor according to some aspects of the present disclosure.

23 shows a flowchart of a method for forming an exemplary 3D memory element according to some aspects of the present disclosure.

24A shows a flowchart of a method for forming a 3D transistor according to some aspects of the present disclosure.

24B shows a flowchart of another method for forming a 3D transistor in accordance with aspects of the present disclosure.

25 illustrates a block diagram of an example system with memory elements, according to some aspects of the present disclosure.

26A shows a view of an example memory card with memory elements according to some aspects of the present disclosure.

26B shows a view of an example solid-state drive (SSD) with memory elements, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the drawings.

While specific configurations and arrangements are discussed, it should be understood that this is done for illustration purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the present disclosure can also be used in various other applications. Functional and structural features as described in this disclosure may be combined, adjusted and modified with each other and in ways not specifically shown in the drawings, such that such combinations, adjustments and modifications are within the scope of this disclosure.

In general, a term can be understood, at least in part, from its usage in context. For example, the term "one or plural" as used herein may be used to describe any feature, structure or characteristic in the singular sense or may be used to describe a feature, structure or combination of features in the plural sense, depending at least in part on the context. Similarly, terms such as "a", "an" or "the" may equally be read to express singular usage or to express plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of other factors not necessarily explicitly described, again depending at least in part on context.

It should be readily understood that the meanings of "on", "above" and "over" in this disclosure should be interpreted in the broadest possible manner, such that "on" not only means "directly on" but also includes the meaning of "on" with intermediate features or layers in between, and "on" or "over" not only means "on" or "over" but can also include "on" without intervening features or layers. "above" or "on something" (ie, directly on something).

In addition, for ease of description, spatially relative terms such as "under", "beneath", "under", "above", "on", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to those shown in the drawing Beyond orientation, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic or a sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. A layer may extend across the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of transverse planes at the top and bottom surfaces. Layers may extend laterally, vertically and/or along the tapered surface. A substrate can be a layer, can include one or more layers, and/or can have one or more layers thereon, above, and/or below. A layer may include a plurality of layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

Complementary metal-oxide-semiconductor (CMOS) technology nodes for peripheral circuits of memory devices such as NAND flash memory are less advanced (e.g., 60nm and above) than logic devices such as microprocessors because memory peripheral circuits require low cost and low leakage current (also known as off-state current I _off ). With the development of 3D memory devices (eg, 3D NAND flash memory devices), more stacked layers (eg, word lines) require more peripheral circuits for operating the 3D memory devices, which in turn requires smaller cell sizes of the peripheral circuits. For example, the number and/or size of page buffers needs to be increased to match the increased number of memory units. In some cases, the die area occupied by the page buffer may become dominant in 3D NAND flash memory, for example, exceeding 50% of the total die area. In another example, the number of string drivers in the word line driver is proportional to the number of word lines in the 3D NAND flash memory. Therefore, the continuous increase of word lines also increases the area occupied by word line drivers, the complexity of metal wiring, and sometimes even increases the number of metal layers. Furthermore, in some 3D memory devices, where the memory cell array and peripheral circuits are fabricated on different substrates and bonded together, the increasing peripheral circuit area, especially the page buffer area, has become a bottleneck in reducing the total die size.

However, scaling down the peripheral circuit size following the advanced technology node trend for logic components would result in significant cost increases and higher leakage currents, which are undesirable for memory components. In addition, since 3D NAND flash memory devices require relatively high voltages (e.g., higher than 5V) in certain memory operations (e.g., programming and erasing), unlike logic devices, which can lower their operating voltages as CMOS technology nodes advance, the voltage supplied to peripheral circuits of the memory cannot be reduced. Therefore, it becomes unfeasible to scale down the memory peripheral circuit size by following the trend of developing CMOS technology nodes such as common logic elements.

On the other hand, there is an increasing demand for higher I/O speeds of 3D NAND flash memory, which requires higher saturation drain current (I _dsat , also known as on-state current I _on ) of transistors used in memory I/O circuits. However, as the saturated drain current continues to increase, planar transistors typically used in existing memory peripheral circuits (eg, I/O circuits) suffer from high leakage current, which is also undesirable for memory devices.

In conclusion, the continuous advancement of memory components such as 3D NAND flash memory simultaneously requires high speed, low leakage current, high voltage and small size of memory peripheral circuits without increasing cost, which has become more and more challenging. Neither the full planar transistor solutions used in existing memory peripheral circuits nor the advanced CMOS technology node solutions used in logic components can meet the above requirements at the same time.

To address one or more of the above problems, this disclosure introduces a solution in which at least some memory peripheral circuits, such as I/O circuits, page buffers, and word line drivers Actuators, using 3D transistors (also known as non-planar transistors) instead of traditional planar transistors. In some embodiments, since the manufacturing process of the 3D transistors disclosed herein is compatible with planar transistors, planar transistors and 3D transistors are fabricated in the same process flow to achieve a hybrid configuration of memory peripheral circuits with both 3D transistors and planar transistors.

Compared with planar transistors, 3D transistors can have larger gate control areas to achieve better channel control with smaller subthreshold swings. During the off-state, the leakage current of the 3D transistor is well reduced significantly due to the complete depletion of the channel. Therefore, memory peripheral circuits (eg, I/O circuits) using 3D transistors instead of planar transistors can achieve much better speed (saturation drain current)/leakage performance. For example, according to some studies done by the inventors, with the same size and the same leakage current, the saturated drain current of a 3D transistor can be more than twice (eg, 3 times) that of a planar transistor.

In addition to the increased switching speed due to the high saturation drain current, the memory peripheral circuit size can also be reduced by replacing the planar transistors with 3D transistors. For example, according to some studies done by the inventors, under the same size and leakage current, the saturation drain current of a 3D transistor can be more than twice (eg, 3 times) that of a planar transistor. Therefore, for certain memory peripheral circuits where size reduction is more desirable than speed increase, such as page buffers and word line drivers, the size of the peripheral circuits can be reduced while maintaining the same leakage and saturation drain currents. Furthermore, according to some studies by the inventors, a simple solution to reduce the transistor size of planar transistors is not feasible because the leakage current increases drastically due to the narrow channel effect, for example, when the gate width is below 180nm.

On the other hand, in order to meet the low leakage current, high voltage and low cost requirements of memory peripheral circuits, compared with logic elements, less advanced CMOS technology nodes (eg, above 14nm) can be used to fabricate the 3D transistors disclosed herein. For example, while advanced CMOS technology nodes (eg, less than 22nm) can reduce transistor size, the voltage must be reduced (eg, to 0.9V) to avoid increasing leakage current. However, for memory devices that need to operate at certain voltage levels during memory operation For memory peripheral circuits, the voltage drop is unacceptable. In addition, advanced CMOS technology nodes and associated processes and structures, such as stressors for strain control and high-k (high-K)/metal gate (HKMG), may increase manufacturing complexity and lower production yield, thus increasing cost, which may not be suitable for cost-sensitive memory peripheral circuits.

Consistent with the scope of the present disclosure, according to some aspects of the present disclosure, peripheral circuits with 3D transistors and memory cell arrays can be formed on different wafers and bonded together in a face-to-face manner. Therefore, the thermal budget of manufacturing the memory cell array does not affect the manufacturing of peripheral circuits. For existing memory components where the peripheral circuitry and the memory cell array are fabricated on the same wafer, the reduction in transistor size is limited by the thermal budget of forming the memory cell array. In contrast, in the present disclosure, the size of transistors (eg, 3D transistors) forming memory peripheral circuits can be reduced without being limited by the thermal budget of the memory cell array. In addition, in some embodiments, after bonding, some peripheral circuits with reduced 3D transistor size (e.g., a string driver of a word line driver) can be arranged in a ladder structure facing a memory cell array formed on another substrate, thereby simplifying metal wiring.

FIG. 1A shows a schematic diagram of a cross-section of a 3D memory element 100 according to some aspects of the present disclosure. 3D memory element 100 represents an example of a bonded wafer. The components of the 3D memory device 100 (eg, the memory cell array and peripheral circuitry) may be formed separately on different substrates and then bonded to form a bonded wafer. The 3D memory element 100 may comprise a first semiconductor structure 102 comprising an array of memory cells (memory cell array). In some embodiments, the array of memory cells includes an array of NAND flash memory cells. For convenience of description, a NAND flash memory cell array may be used as an example to describe the memory cell array in the present disclosure. However, it should be understood that the memory cell array is not limited to NAND flash memory cell arrays, and may include any other suitable type of memory cell arrays, such as dynamic random access memory (DRAM) cell arrays, static random access memory (SRAM) cell arrays, NOR flash memory cell arrays, phase change memory (PCM) cell arrays, An array of resistive memory cells, an array of magnetic memory cells, an array of spin transfer torque (STT) memory cells, to name a few, or any combination thereof.

The first semiconductor structure 102 may be a NAND flash memory element in which the memory cells are provided in the form of an array of 3D NAND memory strings and/or an array of two-dimensional (2D) NAND memory cells. NAND memory cells can be organized into pages or fingers, which are then organized into blocks, with each NAND memory cell electrically connected to a separate wire called a bit line (BL). All cells having the same vertical position in a NAND memory cell can be electrically connected by a word line (WL) through a control gate. In some implementations, a plane contains a certain number of blocks electrically connected by the same bit line. The first semiconductor structure 102 may include one or a plurality of planes, and peripheral circuits required to perform all read/program (write)/erase operations may be included in the second semiconductor structure 104 .

In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating gate transistor. According to some embodiments, the 2D NAND memory cell array includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (eg, 32 to 128 memory cells) connected in series (similar to NAND gates) and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane (in 2D) on the substrate. In some embodiments, the array of NAND memory cells is a 3D array of NAND memory strings, each of which extends vertically (in 3D) through a stacked structure (eg, memory stack) above a substrate. Depending on the 3D NAND technology (eg, the number of layers/levels in the memory stack), a 3D NAND memory string typically includes 32 to 256 NAND memory cells, each of which includes a floating gate transistor or a charge trapping transistor.

As shown in FIG. 1A , the 3D memory device 100 may further include a second semiconductor structure 104 including peripheral circuits of the memory cell array of the first semiconductor structure 102 . Peripheral circuitry (also known as control and sense circuitry) may include any suitable digital, analog, and/or mixed-signal circuitry for facilitating operation of the memory cell array. For example, peripheral circuits may include page buffers, decoders (e.g., column decode decoders and row decoders), sense amplifiers, drivers (e.g., word line drivers), I/O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the foregoing functional circuits (e.g., subcircuits), or any active or passive component of a circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits in the second semiconductor structure 104 use CMOS technology, eg, they can be implemented in logic process (eg, 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, etc. technology nodes). As described in detail above and below, consistent with the scope of the present disclosure, technology nodes for fabricating peripheral circuits in the second semiconductor structure 104 are above 22nm in order to reduce leakage current, maintain certain voltage levels (e.g., 1.2V and above), and reduce cost.

As shown in FIG. 1A , the 3D memory device 100 further includes a bonding interface 106 vertically between the first semiconductor structure 102 and the second semiconductor structure 104 . As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 may be fabricated separately (and in some embodiments in parallel) such that the thermal budget for fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 does not limit the process for fabricating the other of the first semiconductor structure 102 and the second semiconductor structure 104. In addition, a large number of interconnections (e.g., bonding contacts) can be formed through the bonding interface 106 to make direct short-distance (e.g., micron-scale) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, rather than long-distance (e.g., millimeter or centimeter-scale) die-to-die data busses on a circuit board such as a printed circuit board (PCB), thereby eliminating die interface delays and enabling high-speed I/O throughput with reduced power consumption. Data transfer between the memory cell array in the first semiconductor structure 102 and peripheral circuits in the second semiconductor structure 104 may be performed through interconnections (eg, bonding contacts) across the bonding interface 106 . By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the wafer size can be reduced and the memory cell density can be increased.

It should be understood that the relative positions of the stacked first semiconductor structure 102 and the second semiconductor structure 104 are not limited. FIG. 1B shows a schematic diagram of a cross-section of another exemplary 3D memory element 101 according to some embodiments. Unlike the 3D memory element 100 in FIG. 1A, in which the second semiconductor structure 104 including the peripheral circuit is above the first semiconductor structure 102 including the memory cell array, in the 3D memory element 101 in FIG. 1B, the first semiconductor structure 102 including the memory cell array is above the second semiconductor structure 104 including the peripheral circuit. However, according to some embodiments, the bonding interface 106 is vertically formed between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D memory element 101, and the first semiconductor structure 102 and the second semiconductor structure 104 are vertically joined by bonding (eg, hybrid bonding). Hybrid bonding, also known as "metal/dielectric hybrid bonding", is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-metal (e.g., Cu-to-Cu) bonding and dielectric-dielectric (e.g., _SiO2 -to- _SiO2 ) bonding. Data transfer between the memory cell array in the first semiconductor structure 102 and peripheral circuits in the second semiconductor structure 104 may be performed through interconnections (eg, bonding contacts) across the bonding interface 106 .

FIG. 2 shows a schematic circuit diagram of a memory element 200 including peripheral circuitry, according to some aspects of the present disclosure. The memory element 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The 3D memory elements 100 and 101 may be an example of the memory element 200 in which the memory cell array 201 and the peripheral circuit 202 may be included in the first semiconductor structure 102 and the second semiconductor structure 104, respectively. The memory cell array 201 may be an array of NAND flash memory cells, where the memory cells 206 are provided in the form of an array of 3D NAND memory strings 208, each 3D NAND memory string extending vertically above a substrate (not shown). In some embodiments, each 3D NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the area of the memory cell 206 . Each memory cell 206 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory cell 206 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state of "0" may correspond to a first voltage range, while a second memory state of "1" may correspond to a second voltage range. pressure range. In some embodiments, each memory cell 206 is a multi-level cell (MLC) capable of storing more than a single data bit in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a tri-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to use a range of possible nominal memory values. In one example, if each MLC memorizes two bits of data, the MLCs can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal memory values into the cell. A fourth nominal memory value is available for the erased state.

As shown in FIG. 2, each NAND memory string 208 may include a source select gate (SSG) 210 at its source terminal and a drain select gate (DSG) 212 at its drain terminal. SSG transistors 210 and DSG transistors 212 may be configured to enable selected NAND memory strings 208 (rows of the array) during read and program operations. In some implementations, the sources of the SSG transistors 210 of the 3D NAND memory strings 208 in the same block 204 are coupled to ground through the same source line (SL) 214 (eg, a common SL). According to some embodiments, the DSG transistor 212 of each 3D NAND memory string 208 is coupled to a corresponding bit line 216 from which data can be read or programmed via an output bus (not shown). In some embodiments, each 3D NAND memory string 208 is configured by applying a select voltage (e.g., above the threshold voltage of DSG transistor 212) or a deselect voltage (e.g., 0 V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and/or by applying a select voltage (e.g., above the threshold voltage of SSG transistor 210) or deselect voltage (e.g., 0 V) to the corresponding SSG transistor via one or more SSG lines 215. 210, while being selected or not selected.

As shown in FIG. 2 , 3D NAND memory string 208 may be organized into blocks 204 , each of which may have a common source line 214 . In some implementations, each block 204 is the basic unit of data for an erase operation, ie, all memory cells 206 on the same block 204 are erased simultaneously. The memory cells 206 may be coupled by word lines 218 that select which column of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a column 220 of memory cells 206, It is the basic unit of data used for programming and reading operations. Each word line 218 may include a plurality of control gates (gate electrodes) at each memory cell 206 in a corresponding column 220 and a gate line coupled to the control gates.

The peripheral circuit 202 can be coupled to the memory cell array 201 through the bit line 216 , the word line 218 , the source line 214 , the SSG line 215 and the DSG line 213 . As noted above, peripheral circuitry 202 may include any suitable circuitry for facilitating operation of memory cell array 201 by applying and sensing voltage signals and/or current signals to and from each target memory cell 206 via bit lines 216 via word lines 218, source lines 214, SSG lines 215, and DSG lines 213. The peripheral circuit 202 may include various types of peripheral circuits formed using MOS technology. For example, FIG. 3 shows some exemplary peripheral circuits 202, including page buffer 304, row decoder/bitline driver 306, column decoder/wordline driver 308, voltage generator 310, control logic 312, registers 314, interface (I/F) 316, and data bus 318. It should be understood that in some examples, additional peripheral circuitry 202 may also be included.

The page buffer 304 may be configured to buffer data read from or programmed into the memory cell array 201 according to control signals of the control logic 312 . In one example, the page buffer 304 can store a page of program data (write data) to be programmed into a column 220 of the memory cell array 201 . In another example, the page buffer 304 also performs a program verify operation to ensure that data has been correctly programmed into the memory cells 206 coupled to the selected word line 218 .

Column decoder/word line driver 308 may be configured to be controlled by control logic 312 and select or deselect blocks 204 of memory cell array 201 and select or deselect word lines 218 of selected blocks 204 . Column decoder/word line driver 308 may be further configured to drive memory cell array 201 . For example, column decoder/wordline driver 308 may drive memory cells 206 coupled to selected wordline 218 using wordline voltages generated from voltage generator 310 . In some implementations, column decoder/wordline driver 308 may include decoders and string drivers (drive transistors) coupled to local wordlines and wordlines 218 .

The voltage generator 310 may be configured to be controlled by the control logic 312 and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, and verify voltages) to be provided to the memory cell array 201 . In some implementations, the voltage generator 310 is part of a voltage source that provides various levels of voltage to the various peripheral circuits 202, as described in detail below. Consistent with the scope of this disclosure, in some embodiments the voltage provided by voltage generator 310 to, for example, column decoder/word line driver 308 and page buffer 304 is above certain levels sufficient to perform memory operations. For example, the voltage provided to page buffer 304 may be between 2V and 3.3V, such as 3.3V, and the voltage provided to column decoder/wordline driver 308 may be greater than 3.3V, such as between 3.3V and 30V.

Row decoder/bit line driver 306 may be configured to be controlled by control logic 312 and to select one or a plurality of 3D NAND memory strings 208 by applying bit line voltages generated from voltage generator 310 . For example, row decoder/bit line driver 306 may apply a row signal for selecting a set of N data bits from page buffer 304 to be output in a read operation.

Control logic 312 may be coupled to each peripheral circuit 202 and configured to control the operation of peripheral circuit 202 . Registers 314 may be coupled to control logic 312 and include status registers, command registers, and address registers for memory status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202 .

Interface 316 may be coupled to control logic 312 and configured to interface memory cell array 201 with a memory controller (not shown). In some implementations, the interface 316 acts as a control buffer to buffer and relay control commands received from the memory controller and/or host (not shown) to the control logic 312 and to buffer and relay status information received from the control logic 312 to the memory controller and/or host. Interface 316 may also be coupled to page buffer 304 and row decoder/bit line driver 306 via data bus 318 and act as an I/O interface and data buffer to buffer and relay programming data received from the memory controller and/or host to page buffer 304 and to buffer and relay read data from page buffer 304 to the memory controller and/or host. In some implementations, interface 316 and data bus 318 are peripheral Part of the I/O circuitry of circuit 202 .

Consistent with the scope of the present disclosure, at least one peripheral circuit 202 of the memory device 200 may have 3D transistors instead of planar transistors in order to simultaneously achieve high speed, low leakage current, high voltage, and small size without increasing cost. In some implementations, all planar transistors in each peripheral circuit 202 are replaced with 3D transistors. That is, the peripheral circuit 202 may not have planar transistors at all. In some embodiments, since the manufacturing process of the 3D transistors disclosed herein is compatible with planar transistors, planar transistors and 3D transistors are fabricated in the same process flow to achieve a hybrid configuration of memory peripheral circuits with both 3D transistors and planar transistors. That is, the peripheral circuit 202 may include planar transistors. For example, one or a plurality of peripheral circuits 202 may have 3D transistors, while other peripheral circuits 202 may still have planar transistors. It should be understood that in some examples, both 3D transistors and planar transistors may be used in the same peripheral circuit 202 . For example, FIG. 4 shows a perspective view of a planar transistor according to some aspects of the present disclosure, and FIG. 5 shows a perspective view of a 3D transistor according to some aspects of the present disclosure.

As shown in FIG. 4, the planar transistor 400 may be a MOS field effect transistor (MOSFET) on a substrate 402, which may include silicon (eg, single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. Note that the x-axis and y-axis have been added in FIG. 4 to further illustrate the spatial relationship of the components of the semiconductor element (eg, planar transistor 400 ). The base 402 includes two lateral surfaces (eg, top and bottom surfaces) extending laterally in the x-direction (lateral direction or width direction). As used herein, it is determined in the y-direction (vertical or thickness direction) relative to the base of the semiconductor element whether one component (e.g., layer or element) of the semiconductor element is "on," "over" or "below" (e.g., a layer or element) another component (e.g., layer or element) when the substrate (e.g., substrate 402) is located in the lowest plane of the semiconductor element (e.g., planar transistor 400) in the y-direction. The same concepts used to describe spatial relationships are applied in this disclosure.

Trench isolation 404 , such as shallow trench isolation (STI), may be formed in substrate 402 and between adjacent planar transistors 400 to reduce current leakage. Trench isolation 404 may comprise any suitable dielectric Dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or high-K dielectrics (eg, aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, a high-K dielectric material includes any dielectric having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, trench isolation 404 includes silicon oxide.

As shown in FIG. 4 , the planar transistor 400 may further include a gate structure 408 on the substrate 402 . In some embodiments, the gate structure 408 is on the top surface of the substrate 402 . Although not shown, gate structure 408 may include a gate dielectric on substrate 402 , ie, over and in contact with a top surface of substrate 402 . The gate structure 408 may also include a gate electrode on, ie, above and in contact with, the gate dielectric. The gate dielectric may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or high-K dielectric. In some embodiments, the gate dielectric includes silicon oxide, ie, gate oxide. The gate electrode may comprise any suitable conductive material, such as polysilicon, metal (eg, tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (eg, titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide. In some embodiments, the gate electrode comprises doped polysilicon, ie, gate polysilicon.

As shown in FIG. 4 , planar transistor 400 may also include a pair of source and drain 406 in substrate 402 . The source and drain 406 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). In plan view, the source and drain 406 may be separated by a gate structure 408 . That is, according to some embodiments, gate structure 408 is formed between source and drain 406 in plan view. When the gate voltage applied to the gate electrode of gate structure 408 is higher than the threshold voltage of planar transistor 400 , channel 410 of planar transistor 400 in substrate 402 may be formed laterally between source and drain 406 below gate structure 408 . As shown in FIG. 4 , gate structure 408 may be over and in contact with the top surface of the portion of substrate 402 (active region) in which channel 410 may be formed. That is, according to some embodiments, the gate structure 408 is in contact with only one side of the active region, ie in the plane of the top surface of the substrate 402 . Gate structure 408 also includes a gate dielectric (e.g., eg, gate oxide, not shown in Figure 4). It should be understood that, although not shown in FIG. 4 , planar transistor 400 may include additional components, such as wells and spacers.

As shown in FIG. 5, the 3D transistor 500 may be a MOSFET on a substrate 502, which may include silicon (eg, monocrystalline silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator SOI, or any other suitable material. In some embodiments, substrate 502 includes single crystal silicon. Trench isolation 504 such as an STI may be formed in the substrate 502 and between adjacent 3D transistors 500 to reduce current leakage. Trench isolation 504 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-K dielectrics (eg, aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, a high-K dielectric material includes any dielectric having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, trench isolation 404 includes silicon oxide.

As shown in FIG. 5 , unlike the planar transistor 400 , the 3D transistor 500 may further include a 3D semiconductor body 505 above a substrate 502 . That is, in some embodiments, the 3D semiconductor body 505 extends at least partially above the top surface of the substrate 502 to expose not only the top surface of the 3D semiconductor body 505 but also two side surfaces. As shown in FIG. 5 , for example, the 3D semiconductor body 505 may be a 3D structure, also referred to as a "fin", to expose three sides thereof. As described below with respect to the manufacturing process of the 3D transistor 500 , according to some embodiments, the 3D semiconductor body 505 is formed from the substrate 502 and thus has the same semiconductor material as the substrate 502 . In some embodiments, the 3D semiconductor body 505 includes monocrystalline silicon. Since channels can be formed in the 3D semiconductor body 505 , the 3D semiconductor body 505 (eg, fins) opposite the base 502 can be considered as the active region of the 3D transistor 500 .

FIG. 6A illustrates a side view of a cross-section of the 3D transistor 500 in FIG. 5 in the AA plane, according to some aspects of the present disclosure. FIG. 6B illustrates a side view of a cross-section in plane BB of the 3D transistor 500 of FIG. 5 , according to some aspects of the present disclosure. As shown in FIGS. 5 and 6B , the 3D transistor 500 may further include a gate structure 508 on the substrate 502 . Unlike the planar transistor 400 where the gate structure 408 is only in contact with one side of the active region, i.e. in the plane of the top surface of the substrate 402, the gate structure of the 3D transistor 500 508 may be in contact with multiple sides of the active region, ie in multiple planes of the top and side surfaces of the 3D semiconductor body 505 . That is, the active region of the 3D transistor 500 , ie the 3D semiconductor body 505 , may be at least partially surrounded by the gate structure 508 .

The gate structure 508 may comprise a gate dielectric 602 over the 3D semiconductor body 505 , eg in contact with the top surface and both side surfaces of the 3D semiconductor body 505 . The gate structure 508 may also include a gate electrode 604 over and in contact with the gate dielectric 602 . The gate dielectric 602 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or high-K dielectric. In some embodiments, gate dielectric 602 includes silicon oxide, ie, gate oxide. The gate electrode 604 may comprise any suitable conductive material, such as polysilicon, metal (eg, W, Cu, Al, etc.), metal compound (eg, TiN, TaN, etc.), or silicide. In some embodiments, the gate electrode 604 includes doped polysilicon, ie, gate polysilicon.

As shown in FIGS. 5 and 6A , the 3D transistor 500 may further include a pair of source and drain electrodes 506 (doped regions, also called source electrodes and drain electrodes) in the substrate 502 . The source and drain 506 may be doped with any suitable P-type dopant, such as B or Ga, or any suitable N-type dopant, such as P or Ar. In plan view, the source and drain 506 may be separated by a gate structure 508 . That is, according to some embodiments, gate structure 508 is formed between source and drain 506 in plan view. As a result, a plurality of channels of the 3D transistor 500 in the 3D semiconductor body 505 may be formed laterally between the source and the drain 506 surrounded by the gate structure 508 when the gate voltage applied to the gate electrode 604 of the gate structure 508 is higher than the threshold voltage of the 3D transistor 500. Unlike the planar transistor 400 in which only a single channel can be formed on the top surface of the substrate 402 , a plurality of channels can be formed on the top and side surfaces of the 3D semiconductor body 505 in the 3D transistor 500 . In some embodiments, the 3D transistor 500 includes a multi-gate transistor. That is, unlike the planar transistor 400 which includes only a single gate, the 3D transistor 500 may include a plurality of gates on the sides of the 3D semiconductor body 505 due to the 3D structure of the 3D semiconductor body 505 and the gate structure 508 surrounding the sides of the 3D semiconductor body 505. As a result, compared to the planar transistor 400, the 3D transistor 500 can have a larger gate control area while achieving better channel control with a smaller subthreshold swing. During the off-state, the leakage current (I _off ) of the 3D transistor 500 may well be significantly reduced since the channel is fully depleted. On the other hand, the size of the 3D transistor 500 can be significantly reduced from the planar transistor 400 while still maintaining the same electrical properties (eg, channel control, subthreshold swing, and/or leakage current) as the planar transistor 400 .

It should be appreciated that while, as noted above, 3D transistors (e.g., FinFETs) are also used in logic devices (e.g., microprocessors) using advanced technology nodes (e.g., less than 22nm), due to the different requirements placed on the transistors between the logic device and memory peripheral circuits, the design of the 3D transistor 500 may also exhibit unique features not seen in 3D transistors used in logic devices. From a materials perspective, in some embodiments, instead of 3D transistors (e.g., FinFETs) in logic devices using advanced technology nodes (e.g., less than 22nm), which use HKMG (i.e., high-K dielectric for the gate dielectric, and metal for the gate electrode), the 3D transistor 500 in memory peripheral circuits uses gate polysilicon and gate oxide instead of HKMG to reduce manufacturing cost and complexity.

From a transistor size perspective, 3D transistors 500 in memory peripheral circuits may not follow the same trend of scaling down as logic elements (eg, microprocessors) using advanced technology nodes (eg, less than 22nm). The difference in size may allow the 3D transistor 500 to be used at higher voltages (e.g., 3.3V and above) that are typically not used and undesirable for 3D transistors (e.g., FinFETs) in logic elements using advanced technology nodes (e.g., less than 22nm). The difference in size can also significantly reduce the manufacturing cost and complexity of the 3D transistor 500 in memory peripheral circuits.

For example, in some embodiments, as shown in Figure 6B, the width (W) of the 3D semiconductor body 505 is greater than 10 nm. For example, the width of the 3D semiconductor body 505 can be between 30nm and 1000nm (e.g., 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, by any of these values). any range bounded by the lower limit of either value, or in any range bounded by any two of these values). The width of 3D transistor 500 may be significantly larger (e.g., one or more times or even one or more orders of magnitude) than the width of 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22 nm).

In some embodiments, as shown in Figure 6B, the height (H) of the 3D semiconductor body 505 is greater than 40 nm. For example, the height of the 3D semiconductor body 505 may be between 50nm and 1000nm (e.g., 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, any range bounded by a lower limit for any one of these values, or within any range defined by any two of these values). in any range defined by the value). The height of 3D transistor 500 may be significantly greater (e.g., one or more times or even one or more orders of magnitude) than the height of 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22 nm).

In some embodiments, as shown in Figure 6B, the thickness (T) of the gate dielectric 602 is greater than 1.8 nm. For example, the thickness of gate dielectric 602 may be between 2 nm and 100 nm (e.g., 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values) . The thickness of the gate dielectric 602 may be significantly greater (e.g., one or more times or even one or multiple orders of magnitude) than the thickness of 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22 nm). As a result, with thicker gate dielectric 602, 3D transistor 500 can withstand higher voltages (e.g., 3.3V and higher) than 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22nm).

In some embodiments, as shown in FIG. 6A , the channel length (L) of the 3D transistor 500 is greater than 30 nm. For example, the channel length of 3D transistor 500 can be between 50nm and 1500nm (for example, 50nm nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, 1100nm, 1200nm, 1300nm, 1400nm, 1500nm, any range bounded by a lower limit of any of these values, or within any of these values in any range bounded by any two values). The channel length of 3D transistor 500 may be significantly greater (e.g., one or more times or even one or multiple orders of magnitude) than the channel length of 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22 nm).

It should be understood that, although not shown in Figures 5, 6A and 6B, the 3D transistor 500 may include additional components, such as wells and spacers. It should also be appreciated that unlike 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22nm), which include stressors at the source and drain including GaAs or SiGe (aka strained elements) or using strained silicon technology to apply strain in the channel to increase carrier mobility, 3D transistor 500 may not include stressors at source and drain 506 and/or may not be at 3 due to its relatively large size and to reduce manufacturing complexity and cost. D Strained semiconductor material is used in the semiconductor body 505 .

It should also be understood that FIGS. 5, 6A, and 6B illustrate one example of a 3D transistor (e.g., a FinFET) that may be used in memory peripheral circuitry, and that any other suitable 3D transistor (e.g., a gate-all-around (GAA) FET) may also be used in memory peripheral circuitry. For example, FIGS. 7A-7I illustrate side views of cross-sections of various 3D transistors according to various aspects of the present disclosure. Similar to 3D transistor 500 in FIGS. 5, 6A and 6B, each 3D transistor in FIGS. 7A-7I may be a multi-gate transistor with a 3D semiconductor body above a substrate and a gate structure contacting more than one side of the 3D semiconductor body. The gate structure may include a gate dielectric and a gate electrode. For example, Figures 7A, 7B, and 7C show gate-all-around (GAA) silicon-off (SON) transistors, multiple independent gate FETs (MIGETs), and FinFETs, respectively, each of which is considered a double-gate transistor. For example, Figures 7D, 7E, and 7F illustrate a tri-gate FET, a Π-gate FET, and an Ω-FET, respectively, each of which is considered a tri-gate transistor. For example, Figures 7G, 7H, and 7I show a quad-gate FET, a cylindrical FET, and a multi-bridge/stacked nanowire FET, respectively, each of which Both are considered wrap-around gate transistors. As can be seen in Figures 7A-7I, the cross-section of the 3D semiconductor body may have a square shape, a rectangular shape (or trapezoidal shape), a circular (or elliptical shape) or any other suitable shape in side view. It should be understood that, consistent with the scope of the present disclosure, for a 3D semiconductor body whose cross-section has a circular or elliptical shape, the 3D semiconductor body may still be considered to have a plurality of sides such that the gate structure is in contact with more than one side of the 3D semiconductor body. It should be understood that in some examples, a plurality of 3D transistors (eg, a plurality of FinFETs) may share, ie be formed on, a single 3D semiconductor body (eg, a fin). For example, a plurality of FinFETs may be arranged in parallel on the same fin, and no trench isolation (eg, STI) may be formed between the plurality of FinFETs sharing the same fin to separate the FinFETs.

As described above with respect to FIGS. 1A and 1B , 3D transistor 500 may be one example of a transistor in a peripheral circuit of a second semiconductor structure 104 bonded to a first semiconductor structure 102 having an array of memory cells. For example, Figure 8A shows a side view of a cross-section of an exemplary 3D memory element 800, according to some embodiments. It should be understood that FIG. 8A is for illustrative purposes only, and may not necessarily reflect actual component structures (eg, interconnections) in reality. As an example of the 3D memory element 100 described above with respect to FIG. 1A , the 3D memory element 800 is a bonded wafer comprising a first semiconductor structure 802 and a second semiconductor structure 804 stacked on top of the first semiconductor structure 802 . According to some embodiments, the first semiconductor structure 802 and the second semiconductor structure 804 are bonded at a bonding interface 806 therebetween. As shown in FIG. 8A, the first semiconductor structure 802 can include a substrate 808, which can include silicon (eg, single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

The first semiconductor structure 802 may include an element layer 810 over a substrate 808 . In some embodiments, the component layer 810 includes a first peripheral circuit 812 (eg, page buffer 304, word line driver 308, and/or I/O circuits 316 and 318), and a second peripheral circuit 814 (eg, control logic 312, registers 314, etc.). In some embodiments, the first peripheral circuit 812 includes a plurality of 3D transistors 816 (eg, corresponding to the 3D transistor 500 ), and the second peripheral circuit 814 includes a plurality of planar transistors 818 (eg, corresponding to planar transistor 400). Trench isolations 860 and 862 (eg, STIs) and doped regions (eg, wells, sources, and drains of transistors 816 and 818 ) may also be formed on or in substrate 808 . In some embodiments, trench isolation 860 is on substrate 808 and laterally between two adjacent 3D transistors 816 in plan view, and trench isolation 862 extends into substrate 808 and laterally between two adjacent planar transistors 818 . In some embodiments, trench isolation 862 and trench isolation 860 have different depths (eg, their bottom surfaces are in different planes in the y-direction) because they separate different types of transistors (planar transistor 818 and 3D transistor 816 ), respectively. For example, as shown in FIG. 8A , trench isolation 862 may have a greater depth than trench isolation 860 . It should be understood that trench isolation 862 and trench isolation 860 have the same depth (eg, their bottom surfaces are in the same plane in the y-direction) in some examples, depending on different manufacturing processes.

In some embodiments, the first semiconductor structure 802 further includes an interconnect layer 820 above the device layer 810 to transmit electrical signals to and from the peripheral circuits 812 and 814 . Interconnect layer 820 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect via (VIA) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as mid-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnect layer 820 may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which interconnect lines and via contacts may be formed. That is, the interconnect layer 820 may include interconnect lines and via contacts in a plurality of ILD layers. In some implementations, components in component layer 810 are coupled to each other by interconnects in interconnect layer 820 . For example, peripheral circuitry 812 may be coupled to peripheral circuitry 814 through interconnect layer 820 .

As shown in FIG. 8A , the first semiconductor structure 802 may further include a bonding layer 822 at the bonding interface 806 and above the interconnect layer 820 and the device layer 810 . Bonding layer 822 may include a plurality of bonding contacts 824 and a dielectric that electrically isolates bonding contacts 824 . Bonding contacts 824 may include a conductive material. The remaining area of bonding layer 822 may be formed from a dielectric material. Bonding contacts 824 and surrounding dielectric in bonding layer 822 may be used for hybrid bonding. Similarly, as shown in FIG. 8A, the second semiconductor structure 804 may also include the first half Bonding layer 826 at bonding interface 806 of conductor structure 802 and above bonding layer 822 . Bonding layer 826 may include a plurality of bonding contacts 828 and a dielectric that electrically isolates bonding contacts 828 . Bonding contacts 828 may include a conductive material. The remaining area of bonding layer 826 may be formed from a dielectric material. Bonding contacts 828 and surrounding dielectric in bonding layer 826 may be used for hybrid bonding. According to some implementations, bonding contacts 828 make contact with bonding contacts 824 at bonding interface 806 .

The second semiconductor structure 804 may be bonded face-to-face on top of the first semiconductor structure 802 at the bonding interface 806 . In some embodiments, bonding interface 806 is disposed between bonding layers 822 and 826 as a result of hybrid bonding (also referred to as "metal/dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intervening layer such as solder or adhesive) and that can achieve both metal-metal bonding and dielectric-dielectric bonding. In some embodiments, bonding interface 806 is where bonding layers 822 and 826 meet and bond. In practice, the bonding interface 806 may be a layer with a certain thickness including the top surface of the bonding layer 822 of the first semiconductor structure 802 and the bottom surface of the bonding layer 826 of the second semiconductor structure 804 .

In some embodiments, the second semiconductor structure 804 also includes an interconnect layer 830 over the bonding layer 826 to transmit electrical signals. The interconnect layer 830 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 830 also include local interconnects, such as bit lines, bit line contacts, and word line contacts. The interconnect layer 830 may also include one or more ILD layers in which interconnect lines and via contacts may be formed. In some embodiments, the first peripheral circuit 812 is the page buffer 304 , and the 3D transistor 816 of the first peripheral circuit 812 is coupled to the bit line of the second semiconductor structure 804 . In some embodiments, the first peripheral circuit 812 is the wordline driver 308 , and the 3D transistor 816 of the first peripheral circuit 812 is coupled to the wordline (eg, the conductive layer 834 ) of the second semiconductor structure 804 .

In some embodiments, the second semiconductor structure 804 includes NAND flash memory elements, wherein the memory cells are provided in an array of 3D NAND memory strings 838 over the interconnect layer 830 and the bonding layer 826 . According to some embodiments, each 3D NAND memory string 838 extends vertically through the respective Pairs of conductive layers 834 and dielectric layers 836 are included. The stacked and interleaved conductive layers 834 and dielectric layers 836 are also referred to herein as a stack structure, eg, memory stack 832 . According to some embodiments, the alternating conductive layers 834 and dielectric layers 836 in the memory stack 832 alternate in the vertical direction. Each conductive layer 834 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrodes of the stacked conductive layer 834 may extend laterally as word lines, terminating at one or a plurality of ladder structures of the memory stack 832 .

In some embodiments, each 3D NAND memory string 838 is a "charge trapping" type of NAND memory string that includes a semiconductor channel and a memory film. In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trapping/memory layer"), and a barrier layer. Each 3D NAND memory string 838 may have a cylindrical shape (eg, columnar). According to some embodiments, the semiconductor channel of the memory film, the tunneling layer, the memory layer and the barrier layer are arranged in this order along the direction from the center of the pillar to the outer surface. In some implementations, the 3D NAND memory string 838 also includes a plurality of control gates (each being part of a word line). Each conductive layer 834 in the memory stack 832 can serve as a control gate for each memory cell of the 3D NAND memory string 838 .

In some embodiments, the second semiconductor structure 804 further includes a semiconductor layer 848 disposed over the memory stack 832 and the 3D NAND memory string 838 . The semiconductor layer 848 may be a thinned substrate on which the memory stack 832 and the 3D NAND memory string 838 are formed. In some embodiments, semiconductor layer 848 includes monocrystalline silicon. The semiconductor layer 848 may also include isolation and doped regions (eg, used as the array common source (ACS) of the 3D NAND memory string 838 , not shown). It should be understood that 3D NAND memory string 838 is not limited to a "charge trapping" type of 3D NAND memory string, and may be a "floating gate" type of 3D NAND memory string in other examples. The semiconductor layer 848 may comprise polysilicon as a source plate for a "floating gate" type of 3D NAND memory string.

As shown in FIG. 8A , the second semiconductor structure 804 may also include a solder bond over the semiconductor layer 848. The disk outputs the interconnection layer 850 . The pad output interconnect layer 850 may include interconnects in one or more ILD layers, such as contact pads 852 . The pad output interconnection layer 850 and the interconnection layer 830 may be formed on opposite sides of the semiconductor layer 848 . In some embodiments, the interconnects in the pad-out interconnection layer 850 may transmit electrical signals between the 3D memory element 800 and external circuitry, eg, for pad-out purposes. In some embodiments, the second semiconductor structure 804 further includes one or more contacts 854 extending through the semiconductor layer 848 to electrically connect the pad output interconnect layer 850 and the interconnect layers 830 and 820 . Thus, peripheral circuits 812 and 814 may be coupled to an array of 3D NAND memory strings 838 through interconnect layers 830 and 820 and bonding contacts 828 and 824 . That is, an array of 3D NAND memory strings 838 may be coupled across bonding interface 806 to 3D transistor 816 and planar transistor 818 . Additionally, peripheral circuits 812 and 814 and the array of 3D NAND memory strings 838 can be coupled to external circuitry through contact 854 and pad output interconnect layer 850 .

FIG. 8B illustrates a cross-section of another exemplary 3D memory element 801 in accordance with aspects of the present disclosure. It should be understood that FIG. 8B is for illustrative purposes only, and may not necessarily reflect actual component structures (eg, interconnections) in reality. As an example of the 3D memory element 101 described above with respect to FIG. 1B , the 3D memory element 801 is a bonded wafer comprising a second semiconductor structure 803 and a first semiconductor structure 805 stacked on top of the second semiconductor structure 803 . Similar to the 3D memory element 800 described above in FIG. 8A , the 3D memory element 801 represents an example of a bonded wafer in which the first semiconductor structure 805 and the second semiconductor structure 803 are formed separately and bonded in a face-to-face manner at the bonding interface 807 . It should be understood that details of similar structures (eg, materials, manufacturing processes, functions, etc.) in both 3D memory devices 800 and 801 may not be repeated below.

The second semiconductor structure 803 may include a substrate 809 and a memory stack 811 including alternating conductive layers 813 and dielectric layers 815 over the substrate 809 . In some embodiments, the array of 3D NAND memory strings 817 each extend vertically through the interleaved conductive layers 813 and dielectric layers 815 in the memory stack 811 above the substrate 809 . Each 3D NAND memory string 817 may include a semiconductor channel and a memory film. The 3D NAND memory string 817 may be a "charge trapping" type of 3D NAND Strings of memory or "floating gate" type 3D NAND memory strings.

In some embodiments, the second semiconductor structure 803 further includes an interconnection layer 827 above the memory stack 811 and the 3D NAND memory string 817 for transmitting electrical signals to and from the 3D NAND memory string 817 . The interconnect layer 827 may include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in the interconnect layer 827 also include local interconnects, such as bit lines, bit line contacts, and word line contacts. In some embodiments, the second semiconductor structure 803 further includes a bonding layer 829 at the bonding interface 807 and above the interconnect layer 827 and the memory stack 811 and the 3D NAND memory string 817 . Bonding layer 829 may include a plurality of bonding contacts 855 and a dielectric surrounding and electrically isolating bonding contacts 855 .

As shown in FIG. 8B , the first semiconductor structure 805 includes another bonding layer 851 at the bonding interface 807 and above the bonding layer 829 . Bonding layer 851 may include a plurality of bonding contacts 853 and a dielectric surrounding and electrically isolating bonding contacts 853 . According to some embodiments, bonding contacts 853 make contact with bonding contacts 855 at bonding interface 807 . In some embodiments, the first semiconductor structure 805 further includes an interconnection layer 857 above the bonding layer 851 to transmit electrical signals. The interconnect layer 857 may include a plurality of interconnects, including interconnect lines and via contacts.

The first semiconductor structure 805 may further include an interconnection layer 857 and an element layer 831 above the bonding layer 851 . In some implementations, component layer 831 includes first peripheral circuitry 835 (eg, page buffer 304, wordline driver 308, and/or I/O circuits 316 and 318) and second peripheral circuitry 837 (eg, control logic 312, registers 314, etc.). In some embodiments, the peripheral circuit 835 includes a plurality of 3D transistors 839 (eg, corresponding to the 3D transistor 500 ), and the peripheral circuit 837 includes a plurality of planar transistors 841 (eg, corresponding to the planar transistor 400 ). Trench isolations 861 and 863 (eg, STI) and doped regions (eg, wells, sources and drains of transistors 839 and 841 ) may also be formed on or in semiconductor layer 833 (eg, a thinned substrate). In some embodiments, trench isolation 861 is below semiconductor layer 833 and laterally between two adjacent 3D transistors 839 in plan view, and trench isolation 863 extends into semiconductor layer 833 and laterally between two adjacent planar transistors 841 . In some embodiments, the ditch Trench isolation 861 and trench isolation 863 have different depths (eg, their top surfaces are in different planes in the y-direction) because they separate different types of transistors (planar transistor 841 and 3D transistor 839 ), respectively. For example, as shown in FIG. 8B , trench isolation 863 may have a greater depth than trench isolation 861 . It should be understood that trench isolation 863 and trench isolation 861 have the same depth (eg, their top surfaces are in the same plane in the y-direction) in some examples, depending on different manufacturing processes.

In some embodiments, the first peripheral circuit 835 is the page buffer 304 , and the 3D transistor 839 of the first peripheral circuit 835 is coupled to the bit line of the second semiconductor structure 803 . In some embodiments, the first peripheral circuit 835 is the wordline driver 308 , and the 3D transistor 839 of the first peripheral circuit 835 is coupled to the wordline (eg, the conductive layer 834 ) of the second semiconductor structure 803 .

In some embodiments, the first semiconductor structure 805 further includes a semiconductor layer 833 disposed over the device layer 831 . The semiconductor layer 833 may be over and in contact with the peripheral circuits 835 and 837 . Semiconductor layer 833 may be a thinned substrate on which transistors 839 and 841 are formed. In some embodiments, the semiconductor layer 833 includes monocrystalline silicon. The semiconductor layer 833 may further include isolation regions and doped regions.

As shown in FIG. 8B , the first semiconductor structure 805 may further include a pad output interconnect layer 843 over the semiconductor layer 833 . The pad output interconnect layer 843 may include interconnects, eg, contact pads 845 , in one or more ILD layers. In some embodiments, the interconnects in the pad output interconnection layer 843 can transmit electrical signals between the 3D memory element 801 and external circuits, eg, for pad output purposes. In some embodiments, the first semiconductor structure 805 further includes one or more contacts 847 extending through the semiconductor layer 833 to couple the pads out of the interconnect layer 843 and the interconnect layers 857 and 827 . As a result, peripheral circuits 835 and 837 may also be coupled to the array of 3D NAND memory strings 817 through interconnect layers 857 and 827 and bond contacts 853 and 855 . That is, the array of 3D NAND memory strings 817 can be coupled across bonding interface 807 to 3D transistor 839 and planar transistor 841 . In addition, peripheral circuits 835 and 837 and the array of 3D NAND memory strings 817 can be electrically connected to external circuits through contacts 847 and pad output interconnect layer 843 .

As mentioned above, the memory cell array in the semiconductor structure 102 is not limited to An array of NAND flash memory cells is shown, and may include any other suitable array of memory cells, such as an array of DRAM cells. For example, FIG. 8C illustrates a cross-section of another exemplary 3D memory element 899 in accordance with aspects of the present disclosure. It should be understood that FIG. 8C is for illustrative purposes only, and may not in fact reflect actual component structures (eg, interconnections). 3D memory element 899 is similar to 3D memory element 800 in FIG. 8A except that the array of memory cells includes an array of DRAM cells 890 as opposed to the array of NAND memory strings 838 . It should be understood that details of similar structures (eg, materials, manufacturing processes, functions, etc. of the first semiconductor structure 802 ) in both the 3D memory devices 800 and 899 may not be repeated below.

As shown in FIG. 8C , the second semiconductor structure 804 may be bonded face-to-face on top of the first semiconductor structure 802 including the 3D transistor 816 at the bonding interface 806 . In some embodiments, bonding interface 806 is disposed between bonding layers 822 and 826 as a result of hybrid bonding.

In some embodiments, the second semiconductor structure 804 of the semiconductor element 899 also includes an interconnect layer 830 over the bonding layer 826 to transmit electrical signals to and from the DRAM cell 890 . The interconnect layer 830 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 830 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 830 may also include one or more ILD layers in which interconnect lines and via contacts may be formed.

The second semiconductor structure 804 of the semiconductor element 899 may also include an element layer 881 above the interconnect layer 830 and the bonding layer 826 . In some embodiments, component layer 881 includes an array of DRAM cells 890 over interconnect layer 830 and bonding layer 826 . In some embodiments, each DRAM cell 890 includes a DRAM select transistor 886 and a capacitor 888 . DRAM cell 890 may be a 1T1C cell consisting of a transistor and a capacitor. It should be understood that DRAM cells 890 may have any suitable configuration, such as 2T1C cells, 3T1C cells, and the like. In some embodiments, the DRAM selection transistor 886 is formed “on” the semiconductor layer 848, wherein all or a portion of the DRAM selection transistor 886 is formed in the semiconductor layer 848 (e.g., below the top surface of the semiconductor layer 848) and/or directly on the semiconductor layer 848. every other Isolated regions (eg, STI) and doped regions (eg, source and drain regions of DRAM select transistor 886 ) may also be formed in semiconductor layer 848 . In some implementations, capacitor 888 is disposed below DRAM select transistor 886 . According to some embodiments, each capacitor 888 includes two electrodes, one of which is electrically connected to a node of a corresponding DRAM select transistor 886 . According to some embodiments, the other node of each DRAM select transistor 886 is coupled to the bit line 880 of the DRAM. The other electrode of each capacitor 888 may be coupled to a common plate 882, such as a common ground. It should be understood that the structure and configuration of DRAM cell 890 is not limited to the example in FIG. 8C and may include any suitable structure and configuration. For example, capacitor 888 may be a planar capacitor, a stack capacitor, a multi-fin capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.

In some embodiments, the second semiconductor structure 804 further includes a semiconductor layer 848 disposed over the element layer 881 . The semiconductor layer 848 may be over and in contact with the DRAM cell array 890 . Semiconductor layer 848 may be a thinned substrate upon which DRAM select transistor 886 is formed. In some embodiments, semiconductor layer 848 includes monocrystalline silicon. In some embodiments, the semiconductor layer 848 may include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. The semiconductor layer 848 may also include isolation regions and doped regions (eg, as the source and drain of the DRAM select transistor 886).

As mentioned above, unlike logic elements, memory elements (e.g., 3D NAND flash memory) need to supply a wide range of voltages to various memory peripheral circuits, including higher voltages (e.g., 3.3V or above) that are not suitable for logic elements (e.g., microprocessors) (especially using advanced CMOS technology nodes (e.g., less than 22nm)) for memory operation. For example, FIG. 9 shows a block diagram of peripheral circuits supplied with various voltages according to some aspects of the present disclosure. In some embodiments, a memory element (e.g., memory element 200) includes a low low voltage (LLV) source 901, a low voltage (LV) source 903, and a high voltage (HV) source 905, each of which is configured to provide a voltage at a corresponding level (Vdd1, Vdd2, or Vdd3, where Vdd1<Vdd2<Vdd3). Each voltage source 901, 903 or 905 may receive a voltage input at an appropriate level from an external power source (eg, a battery). per voltage The source 901, 903 or 905 may also include a voltage converter and/or a voltage regulator to convert an external voltage input to and maintain a voltage at a corresponding level (Vdd1, Vdd2 or Vdd3) and output the voltage through a corresponding power rail. In some embodiments, the voltage generator 310 of the memory element 200 is part of the voltage sources 901 , 903 and 905 .

In some embodiments, the LLV source 901 is configured to provide a voltage between 0.9V and 2.0V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, 1.25V, 1.3V, 1.35V, 1.4V, 1.45V, 1.5V, 1.55V, 1.6V, 1.65V, 1.7V, 1.75V, 1.8V, 1.85V, 1.9V, 1.95V, any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values). In one example, the voltage is 1.2V. In some embodiments, LV source 903 is configured to provide a voltage between 2V and 3.3V (e.g., 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range bounded by a lower limit of any one of these values, or within any range bounded by any two of these values). in any range of ). In one example, the voltage is 3.3V. In some implementations, the HV source 905 is configured to provide a voltage greater than 3.3V. In one example, the voltage is between 5V and 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, determined by any of these values any range bounded by a lower limit of one value, or in any range bounded by any two of these values). It should be understood that the voltage ranges described above with respect to HV source 905, LV source 903, and LLV source 901 are for illustrative purposes and not limiting, and that HV source 905, LV source 903, and LLV source 901 may provide any other suitable voltage range. However, the voltage levels provided by at least LV source 903 and HV source 905 (eg, 2V and above) may not be suitable for 3D transistors (eg, FinFETs) in logic elements using advanced CMOS technology nodes (eg, less than 22nm).

Based on their appropriate voltage levels (Vdd1, Vdd2, or Vdd3), memory peripheral circuits (e.g., peripheral circuit 202) can be classified into LLV circuits 902, LV circuits 904, and HV circuits 906, which Can be coupled to LLV source 901 , LV source 903 and HV source 905 respectively. In some embodiments, the HV circuit 906 includes one or more drivers coupled to the memory cell array (e.g., memory cell array 201) through word lines, bit lines, SSG lines, DSG lines, source lines, etc., and configured to drive the memory by applying a voltage at an appropriate level to the word line, bit line, SSG line, DSG line, source line, etc. when performing a memory operation (e.g., read, program, or erase). cell array. In one example, the HV circuit 906 may include a wordline driver (eg, a column decoder/wordline driver) that applies a programming voltage (Vprog) or a pass voltage (Vpass) in the range of, for example, 5V and 30V to the wordlines during a programming operation. In another example, the HV circuit 906 may include a bit line driver (eg, row decoder/bit line driver 306 ) that applies an erase voltage (Veras) in the range of, for example, 5V and 30V to the bit lines during an erase operation. In some implementations, LV circuit 904 includes a page buffer (eg, page buffer 304 ) configured to buffer data read from or programmed to the array of memory cells. For example, a voltage of eg 3.3V may be supplied from the LV source 903 to the page buffer. In some implementations, LLV circuitry 902 includes I/O circuitry (eg, interface 316 and/or data bus 318 ) configured to interface the array of memory cells with a memory controller. For example, a voltage of eg 1.2V may be provided by LLV source 901 to the I/O circuit.

At least one of LLV circuit 902, LV circuit 904, or HV circuit 906 may include a 3D transistor (eg, 3D transistor 500) disclosed herein. In some implementations, each of LLV circuit 902 , LV circuit 904 , and HV circuit 906 includes 3D transistors. In some implementations, each of LLV circuit 902 and LV circuit 904 includes a 3D transistor, while HV circuit 906 includes a planar circuit disclosed herein (eg, planar transistor 400 ). Additionally, LLV circuit 902, LV circuit 904, or HV circuit 906 may be implemented with 3D transistors and/or planar transistors in any suitable combination disclosed herein as peripheral circuits 812, 814, 835, and 837 in FIGS. 8A-8C.

Consistent with the scope of the present disclosure, various designs of 3D transistors suitable for LLV circuit 902, LV circuit 904, and HV circuit 906, respectively, are described in detail below. According to some of this disclosure In one aspect, as shown in FIG. 10 , the LLV circuit 902 of the memory device 200 may be represented by an I/O circuit including, for example, the interface 316 and the data bus 318 . I/O circuitry may be configured to interface memory cell array 201 with a memory controller. In some implementations, the I/O circuit is supplied by the LLV source 901 with a voltage between 0.9V and 2.0V, for example 1.2V.

11A and 11B illustrate perspective and side views, respectively, of 3D transistor 1100 in the I/O circuit of FIG. 10, in accordance with some aspects of the present disclosure. 3D transistor 1100 may be an example of 3D transistor 500 in FIGS. 5, 6A and 6B, and is designed to meet the specific requirements of I/O circuitry or any other suitable LLV circuitry 902, as described in detail below. FIG. 11B shows a side view of the cross-section of the 3D transistor 1100 in FIG. 11A in plane BB. As shown in FIGS. 11A and 11B , the 3D transistor 1100 may include a 3D semiconductor body 1104 above a substrate 1102, and a gate structure 1108 in contact with a plurality of sides (eg, a top surface and two side surfaces) of the 3D semiconductor body 1104. It should be understood that the 3D transistor 1100 may be any suitable multi-gate transistor, eg, as shown in FIGS. 7A-7I . In some embodiments, the gate structure 1108 includes a gate dielectric 1107 in contact with the sides of the 3D semiconductor body 1104 and a gate electrode 1109 in contact with the gate dielectric 1107 . As shown in FIGS. 11A and 11B , the top surface of the gate structure 1108 (eg, gate electrode 1109 ) is curved.

As shown in FIGS. 11A and 11B , the 3D transistor 1100 may also include a pair of source and drain electrodes 1106 in the 3D semiconductor body 1104 and separated by a gate structure 1108 in plan view. As shown in FIG. 11B , trench isolations 1103 (eg, STIs) may be formed in the substrate 1102 such that gate structures 1108 may be formed on the trench isolations 1103 . In some embodiments, trench isolation 1103 is also formed laterally between adjacent 3D transistors 1100 to reduce leakage current. It should be understood that trench isolation 1103 is shown in FIG. 11B but not shown in FIG. 11A for ease of illustration. It should also be understood that the 3D transistor 1100 may include additional components not shown in FIGS. 11A and 11B , such as wells and spacers.

For the 3D transistor 1100 used in the I/O circuit of the memory device 200, switching speed is an important characteristic. In particular, when memory element 200 is a bonded wafer, such as 3D memory elements 800 and 801, which can achieve high-speed I/O throughput with reduced power consumption by using direct, short-distance (e.g., micron-scale) electrical connections between two bonded semiconductor structures, the switching speed of transistors forming the I/O circuit can become a performance bottleneck for the I/O circuit. In order to increase the switching speed, as mentioned above, it is necessary to increase the on-state current (I _on or I _dsat ) of the transistor. However, at the same time, the off-state leakage current (I _off ) cannot be increased, which is difficult to achieve with planar transistors.

For example, Figures 12A and 12B show a perspective view and a side view, respectively, of a planar transistor 1200. Planar transistor 1200 may be an example of planar transistor 400 in FIG. 4 . The planar transistor 1200 includes a gate structure 1208 on a substrate 1202 , ie, above and in contact with a top surface of the substrate 1202 . The gate structure 1208 includes a planar gate dielectric 1207 over and in contact with the top surface of the substrate 1202 , and a gate electrode 1209 on the planar gate dielectric 1207 . The planar transistor 1200 also includes a pair of source and drain electrodes 1206 in the substrate 1202 and separated by a gate structure 1208 in plan view. Trench isolation 1203 (eg, STI) is formed in substrate 1202 and laterally between adjacent planar transistors 1200 . It should be understood that trench isolation 1203 is shown in FIG. 12B but not shown in FIG. 12A for ease of illustration. Due to the lower number of channels and gates compared to the 3D transistor 1100, the channel control and sub-threshold swing of the planar transistor 1200 may be poor. As a result, according to the research conducted by the inventors, under the same size and leakage current (off-state current), the saturation drain current (on-state current) of the 3D transistor 1100 can be several times higher (for example, more than twice) than that of the planar transistor 1200 . On the other hand, in order to maintain the same switching speed and leakage current as the planar transistor 1200, the size of the 3D transistor 1100 can be reduced. In addition, in order to further improve the electrical performance of the I/O circuit, HKMG can be used in the gate structure 1108 of the 3D transistor 1100 , while the planar transistor 1200 with a larger size does not use it.

Referring back to FIGS. 11A and 11B , in some embodiments, the gate electrode 1109 of the 3D transistor 1100 in the I/O circuit of the memory device 200 includes a metal, such as Cu. In some embodiments, the gate dielectric 1107 of the 3D transistor 1100 comprises a high-K dielectric such as hafnium dioxide, zirconium dioxide, titanium dioxide, or any other dielectric with a higher dielectric constant than silicon nitride (eg, higher than 3.9). That is, HKMG can be used to form the gate structure 1108 of the 3D transistor 1100 in the I/O circuit of the memory device 200 . It should be understood that gate polysilicon and gate oxide may also be used as gate structure 1108 in some examples.

In some embodiments, as shown in FIG. 11B , the thickness (T) of gate dielectric 1107 is between 1.8 nm and 10 nm. For example, the thickness of the gate dielectric 1107 can be between 2nm and 4nm (e.g., 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3nm, 3.1nm, 3.2nm, 3.3nm, 3.4nm, 3.5nm, 3.6nm, 3.7nm, 3.8nm, 3.9nm, 4nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The thickness of the gate dielectric 1107 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic elements using advanced technology nodes (eg, less than 22nm), and may be comparable to the range of LLV voltages applied to I/O circuits, eg, between 0.9V and 2.0V (eg, 1.2V), as detailed above.

In some embodiments, as shown in FIG. 11B , the width (W) of the 3D semiconductor body 1104 is between 10 nm and 180 nm. The width of the 3D semiconductor body 1104 may refer to the width at the top of the 3D semiconductor body 1104 (eg, the top critical dimension (CD)), as shown in FIG. 11B . For example, the width of the 3D semiconductor body 1104 may be between 30 nm and 100 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The width of 3D transistor 1100 may be larger (eg, one or more times) than the width of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22nm). On the other hand, the width of the 3D transistor 1100 may be smaller than the width of the planar transistor 1200 used in the I/O circuit of the existing memory device. It should be appreciated that in some examples, the 3D semiconductor body 1104 may have a "dumbbell" shape, wherein the width of the 3D semiconductor body 1104 at the sides where the source and drain 1106 are formed is greater than the width of the semiconductor body 1104 at the source The width between the pole and the drain 1106.

In some embodiments, the channel length of the 3D transistor 1100 between the source and the drain 1106 is between 30 nm and 180 nm. The channel length of the 3D transistor 1100 may refer to the distance between the source and drain 1106, ie, the dimension of the gate structure 1104 in contact with the top surface of the channel. For example, the channel length of 3D transistor 1100 may be between 50 nm and 120 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The channel length of 3D transistor 1100 may be larger (eg, one or more times) than that of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22nm). On the other hand, the channel length of the 3D transistor 1100 may be smaller than the channel length of the planar transistor 1200 used in the I/O circuit of the existing memory device.

In some embodiments, as shown in FIG. 11B , the height (H) of the 3D semiconductor body 1104 is between 40 nm and 300 nm. For example, the height of the 3D semiconductor body 1104 may be between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The height of the 3D semiconductor body 1104 may be greater (eg, one or more times) than the height of 3D transistors (eg, FinFETs) used in logic elements using advanced technology nodes (eg, less than 22nm).

In some embodiments, as shown in FIG. 11B , the thickness (t) of the trench isolation 1103 is the same as the height of the 3D semiconductor body 1104 . For example, trench isolation 1103 may have a thickness between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit for any one of these values, or in any range bounded by any two of these values). The thickness of trench isolation 1103 may be greater (eg, one or more times) than that of 3D transistors (eg, FinFETs) used in logic elements using advanced technology nodes (eg, less than 22nm) thickness.

According to some aspects of the present disclosure, the LV circuit 904 of the memory element 200 may be represented by, for example, a page buffer 304 as shown in FIG. 13 . The page buffer 304 may be configured to buffer data read from or programmed into the memory cell array 201 . In some implementations, the page buffer 304 is supplied by the LV source 903 with a voltage between 2V and 3.3V, for example 3.3V. According to some aspects of the present disclosure, as shown in FIG. 13 , the HV circuit 906 of the memory element 200 may be represented by, for example, a word line driver 308 . The word line driver 308 may be configured to drive the memory cell array 201 through the word lines. In some implementations, the wordline driver 308 is provided by the HV source 905 with a voltage greater than 3.3V (eg, between 5V and 30V).

FIG. 14 shows a schematic circuit diagram of word line driver 308 and page buffer 304 in FIG. 13 in accordance with some aspects of the present disclosure. In some embodiments, the page buffer 304 includes a plurality of sub-page buffer circuits 1402 each coupled to a 3D NAND memory string 208 via a corresponding bit line 216 . That is, memory device 200 may include bit lines 216 respectively coupled to 3D NAND memory strings 208 , and page buffer 304 may include subpage buffer circuits 1402 respectively coupled to bit lines 216 and 3D NAND memory strings 208 . Each subpage buffer circuit 1402 may include one or a plurality of latches, switches, power supplies, nodes (eg, data nodes and I/O nodes), current mirrors, verification logic, sensing circuits, and the like. In some embodiments, each subpage buffer circuit 1402 is configured to store sense data received from the corresponding bit line 216, eg, a sense current corresponding to the read data. Each subpage buffer circuit 1402 can be configured to also output the sensed data stored in the memory during a read operation. Each sub-page buffer circuit 1402 can also be configured to store programming data, and output the stored programming data to the corresponding bit line 216 during a programming operation.

As shown in FIG. 14, each subpage buffer circuit 1402 may include a plurality of transistors, such as the 3D transistor 2000 disclosed in detail below with reference to FIGS. exist In some implementations, the 3D transistors 2000 in the page buffer 304 are coupled to the bit line 216 . Therefore, the 3D transistor 2000 in the page buffer 304 can be coupled to the memory cell array 201 through the bit line 216 .

In some embodiments, the wordline driver 308 includes a plurality of string drivers 1404 (also called driving elements) respectively coupled to the wordlines 218 . The word line driver 308 may also include a plurality of local word lines 1406 (LWL) respectively coupled to the string driver 1404 . Each string driver 1404 may include a gate coupled to a decoder (not shown), a source/drain coupled to a corresponding local wordline 1406 , and another source/drain coupled to a corresponding wordline 218 . In some memory operations, the decoder may select certain string drivers 1404, such as by applying a voltage signal greater than the threshold voltage of the string drivers 1404 and applying a voltage (e.g., a program voltage, a pass voltage, or an erase voltage) to each local word line 1406 such that a voltage is applied by each selected string driver 1404 to the corresponding word line 218. Conversely, the decoder can also deselect certain string drivers 1404, such as by applying a voltage signal less than the threshold voltage of the string drivers 1404, so that each unselected string driver 1404 floats the corresponding word line 218 during memory operation.

As shown in FIG. 14, each string driver 1404 may include one or a plurality of transistors, such as the 3D transistor 2100 disclosed in detail below with reference to FIGS. In some embodiments, the 3D transistor 2100 in the wordline driver 308 is coupled to the wordline 218 . Therefore, the 3D transistor 2100 in the word line driver 308 can be coupled to the memory cell array 201 through the word line 218 .

As shown in FIG. 15 , in some embodiments, the memory cell array 201 is arranged in a plurality of planes 1502 , each plane having a plurality of blocks 204 and its own page buffer 304 . That is, the memory device 200 may include a plurality of planes 1502 of the memory unit 206 and a plurality of page buffers 304 respectively coupled to the plurality of planes 1502 . Although not shown in FIG. 15, it should be understood that in some examples, each plane 1502 may have its own page buffer 304, column decoder/word line driver 308, and row decoder. The set of encoders/bit line drivers 306 enables the control logic 312 to control the operations of the plurality of planes 1502 in parallel in a synchronous or asynchronous manner, so as to increase the operating speed of the memory device 200 . As described above with respect to FIGS. 2 and 14, it should be understood that the number of page buffers 304 and the number of sub-page buffer circuits 1402 in each page buffer 304 may increase as the number of memory cells increases due to the increased number of planes 1502, blocks 204, and/or 3D NAND memory strings 208 (bit lines 216). Therefore, the total area of the page buffer 304 continues to increase if the element size of each transistor forming the sub-page buffer circuit 1402 does not decrease. Similarly, the number of string drivers 1404 may increase as the number of memory cells increases due to the increased number of planes 1502, blocks 204, and/or columns 220 (word lines 218). Therefore, if the size of the elements forming each transistor of the string driver 1404 does not decrease, the overall area of the word line driver 308 continues to increase.

Furthermore, in the 3D memory device 100 or 101 in which peripheral circuits and memory cell arrays are vertically stacked on each other in a bonded wafer, the size of the 3D memory device 100 or 101 depends on the larger size of the first semiconductor structure 102 or the second semiconductor structure 104 . As shown in FIG. 16 , as the area of the page buffer 304 continues to increase, the size of the second semiconductor structure 104 (e.g., shown in FIGS. 1A and 1B ) having the page buffer 304, the word line driver 308 and other peripheral circuits 1600 (e.g., I/O circuits, etc.) may eventually become larger than the size of the first semiconductor structure 102 having the memory cell array, and thus dominate the size of the 3D memory element 100 or 101. As a result, to compensate for the increased size of the memory element 200 (and in particular, the 3D memory element 100 or 101), the element size of each transistor forming the page buffer 304 and the wordline driver 308 needs to be reduced without sacrificing too much performance (such as transistor current leakage) and product yield and cost, as described above.

As mentioned above, compared with planar transistors used to form existing memory peripheral circuits (such as sub-page buffer circuits and string drivers), 3D transistors can reduce the size of components without sacrificing too much performance (such as leakage current), manufacturing complexity and cost due to larger gate control area, higher on-state current and lower off-state current. For example, Figure 17 shows a word line driver or The design layout of the planar transistors in the page buffer, and for comparison, FIG. 18 shows the design layout of the word line driver 308 in FIG. 13 or the 3D transistors in the page buffer 304 according to some aspects of the present disclosure.

As shown in Figures 17 and 18, the width (W) of the active region (ie, the channel width) and/or the length (L) of the gate structure (ie, the channel length) may be affected by switching from planar to 3D transistors. Accordingly, the pitch in the width direction (PW) and/or the pitch in the length direction (PL) in the word line driver 308 or the page buffer 304 can be reduced. In some embodiments, the use of planar transistors to form sub-page buffer circuit 1402 for page buffer 304 can only achieve a minimum channel width (W1) of 180 nm without introducing a significant increase in leakage current. On the contrary, according to the research of the inventors, using 3D transistors to form the sub-page buffer circuit 1402, the channel width (W2) can be reduced below 180nm without introducing a significant increase in leakage current. For example, under the same leakage current, by replacing the planar transistors with 3D transistors when forming the subpage buffer circuit 1402, the spacing in the width direction can be reduced by 5% to 50% (eg, 25%), thereby reducing the total area of the page buffer 304. In addition, since the bit lines 216 can be arranged along the width direction, the reduction of the pitch of the subpage buffer circuit 1402 along the width direction can accommodate more bit lines 216 and 3D NAND memory strings 208 .

In some embodiments, for the wordline driver 308, similar to the page buffer 304, using 3D transistors instead of planar transistors to form the string driver 1404 can reduce the channel width, for example, from 1900nm to 500nm, thereby reducing the overall area of the wordline driver 308 without introducing a significant increase in leakage current. In addition, the channel length can also be reduced by replacing planar transistors with 3D transistors in the string driver 1404 . Thus, by using 3D transistors, the distance from the gate structure to the well boundary can be increased, thereby increasing the breakdown voltage (BV) margin, which is an important characteristic of the HV circuit 906 (eg, wordline driver 308 ). In addition, since the word lines 218 can be arranged along the length direction, the reduction of the pitch of the string driver 1404 along the length direction can also accommodate more word lines 218 . The reduced size of the string driver 1404 may allow more string drivers 1404 to be targeted to bonded 3D memory components (e.g., 3D memory component 800 and 801), and thus reduce metal wiring and metal layers. In some embodiments, for the word line driver 308 or any other HV circuit 906, the channel length (L2) is greater than the channel width (W2) of a 3D transistor as shown in FIG. It should be understood that for the word line driver 308 or any other HV circuit 906, unlike that shown in FIG. 18 , the width (W2') of the source/drain of the 3D transistor may be the same as the channel width of the 3D transistor (W2, i.e. the width of the 3D semiconductor body/active region between the source and drain), so that the 3D semiconductor body of the 3D transistor may not have a dumbbell shape in plan view, but have a uniform width along the length of the channel.

For example, FIG. 19 illustrates a side view of a cross-section of a 3D memory element 1900 including a string driver with 3D transistors, according to some aspects of the present disclosure. The 3D memory element 1900 may be an example of the 3D memory element 800 . As shown in FIG. 19 , a 3D memory device 1900 may include a first semiconductor structure 1902 and a second semiconductor structure 1904 bonded to each other in a face-to-face manner at a bonding interface 1915 . It should be understood that in other examples, the relative positions of the first and second semiconductor structures may be switched. The first semiconductor structure 1902 may include a stacked structure, such as a memory stack 1906 including interleaved word lines 1905 and a dielectric layer 1907 . In some embodiments, the edges of the interleaved word lines 1905 and dielectric layer 1907 define one or more stair structures 1908 on one or more sides of the memory stack 1906 . A ladder structure 1908 may be used to interconnect wordlines 1905 through wordline contacts 1912 . The first semiconductor structure 1902 may also include an array of memory cells, such as an array of 3D NAND memory strings 1910 , each string extending vertically through the memory stack 1906 .

The second semiconductor structure 1904 may include a plurality of string drivers 1914 respectively corresponding to the word lines 1905 . Each string driver 1914 may include 3D transistors for the HV circuit 906 disclosed herein. As shown in FIG. 19, by using 3D transistors to reduce the size of each transistor, the string driver 1914 can face the stepped structure 1908 across the bonding interface 1915 to allow each wordline contact 1912 to electrically connect a pair of wordlines 1905 and the string driver 1914 without wiring outside the stepped region in plan view. That is, all strings Driver 1914 may be disposed directly below or above stepped structure 1908 . Therefore, by replacing the planar transistors with 3D transistors in the string driver 1914, extra metal wiring outside the step region and the resulting extra metal layers can be avoided. It should be understood that word line contacts 1912 in FIG. 19 are for illustrative purposes only and may include interconnects in various interconnect layers and bonding layers (not shown) of 3D memory element 1900 . As shown in FIGS. 8A and 8B , the first semiconductor structure 1902 and the second semiconductor structure 1904 can also include their own interconnection layer and bonding layer, so that the 3D transistor of the string driver 1914 can be coupled to the word line 1905 through the first and second interconnection layer and the first and second bonding layer, respectively.

20A and 20B illustrate perspective and side views, respectively, of 3D transistor 2000 in page buffer 304 of FIG. 13 in accordance with some aspects of the present disclosure. 3D transistor 2000 may be an example of 3D transistor 500 in FIGS. 5, 6A and 6B, and is designed to meet the specific requirements of page buffer 304 or any other suitable LV circuit 904, as described in detail below. FIG. 20B shows a side view of the cross-section of the 3D transistor 2000 in FIG. 20A in plane BB. As shown in FIGS. 20A and 20B , a 3D transistor 2000 may include a 3D semiconductor body 2004 above a substrate 2002, and a gate structure 2008 in contact with a plurality of sides (eg, a top surface and two side surfaces) of the 3D semiconductor body 2004. It should be understood that the 3D transistor 2000 may be any suitable multi-gate transistor, eg, as shown in FIGS. 7A-7I . In some embodiments, the gate structure 2008 includes a gate dielectric 2007 in contact with the sides of the 3D semiconductor body 2004 and a gate electrode 2009 in contact with the gate dielectric 2007 . As shown in Figures 20A and 20B, the top surface of the gate structure 2008 (eg, gate electrode 2009) is curved.

As shown in FIGS. 20A and 20B , the 3D transistor 1100 may also include a pair of source and drain electrodes 2006 in the 3D semiconductor body 2004 and separated by a gate structure 2008 in plan view. As shown in FIG. 20B , trench isolation 2003 (eg, STI) may be formed in substrate 2002 such that gate structure 2008 may be formed on trench isolation 2003 . In some embodiments, trench isolation 2003 is also formed laterally between adjacent 3D transistors 2000 to reduce leakage current. It should be understood that trench isolation 2003 is shown in FIG. 20B but not shown in FIG. 20A for ease of illustration. It should also be understood that 3D transistor 2000 may comprise the Additional components not shown in , such as wells and spacers.

As mentioned above, for the 3D transistor 2000 used in the page buffer 304 of the memory device 200, the device size is an important characteristic. On the other hand, the off-state leakage current (Ioff) cannot be increased to reduce current leakage, which is difficult to achieve with planar transistors. Furthermore, since the LV circuit 904 operates at a voltage between, for example, 2V and 3.3V (e.g., 3V), the size reduction of the 3D transistor 2000 cannot rely on voltage reduction, which is difficult to achieve with 3D transistors used in logic elements using advanced CMOS technology nodes (e.g., below 22nm). It should be appreciated that page buffer 304 may include HV circuitry 906 and LV circuitry 904 . In one example, LV circuit 904 of page buffer 304 may include 3D transistor 2000 and HV circuit 906 of page buffer 304 may include planar transistors (eg, planar transistor 400 ). In another example, one of the LV circuits 904 in the page buffer 304 may include a 3D transistor having a structure similar to that in FIGS. 11A and 11B . One of the HV circuits 906 in the page buffer includes a 3D transistor having a structure similar to that of FIGS. 21A and 21B . The two 3D transistors in the page buffer have different structures and different sizes. The size of the 3D transistors in the HV circuit 906 is larger than the size of the 3D transistors in the LV circuit 904 . The dimensions of the 3D transistor include at least one of the channel length of the 3D transistor, the height of the 3D semiconductor body of the 3D transistor, the width of the 3D semiconductor body of the 3D transistor, or the area of the 3D transistor. In some embodiments, in the peripheral circuit, the page buffer and other circuits both include 3D transistors, the 3D transistor in the page buffer includes a single fin, and the 3D transistor in other peripheral circuits includes more than one fin.

In some embodiments, as shown in Figure 20B, the thickness (T) of the gate dielectric 2007 is between 1.8 nm and 10 nm. For example, the gate dielectric 2007 may have a thickness between 2nm and 8nm (e.g., 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3nm, 3.1nm, 3.2nm, 3.3nm, 3.4nm, 3.5nm, 3.6nm, 3.7nm, 3.8nm, 3.9nm, 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, any range bounded by the lower limit of any one of these values, or any two of these values in any range defined by the value). The thickness of the gate dielectric 2007 may be greater (e.g., one or more times) than the thickness of 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22nm), and may be comparable to the range of LV voltages applied to the page buffer 304, such as between 2V and 3.3V (e.g., 3.3V), as detailed above. Furthermore, compared to the 3D transistor 1100 in the LLV circuit 902 (such as an I/O circuit), in some embodiments the thickness of the gate dielectric 2007 of the 3D transistor 2000 is thicker due to the higher operating voltage, for example between 4 nm and 8 nm, such as between 5 nm and 8 nm.

In some embodiments, as shown in Figure 20B, the width (W) of the 3D semiconductor body 2004 is between 10 nm and 180 nm. The width of the 3D semiconductor body 2004 may refer to the width at the top (eg, top CD) of the 3D semiconductor body 2004, as shown in FIG. 20B. For example, the width of the 3D semiconductor body 1104 may be between 30 nm and 100 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The width of 3D transistor 2000 may be larger (eg, one or more times) than the width of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22nm). On the other hand, the width of the 3D transistor 2000 can be smaller than the width of the planar transistor used in the page buffer of the existing memory device, for example larger than 180nm, as mentioned above. It should be appreciated that in some examples, the 3D semiconductor body 2004 may have a "dumbbell" shape, wherein the width of the 3D semiconductor body 2004 at the sides where the source and drain 2006 are formed is greater than the width of the 3D semiconductor body 2004 between the source and drain 2006 due to the relatively small width of the 3D semiconductor body 2004 that is insufficient to form the source and drain 2006. For example, as shown in FIG. 18, the width (W2') of the source/drain of the 3D transistor may be greater than the channel width (W2, ie, the width of the 3D semiconductor body/active region between the source and drain) of the 3D transistor.

In some embodiments, the channel length of the 3D transistor 2000 between the source and the drain 2006 is between 30 nm and 180 nm. The channel length of the 3D transistor 2000 can refer to the distance between the source and the drain 2006 , ie, the size of the gate structure 2008 in contact with the top surface of the channel. For example, the channel length of 3D transistor 2000 may be between 50 nm and 120 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The channel length of 3D transistor 2000 may be greater (eg, one or more times) than that of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22nm). On the other hand, the channel length of the 3D transistor 2000 may be smaller than the channel length of the planar transistor used in the page buffer of the existing memory device, eg greater than 180 nm.

In some embodiments, as shown in Figure 20B, the height (H) of the 3D semiconductor body 2004 is between 40 nm and 300 nm. For example, the height of the 3D semiconductor body 2004 may be between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The height of the 3D semiconductor body 2004 may be greater (eg, one or more times) than the height of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22nm).

In some embodiments, as shown in FIG. 20B , the thickness (t) of the trench isolation 2003 is the same as the height of the 3D semiconductor body 2004 . For example, trench isolation 2003 may have a thickness between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit for any one of these values, or in any range bounded by any two of these values). The thickness of trench isolation 2003 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22nm).

Compared to 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22nm), for example, by changing materials and/or simplifying structure and process, it is also possible to Improve the production yield and cost of 3D Transistor 2000. In some embodiments, instead of using HKMG, the gate electrode 2009 of the 3D transistor 2000 in the page buffer 304 of the memory device 200 comprises polysilicon, eg, polysilicon doped with nitride (N). In some embodiments, the gate dielectric 2007 of the 3D transistor 2000 includes silicon oxide. That is, gate polysilicon and gate oxide can be used as the gate structure 2008 to reduce manufacturing complexity and cost. In some embodiments, the 3D transistor 2000 does not include stressors at the source and drain 2006 and/or does not use strained semiconductor material in the 3D semiconductor body 2004 to reduce manufacturing complexity and cost.

21A and 21B illustrate perspective and side views, respectively, of 3D transistor 2100 in word line driver 308 of FIG. 13 in accordance with some aspects of the present disclosure. 3D transistor 2100 may be an example of 3D transistor 500 in FIGS. 5 , 6A and 6B and is designed to meet the specific requirements of word line driver 308 or any other suitable HV circuit 906 as described in detail below. FIG. 21B shows a side view of a cross-section of the 3D transistor 2100 in FIG. 21A in the BB plane. As shown in FIGS. 21A and 21B , the 3D transistor 2100 may include a 3D semiconductor body 2104 above a substrate 2102 and a gate structure 2108 in contact with a plurality of sides (eg, a top surface and two side surfaces) of the 3D semiconductor body 2104 . It should be understood that the 3D transistor 2100 may be any suitable multi-gate transistor, eg, as shown in FIGS. 7A-7I . In some embodiments, the gate structure 2108 includes a gate dielectric 2107 in contact with the sides of the 3D semiconductor body 2104 and a gate electrode 2109 in contact with the gate dielectric 2107 .

As shown in FIGS. 21A and 21B , the 3D transistor 2100 may also include a pair of source and drain electrodes 2106 in the 3D semiconductor body 2104 and separated by a gate structure 2108 in plan view. Due to the relatively high voltage applied to the 3D transistor 2100 used in the HV circuit 906 , the 3D transistor 2100 may further include a drift region 2110 in the 3D semiconductor body 2104 . The source and drain 2106 may be in contact with the drift region 2110 . It should be understood that, in some examples, 3D transistors 1100 and 2000 used in LLV circuit 902 and LV circuit 904 may not include drift region 2110 due to lower voltages applied to 3D transistors 1100 and 2000 and fewer breakdown issues. The drift region 2110 may be a doped region in the 3D semiconductor body 2104, similar to source and drain electrode 2106, but with a lower doping concentration than the source and drain electrodes 2106. That is, the source and drain 2106 may be heavily doped regions formed in the lightly doped region (ie, the drift region 2110 ) in the 3D transistor 2100 . In some embodiments, the drift region 2110 and the source and the drain 2106 are doped with N-type dopants, so that the source and the drain 2106 become the heavily N-doped region (N+) in the lightly N-doped region (N, ie, the drift region 2110). In order to maintain a relatively high voltage applied to the 3D transistor 2100 used in the HV circuit 906 and avoid breakdown, in some embodiments, the distance (d1) between the source/drain 2106 and the gate structure 2108 is greater than the distance (d2) between the source/drain 2106 and the edge of the 3D semiconductor structure 2104. For example, d1 may be two or more times larger than d2. As shown in FIG. 21B , a trench isolation 2103 (eg, STI) may be formed in the substrate 2102 such that a gate structure 2108 may be formed on the trench isolation 2103 . In some embodiments, trench isolation 2103 is also formed laterally between adjacent 3D transistors 2100 to reduce leakage current. It should be understood that trench isolation 2103 is shown in FIG. 21B but not shown in FIG. 21A for ease of illustration. It should also be understood that 3D transistor 2100 may include additional components not shown in FIGS. 21A and 21B , such as wells and spacers.

As mentioned above, for the 3D transistor 2100 used in the word line driver 308 of the memory device 200, the device size is an important characteristic. On the other hand, the off-state leakage current (Ioff) cannot be increased to reduce current leakage, which is difficult to achieve with planar transistors. Also, since the HV circuit 906 operates at voltages, e.g., greater than 3.3V (e.g., between 5V and 30V), the size reduction of the 3D transistor 2100 cannot rely on voltage reduction, which is difficult to achieve with 3D transistors used in logic elements using advanced CMOS technology nodes (e.g., less than 22nm).

In some embodiments, as shown in Figure 2 IB, the thickness (T) of gate dielectric 2107 is greater than 10 nm. For example, the gate dielectric 2107 may have a thickness between 20nm and 80nm (e.g., 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, 31nm, 32nm, 33nm, 34nm, 35nm, 36nm, 37nm, 38nm, 39nm, 40nm, 45nm, 50nm, 55nm, 6 0nm, 65nm, 70nm, 75nm, 80nm, any range defined by the lower limit of any one of these values, or any range defined by any two of these values in any range). The thickness of gate dielectric 2107 may be significantly greater (eg, by an order or multiple of orders of magnitude) than the thickness of 3D transistors (eg, FinFETs) used in logic elements using advanced technology nodes (eg, less than 22 nm), and may be comparable to the range of HV voltages applied to wordline driver 308, eg, greater than 3.3V (eg, between 5V and 30V), as detailed above. Furthermore, compared to 3D transistor 1100 in LLV circuit 902 (such as I/O circuit) and 3D transistor 2000 in LV circuit 904 (such as page buffer 304), in some embodiments, the thickness of gate dielectric 2107 of 3D transistor 2100 is thicker due to the higher operating voltage.

In some embodiments, as shown in FIG. 21B , the width (W) of the 3D semiconductor body 2104 is greater than 100 nm. The width of the 3D semiconductor body 2104 may refer to the width at the top (eg, top CD) of the 3D semiconductor body 2104, as shown in FIG. 21B. For example, the width of the 3D semiconductor body 2104 may be between 300 nm and 1000 nm (e.g., 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The width of 3D transistor 2100 may be significantly greater (eg, by one or several orders of magnitude) than the width of 3D transistors (eg, FinFETs) used in logic elements using advanced technology nodes (eg, less than 22nm). On the other hand, the width of the 3D transistor 2100 can be smaller than the width of the planar transistor used in the word line driver of the existing memory device, eg 1900nm, as mentioned above. Furthermore, in some embodiments, the width of the 3D semiconductor body 2104 of the 3D transistor 2100 is larger due to the higher operating voltage compared to the 3D transistor 1100 in the LLV circuit 902 (such as the I/O circuit) and the 3D transistor 2000 in the LV circuit 904 (such as the page buffer 304). It should be appreciated that in some examples, unlike some examples where 3D semiconductor bodies 1104 and 2004 have a dumbbell shape in plan view, since 3D semiconductor body 1104 may have a relatively large width sufficient to form source and drain 2106, 3D semiconductor body 2104 may not have a dumbbell shape in plan view, i.e., have a uniform width.

In some embodiments, the channel length of the 3D transistor 2100 between the source and the drain 2106 is The degree is greater than 120nm. The channel length of the 3D transistor 2100 may refer to the distance between the source and drain 2106, ie, the dimension of the gate structure 2108 in contact with the top surface of the channel. For example, the channel length of 3D transistor 2100 may be between 500 nm and 1200 nm (e.g., 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The channel length of 3D transistor 2100 may be significantly greater (eg, by one or multiple orders of magnitude) than the channel length of 3D transistors (eg, FinFETs) used in logic elements using advanced technology nodes (eg, less than 22 nm). On the other hand, the channel length of the 3D transistor 2100 may be smaller than the channel length of the planar transistor used in the word line driver of the existing memory device, for example, 900nm. Furthermore, compared to 3D transistor 1100 in LLV circuit 902 (such as I/O circuit) and 3D transistor 2000 in LV circuit 904 (such as page buffer 304), in some embodiments, the channel length of 3D transistor 2100 is larger due to the higher operating voltage.

In some embodiments, as shown in Figure 2 IB, the height (H) of the 3D semiconductor body 2104 is greater than 50 nm. For example, the height of the 3D semiconductor body 2104 may be between 300 nm and 500 nm (e.g., 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values). The height of the 3D semiconductor body 2104 may be significantly greater (eg, by an order or orders of magnitude) than the height of 3D transistors (eg, FinFETs) used in logic elements using advanced technology nodes (eg, less than 22nm). Furthermore, in some embodiments, the height of the 3D semiconductor body 2104 of the 3D transistor 2100 is larger due to the higher operating voltage compared to the 3D transistor 1100 in the LLV circuit 902 (such as the I/O circuit) and the 3D transistor 2000 in the LV circuit 904 (such as the page buffer 304).

In some embodiments, as shown in FIG. 21B , the thickness (t) of the trench isolation 2103 is less than, eg, not greater than one third (1/3) of the height of the 3D semiconductor body 2104 . For example, trench isolation 2103 may have a thickness between 100 nm and 200 nm (eg, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values). The thickness of trench isolation 2103 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22nm). Furthermore, compared to 3D transistors 1100 in LLV circuits 902 (such as I/O circuits) and 3D transistors 2000 in LV circuits 904 (such as page buffers 304), in some embodiments, the thickness of trench isolation 2103 of 3D transistors 2100 is smaller due to the higher operating voltage.

The product yield and cost of the 3D transistor 2100 may also be improved, for example, by changing materials and/or simplifying the structure and process, compared to 3D transistors (e.g., FinFETs) used in logic elements using advanced technology nodes (e.g., less than 22nm). In some embodiments, instead of using HKMG, the gate electrode 2109 of the 3D transistor 2100 in the word line driver 308 of the memory device 200 includes polysilicon, for example, polysilicon doped with P-type dopants or N-type dopants, and the gate dielectric 2107 of the 3D transistor 2100 includes silicon oxide doped with nitrogen ( _N2 ). In some embodiments, the gate dielectric 2107 of the 3D transistor 2100 includes silicon oxide. That is, gate polysilicon and gate oxide can be used as the gate structure 2108 to reduce manufacturing complexity and cost. In some embodiments, the 3D transistor 2100 includes no stressors at the source and drain 2106 and/or uses no strained semiconductor material in the 3D semiconductor body 2104 to reduce manufacturing complexity and cost.

Consistent with the scope of the present disclosure, peripheral circuitry 202 may include LLV circuitry 902 with 3D transistors 1100 (e.g., I/O circuitry of interface 316 and data bus 318), LV circuitry 904 with 3D transistors 2000 (eg, part of page buffer 304), and HV circuitry 906 with 3D transistors 2100 (eg, wordline driver 308). LLV source 901 may be coupled to LLV circuit 902 and configured to provide Vdd1 to 3D transistor 1100, LV source 903 may be coupled to LV circuit 904 and configured to provide Vdd2 to 3D transistor 2000, and HV source 905 may be coupled to HV circuit 906 and configured to provide Vdd3 to 3D transistor 2100, wherein Vdd3>Vdd2>Vdd1. such as 3D in word line driver 308 Transistor 2100 may be coupled to memory cell array 201 via word line 218 , and 3D transistor 2000 , for example in page buffer 304 , may be coupled to memory cell array 201 via bit line 216 . Due to different operating voltages, the gate dielectric thickness (T) of the 3D transistor 2100 may be greater than that of the 3D transistor 2000 , which in turn may be greater than that of the 3D transistor 1100 . It should be understood that, as described in detail above, due to the higher operating voltage applied to the 3D transistor 2100, other sizes/dimensions of the 3D transistor 2100 may be larger than the 3D transistor 2000 and/or the size/dimensions of the 3D transistor 2100, such as the channel length (L), the height (H) of the 3D semiconductor body, the width (W) of the 3D semiconductor body, etc. In some embodiments, unlike the 3D transistors 1100 and 2000 of the LLV circuit 902 and the LV circuit 904, the 3D transistor 2100 of the HV circuit 906 further includes a drift region 2110 having a lower doping concentration than the source/drain 2106 in order to maintain a higher voltage of Vdd3 than Vdd2 and Vdd1. In some embodiments, unlike 3D transistors 2000 and 2100 having polysilicon gate and gate oxide gate structures 2008 and 2108 , 3D transistor 1100 has gate structure 1108 of HKMG to achieve faster switching speed than 3D transistors 2000 and 2100 .

25 shows a block diagram of a system 2500 with memory elements in accordance with some aspects of the present disclosure. System 2500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. As shown in FIG. 25 , system 2500 may include a host 2508 and a memory system 2502 having one or more memory elements 2504 and a memory controller 2506 . The host 2508 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host 2508 may be configured to send data to or receive data from memory element 2504 .

The memory element 2504 may be any memory element disclosed herein, such as 3D memory elements 100 and 101 , memory element 200 , 3D memory elements 800 , 801 and 1900 . In some embodiments, each memory element 2504 includes peripheral circuitry with 3D transistors, as described in detail above of.

According to some embodiments, memory controller 2506 is coupled to memory element 2504 and host 2508 and is configured to control memory element 2504 . The memory controller 2506 can manage the memory data in the memory element 2504 and communicate with the host 2508 . In some embodiments, memory controller 2506 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the memory controller 2506 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC) used as data memory for mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise memory arrays. Memory controller 2506 may be configured to control operations of memory element 2504, such as read, erase, and program operations. Memory controller 2506 may also be configured to manage various functions regarding data stored or to be stored in memory element 2504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, memory controller 2506 is also configured to process error correction code (ECC) for data read from or written to memory element 2504 . Any other suitable function may also be performed by memory controller 2506 , such as programming memory elements 2504 . The memory controller 2506 can communicate with external devices (eg, the host 2508) according to a particular communication protocol. For example, the memory controller 2506 may communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, and the like.

Memory controller 2506 and one or more memory elements 2504 may be integrated into various types of memory elements, for example, included in the same package, such as Universal Flash (UFS) package or eMMC package. That is, the memory system 2502 can be implemented and packaged into different types of end electronic products. In one example, as shown in FIG. 26A , memory controller 2506 and individual memory elements 2504 may be integrated into memory card 2602 . The memory card 2602 may include a PC card (PCMCIA, Personal Computer Memory Card Association International), CF card, smart media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 2602 may further include a memory card connector 2604 that couples the memory card 2602 with a host (eg, host 2508 in FIG. 25 ). In another example as shown in FIG. 26B , memory controller 2506 and plurality of memory elements 2504 may be integrated into SSD 2606 . SSD 2606 may also include SSD connector 2608 that couples SSD 2606 to a host (eg, host 2508 in FIG. 25 ). In some embodiments, the memory capacity and/or operating speed of SSD 2606 is greater than the memory capacity and/or operating speed of memory card 2602 .

22A-22J illustrate a fabrication process for forming a 3D transistor according to some aspects of the present disclosure. FIG. 23 shows a flowchart of a method 2300 for forming an exemplary 3D memory element, according to some aspects of the present disclosure. FIG. 24A shows a flowchart of a method 2400 for forming a 3D transistor according to some aspects of the present disclosure. FIG. 24B shows a flowchart of another method 2401 for forming a 3D transistor in accordance with aspects of the present disclosure. Examples of the 3D memory element shown in FIG. 23 include the 3D memory elements 800, 801, and 899 shown in FIGS. 8A-8C. Examples of the 3D transistors shown in FIGS. 22A-22J , 24A, and 24B include the 3D transistors 500 , 1100 , 2000 , and 2100 shown in FIGS. 5 , 11A, 20A, and 21A. 22A-22J, 23, 24A, and 24B will be described together. It should be understood that the operations shown in methods 2300, 2400, and 2401 are not exhaustive, and other operations may also be performed before, after, or between any of the operations shown. Additionally, some operations may be performed simultaneously, or in a different order than that shown in Figures 23, 24A, and 24B.

Referring to FIG. 23, method 2300 begins at operation 2302, wherein a first semiconductor structure including an array of memory cells is formed on a first substrate. In some embodiments, in order to form a memory cell array columns, forming an array of 3D NAND memory strings. For example, as shown in FIG. 8B , an array of 3D NAND memory strings 817 is formed on a substrate 809 . Method 2300 proceeds to operation 2304, as shown in FIG. 23, wherein a first bonding layer including a plurality of first bonding contacts is formed over the array of NAND memory strings. For example, as shown in FIG. 8B , a bonding layer 829 including bonding contacts 855 is formed over the array of 3D NAND memory strings 817 .

Method 2300 proceeds to operation 2306, as shown in FIG. 23, wherein a second semiconductor structure including peripheral circuitry including 3D transistors is formed on a second substrate. The recessed gate transistor may include a recessed gate structure protruding into the second substrate. To form the second semiconductor structure, a 3D semiconductor body is formed from the second substrate, and a gate structure is formed in contact with the sides of the 3D semiconductor body.

3D semiconductor bodies can be formed using various fabrication processes. In some embodiments, to form a 3D semiconductor body, as shown in FIG. 24A , at operation 2402 , trench isolation is formed in the second substrate around a portion of the second substrate. The substrate may be a silicon substrate.

As shown in FIG. 22A, trench isolations 2204, such as STI, are formed in a silicon substrate 2202, eg, using wet/dry etching and thin film deposition of silicon oxide. The top surface of trench isolation 2204 may be planarized using, for example, chemical mechanical polishing (CMP). The trench isolation 2204 can divide the silicon substrate 2202 into a plurality of regions in which a plurality of 3D transistors can be respectively formed. Before forming the trench isolation 2204, a sacrificial layer 2206 may be formed to cover the region of the 3D semiconductor body where the 3D transistor is to be formed. In some embodiments, a sacrificial material layer other than silicon substrate 2202 and trench isolation 2204, such as silicon nitride, is deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The deposited layer of sacrificial material may then be patterned using lithography and wet/dry etching to form sacrificial layer 2206 . Therefore, trench isolation 2204 cannot be formed in the portion of silicon substrate 2202 covered by sacrificial layer 2206 . As a result, as shown in FIG. 22A , the trench isolation 2204 surrounds a portion of the silicon substrate 2202 covered by the sacrificial layer 2206 . Although not shown, wells may subsequently be formed in the silicon substrate 2202 . Wells can be patterned using lithography and isolated in trenches 2204, followed by ion implantation of N-type dopants and/or P-type dopants.

As shown in FIG. 24A , at operation 2404 , the trench isolation is etched back to expose at least a portion of a portion of the second substrate. As shown in FIG. 22B , in accordance with some embodiments, recesses are formed in trench isolation 2204 by etching back and forth, for example, using wet/dry etching, to expose at least a portion of the portion of silicon substrate 2202 covered by sacrificial layer 2206 and surrounded by trench isolation 2204 (eg, in FIG. 22A ). As a result, after recessing (etch back), the exposed portion of the silicon substrate 2202 is now a 3D semiconductor body 2208 over the resulting top surface of the silicon substrate 2202 and trench isolation 2204, according to some embodiments.

As shown in Figures 22A, 22B and 24A, instead of forming the 3D semiconductor body after forming the trench isolation, the 3D semiconductor body may be formed before forming the trench isolation, as shown in Figures 22H, 22I and 24B. In some embodiments, to form a 3D semiconductor body, as shown in FIG. 24B , at operation 2403 , a trench is formed in the second substrate around a portion of the second substrate. As shown in FIG. 22H, trenches 2209 are formed in the silicon substrate 2202, for example, by etching the silicon substrate 2202 using dry/wet etching. In some embodiments, a sacrificial layer 2206 is formed prior to etching to cover the portion of the silicon substrate 2202 where the 3D semiconductor body 2208 is to be formed. As a result, according to some embodiments, a portion of the silicon substrate 2202 is surrounded by the trench 2209 .

As shown in FIG. 24B , at operation 2405 , an isolation material is deposited to partially fill the trench, thereby exposing at least a portion of portions of the second substrate. As shown in FIG. 22I , trench isolation 2204 is formed in trench 2209 by depositing an isolation material such as silicon oxide into trench 2209 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) (eg, as shown in FIG. 22H ). To form 3D semiconductor body 2208 , the deposition rate and/or duration may be controlled to partially fill trench 2209 , thereby exposing at least a portion of portions of silicon substrate 2202 . As a result, after formation of trench isolation 2204 , the exposed portion of silicon substrate 2202 now becomes 3D semiconductor body 2208 over the resulting top surface of silicon substrate 2202 and trench isolation 2204 , according to some embodiments.

Referring back to FIG. 22C, after forming the 3D semiconductor body 2208, whether it is forming the trench Whether trench isolation 2204 is formed before or after sacrificial layer 2206 is removed, eg, by wet/dry etching (eg, as shown in FIGS. 22B and 22I ).

In some embodiments, to form the gate structure, as shown in Figures 24A and 24B, at operation 2406, a gate dielectric layer and a gate electrode layer are subsequently formed on the sides of the 3D semiconductor body. As shown in FIG. 22D , a gate dielectric layer 2210 , such as a silicon oxide layer or a high-K dielectric layer, is formed on multiple sides of the 3D semiconductor body 2208 . In some embodiments, a layer of dielectric material is deposited onto all exposed surfaces of the 3D semiconductor body 2208 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments where the gate dielectric layer 2210 is a silicon oxide layer, dry/wet oxidation is used to oxidize portions of the silicon at exposed surfaces in the 3D semiconductor body 2208 to form the gate dielectric layer 2210 .

As shown in FIG. 22E , a gate electrode layer 2212 such as a doped polysilicon layer or a metal layer is formed over the gate dielectric layer 2210 . In some embodiments, a layer of semiconductor or conductive material is deposited over gate dielectric layer 2210 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments where the gate electrode layer 2212 is a polysilicon layer, in-situ doping is performed to dope the polysilicon layer, or a doping process such as ion implantation is performed after deposition to dope the polysilicon layer.

In some embodiments, to form the gate structure, as shown in FIGS. 24A and 24B , at operation 2408 , the gate electrode layer is patterned to form the gate electrode. As shown in FIG. 22F , gate electrode layer 2212 (eg, as shown in FIG. 22E ) is patterned to form gate electrode 2214 , eg, using lithography and wet/dry etching.

As shown in Figures 24A and 24B, at operation 2410, a source and a drain are formed in the 3D semiconductor body. In some embodiments, the portion of the 3D semiconductor body not covered by the gate structure is doped in order to form the source and drain. As shown in FIG. 22G , a pair of source and drain electrodes 2216 is formed in the 3D semiconductor body 2208 by doping the portion of the 3D semiconductor body 2208 not covered by the gate electrode 2214 , for example using ion implantation. As a result, according to some embodiments, the source and drain 2216 are not formed directly on the gate electrode 2214 below to allow a channel to form between the source and drain 2216 . Although not shown, in some embodiments, portions of gate dielectric layer 2210 overlying source and drain 2216 are removed, such as by dry/wet etching, to expose portions of source and drain 2216 upon which source and drain contacts (not shown) may be formed.

According to some embodiments, a 3D transistor is thus formed having a 3D semiconductor body 2208 , a gate electrode 2214 , a gate dielectric layer 2210 , and a source and drain 2216 . It should be understood that since the aforementioned manufacturing process for forming a 3D transistor is compatible with the manufacturing process for forming a planar transistor, in some examples, the same manufacturing process as described above may be used to form a planar transistor having the same trench isolation depth as a 3D transistor or a different trench isolation depth. In one example, the fabrication process described in FIG. 24A can be used to form 3D transistors and planar transistors with the same trench isolation depth. The same trench isolation depth may be determined by forming trench isolation 2204 before forming 3D semiconductor body 2208 . In another example, the fabrication process described in FIG. 24B can be used to form 3D transistors and planar transistors with different trench isolation depths.

In order to form the 3D transistor and the planar transistor with the same trench isolation depth, as shown in FIGS. 22A-22G , the 3D transistor can be formed in the first region 2201 and the planar transistor can be formed in the second region 2203 of the same silicon substrate 2202 . As shown in FIG. 22A , trench isolation 2204 , such as STI, may be formed in both the first region 2201 and the second region 2203 to form 3D transistors and planar transistors, respectively, in the same fabrication process described in detail above with respect to FIG. 22A . Therefore, trench isolation 2204 for 3D transistors and trench isolation 2204 for planar transistors may have the same depth. As shown in FIG. 22B , the etch back of the trench isolation 2204 may be performed only in the first region 2201 and not in the second region 2203 . That is, according to some embodiments, when the trench isolations 2204 for 3D transistors are formed in the first region 2201 , the trench isolations 2204 for planar transistors in the second region 2203 remain unchanged without grooves. In some embodiments, before etching back the trench isolation 2204 in the first region 2201 , an etch mask is patterned to cover the second region 2203 and only expose the first region 2201 to protect the trench isolation 2204 in the second region 2203 . As shown in FIG. 22C, in both the first region 2201 and the second region 2203 The sacrificial layer 2206 may be removed during the same fabrication process described in detail above with respect to Figure 22C. As shown in FIG. 22D , the gate dielectric layer 2211 of the planar transistors in the second region 2203 may be formed in the same fabrication process as was used to form the gate dielectric layer 2210 of the 3D transistors in the first region 2201 as described in detail above with respect to FIG. 22D . As shown in FIG. 22E , gate electrode layer 2212 may be formed over gate dielectric layers 2210 and 2211 in both first region 2201 and second region 2203 in the same fabrication process as described in detail above with respect to FIG. 22E . As shown in FIG. 22F , the gate electrode 2215 of the planar transistor in the second region 2203 can be patterned from the gate electrode layer 2212 in the same fabrication process as described in detail above with respect to FIG. 22F for patterning the gate electrode 2214 of the 3D transistor in the first region 2201 . As shown in FIG. 22G , the pair of source and drain 2217 of the planar transistor in the second region 2203 may be formed in the same fabrication process as was used to form the pair of source and drain 2216 of the 3D transistor in the first region 2201 as described in detail above with respect to FIG. 22G . According to some embodiments, a planar transistor with gate electrode 2215, gate dielectric layer 2211, and source and drain 2217 is thus formed in the same process flow as used to form a 3D transistor with 3D semiconductor body 2208, gate electrode 2214, gate dielectric layer 2210, and source and drain 2216 (except for the etch-back process in FIG. 22B ).

It should also be understood that 3D transistors with different isolation trench depths can be formed by varying the groove depth when etching back the trench isolation 2204, e.g., for peripheral circuits with different applied voltages (e.g., LLV circuit 902, LV circuit 904, and HV circuit 906). As shown in FIG. 22J , the 3D semiconductor body 2219 in the third region 2205 of the silicon substrate 2202 may have a different groove depth than the 3D semiconductor body 2208 in the first region 2201 in FIG. 22D by etching back different groove depths of the trench isolation 2204 in the first region 2201 and the third region 2205. In some embodiments, the 3D semiconductor body 2219 is part of a 3D transistor in the HV circuit 906 and the 3D semiconductor body 2208 is part of a 3D transistor in the LLV circuit 902 and/or the LV circuit 904, and the first groove depth used to form the 3D semiconductor body 2219 is greater than the second groove depth used to form the 3D semiconductor body 2208. In one example, the first groove depth can be between 300nm and 400nm, and the second groove depth can be between 50nm and 100nm between.

Referring to FIG. 23 , method 2300 proceeds to operation 2308 where a second bonding layer including a second plurality of bonding contacts is formed over the peripheral circuitry. For example, as shown in FIG. 8B , a bonding layer 851 including bonding contacts 853 is formed over the 3D transistor 839 in the peripheral circuit 835 . Method 2300 proceeds to operation 2310, as shown in FIG. 23, where the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the memory cell array is coupled to peripheral circuitry across the bonded interface. Bonding can be mixed bonding. In some embodiments, the second semiconductor structure is over the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is over the second semiconductor structure after bonding.

As shown in FIG. 8A , the second semiconductor structure 804 with the 3D NAND memory strings 838 is turned upside down. The downward-facing bonding layer 826 is bonded to the upward-facing bonding layer 822 , ie, in a face-to-face manner, thereby forming the bonding interface 806 . In some embodiments, a treatment process, such as plasma treatment, wet treatment, and/or heat treatment, is applied to the bonding surface prior to bonding. After bonding, bonding contacts 828 in bonding layer 826 and bonding contacts 824 in bonding layer 822 are aligned and contact each other so that 3D NAND memory string 838 can be coupled to component layer 810 (eg, peripheral circuits 812 and 814). Similarly, as shown in FIG. 8B , the first semiconductor structure 805 with peripheral circuits 835 and 837 is turned upside down. The downward-facing bonding layer 851 is bonded to the upward-facing bonding layer 829 , ie, in a face-to-face manner, thereby forming a bonding interface 807 . After bonding, bonding contacts 853 in bonding layer 851 and bonding contacts 855 in bonding layer 829 are aligned and contact each other so that 3D NAND memory string 817 can be coupled to component layer 831 (eg, peripheral circuits 835 and 837).

Method 2300 proceeds to operation 2312, where after bonding, the other of the first and second substrates over one of the first and second substrates is thinned, as shown in FIG. 23 . As shown in FIG. 8A, since the base of the second semiconductor structure 804 having the 3D NAND memory string 838 is above the base of the first semiconductor structure 802 having the peripheral circuits 812 and 814, the base of the second semiconductor structure 804 is thinned using CMP and/or etching processes to form a semiconductor layer 848. Similarly, as shown in FIG. 8B, since the substrate of the first semiconductor structure 805 having the peripheral circuits 835 and 837 is placed on the 3D NAND memory string 817 Above the base of the second semiconductor structure 803 , the base of the first semiconductor structure 805 is thinned using CMP and/or etching processes to form a semiconductor layer 833 .

Method 2300 proceeds to operation 2314, as shown in FIG. 23, where an interconnect layer is formed on the thinned first or second substrate. As shown in FIG. 8A, a pad output interconnect layer 850 is formed over the semiconductor layer 848 (thinned top substrate). Similarly, as shown in FIG. 8B , a pad output interconnect layer 843 is formed over the semiconductor layer 833 (thinned top substrate).

According to an aspect of the present disclosure, a memory device includes a memory cell array and a plurality of peripheral circuits coupled to the memory cell array and configured to control the memory cell array. The first peripheral circuit of the plurality of peripheral circuits includes a first 3D transistor. The first 3D transistor includes a 3D semiconductor body and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode includes metal, and the gate dielectric has a thickness between 1.8 nm and 10 nm.

In some embodiments, the top surface of the gate structure is curved.

In some embodiments, the gate dielectric includes silicon oxide and has a thickness between 2 nm and 4 nm.

In some embodiments, the first 3D transistor is a multi-gate transistor.

In some embodiments, the gate dielectric includes a high-K dielectric.

In some embodiments, the width of the 3D semiconductor body is between 10 nm and 180 nm. In some embodiments, the width of the 3D semiconductor body is between 30 nm and 100 nm.

In some embodiments, the channel length of the 3D semiconductor body is between 30 nm and 180 nm. In some embodiments, the channel length of the 3D semiconductor body is between 50 nm and 120 nm.

In some embodiments, the height of the 3D semiconductor body is between 40 nm and 300 nm. In some embodiments, the height of the 3D semiconductor body is between 50 nm and 100 nm.

In some embodiments, the first peripheral circuit further includes another 3D transistor, and the first Trench isolation between a 3D transistor and another 3D transistor. In some embodiments, the thickness of the trench isolation is the same as the height of the 3D semiconductor body.

In some embodiments, the memory element further includes a first voltage source coupled to the first peripheral circuit and configured to provide a first voltage to the first 3D transistor. In some embodiments, the first voltage is between 0.9V and 1.2V.

In some embodiments, the first voltage is 1.2V.

In some implementations, the first peripheral circuit is an I/O circuit.

In some embodiments, the second peripheral circuit of the plurality of peripheral circuits includes a second 3D transistor, and the thickness of the gate dielectric of the second 3D transistor is greater than the thickness of the gate dielectric of the first 3D transistor.

In some embodiments, the second 3D transistor further includes a drift region.

In some embodiments, the memory element further includes a second voltage source coupled to the second peripheral circuit and configured to provide a second voltage to the second 3D transistor. In some embodiments, the second voltage is greater than the first voltage applied to the first 3D transistor.

In some embodiments, the second voltage is greater than 1.2V.

In some implementations, a third peripheral circuit of the plurality of peripheral circuits includes a planar transistor.

In some embodiments, the array of memory cells includes an array of 3D NAND memory strings.

According to another aspect of the present disclosure, a memory device includes an array of memory cells and I/O circuitry coupled to the array of memory cells and configured to interface the array of memory cells with a memory controller. The I/O circuit includes 3D transistors.

In some embodiments, the memory element further includes a voltage source coupled to the I/O circuit and configured to provide a voltage to the 3D transistor. In some embodiments, the voltage is between 0.9V and 1.2V.

In some embodiments, the voltage is 1.2V.

In some embodiments, the first 3D transistor is a multi-gate transistor.

In some embodiments, the multi-gate transistors include FinFETs.

In some embodiments, the multi-gate transistor includes a GAA FET.

In some embodiments, the first 3D transistor includes a 3D semiconductor body and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure may include a gate dielectric and a gate electrode. In some embodiments, the gate dielectric includes silicon oxide and has a thickness between 1.8 nm and 10 nm.

In some embodiments, the thickness of the gate dielectric is between 2 nm and 4 nm.

In some embodiments, the gate dielectric includes a high-K dielectric.

In some embodiments, the width of the 3D semiconductor body is between 10 nm and 180 nm. In some embodiments, the width of the 3D semiconductor body is between 30 nm and 100 nm.

In some embodiments, the channel length of the 3D semiconductor body is between 30 nm and 180 nm. In some embodiments, the channel length of the 3D semiconductor body is between 50 nm and 120 nm.

In some embodiments, the height of the 3D semiconductor body is between 40 nm and 300 nm. In some embodiments, the height of the 3D semiconductor body is between 50 nm and 100 nm.

In some embodiments, the array of memory cells includes an array of 3D NAND memory strings.

According to yet another aspect of the present disclosure, a system includes a memory element configured to store data. The memory element includes an array of memory cells and I/O circuitry coupled to the array of memory cells and configured to interface the array of memory cells with a memory controller. The I/O circuit includes 3D transistors. The system also includes a memory controller coupled to the memory element and configured to control the array of memory cells through the I/O circuit.

In some implementations, the system further includes a host coupled to the memory controller and configured to send or receive data.

The foregoing description of specific embodiments can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in light of the appended claims and their equivalents. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

800:3D memory components

802: The first semiconductor structure

804: Second semiconductor structure

806: Bonding interface

808: base

810: component layer

812: The first peripheral circuit

814: The second peripheral circuit

816:Transistor

818:transistor

820: interconnect layer

822: Bonding layer

824: Bonding contacts

826: Bonding layer

828: Bonding contacts

830: Interconnect layer

832:Memory stack

834: conductive layer

836: dielectric layer

838:3D NAND memory string

848:Semiconductor layer

850:Pad output interconnection layer

852: Contact pad

854: contact

860: Trench isolation

862: Trench isolation

Claims (19)

A memory element, comprising: a memory cell array; and a plurality of peripheral circuits coupled to the memory cell array and configured to control the memory cell array, wherein a first peripheral circuit in the plurality of peripheral circuits includes a first three-dimensional (3D) transistor; a second peripheral circuit in the plurality of peripheral circuits includes a second 3D transistor, and a gate dielectric of the second 3D transistor has a thickness greater than a gate dielectric of the first 3D transistor; the first 3D transistor includes 3 D. A semiconductor body and a gate structure in contact with sides of the 3D semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; the gate electrode comprising a metal; and the gate dielectric having a thickness between 1.8 nm and 10 nm. The memory device of claim 1, wherein the top surface of the gate structure is curved. The memory device according to claim 2, wherein the thickness of the gate dielectric is between 2nm and 4nm. The memory device according to claim 1, wherein the first 3D transistor is a multi-gate transistor. The memory device of claim 1, wherein the gate dielectric comprises a high-k dielectric. The memory element according to claim 1, wherein the width of the 3D semiconductor body is between 10nm and 180nm; the channel length of the 3D semiconductor body is between 30nm and 180nm; and the height of the 3D semiconductor body is between 40nm and 300nm. The memory element according to claim 6, wherein the first peripheral circuit further includes: another 3D transistor; and trench isolation, between the first 3D transistor and the other 3D transistor, the thickness of the trench isolation is the same as the height of the 3D semiconductor body. The memory device according to claim 1, further comprising a first voltage source coupled to the first peripheral circuit and configured to provide a first voltage to the first 3D transistor, wherein the first voltage is between 0.9V and 1.2V. The memory device according to claim 1, wherein the first peripheral circuit is an input/output (I/O) circuit. The memory device according to claim 1, wherein the second 3D transistor further includes a drift region. The memory device according to claim 8, further comprising a second voltage source coupled to the second peripheral circuit and configured to provide a second voltage to the second 3D circuit crystal, wherein the second voltage is greater than the first voltage applied to the first 3D transistor. The memory device according to claim 11, wherein the second voltage is greater than 1.2V. The memory device according to claim 1, wherein a third peripheral circuit of the plurality of peripheral circuits includes a planar transistor. The memory device according to claim 1, wherein the memory cell array comprises a 3D NAND memory string array. A memory element comprising: a memory cell array; an input/output (I/O) circuit coupled to the memory cell array and configured to interface the memory cell array with a memory controller, wherein the I/O circuit includes a first three-dimensional (3D) transistor; and a peripheral circuit coupled to the memory cell array and configured to control the memory cell array, the peripheral circuit including a second 3D transistor, and a gate dielectric of the second 3D transistor The thickness of is greater than the thickness of the gate dielectric of the first 3D transistor. The memory device of claim 15, further comprising a voltage source coupled to the I/O circuit and configured to provide a voltage to the first 3D transistor, wherein the voltage is between 0.9V and 1.2V. The memory element according to claim 15, wherein the first 3D transistor includes a 3D semiconductor body and a gate structure in contact with multiple sides of the 3D semiconductor body, the gate structure includes a gate dielectric and a gate electrode; the gate electrode includes metal; and the thickness of the gate dielectric is between 1.8 nm and 10 nm. The memory device according to claim 15, wherein the memory cell array comprises a 3D NAND memory string array. A system having a memory element, comprising: a memory element configured as memory data and comprising: an array of memory cells; an input/output (I/O) circuit coupled to the array of memory cells and configured to interface the array of memory cells with a memory controller, wherein the I/O circuit includes a first three-dimensional (3D) transistor; and a peripheral circuit coupled to the array of memory cells and configured to control the array of memory cells, the peripheral circuit including a second 3 D transistor, and the thickness of the gate dielectric of the second 3D transistor is greater than the thickness of the gate dielectric of the first 3D transistor; and a memory controller, coupled to the memory element and configured to control the memory cell array through the I/O circuit.