KR20160020347A - Methods and apparatus for bump-on-trace chip packaging - Google Patents

Abstract

A method for attaching a first substrate to a second substrate and a device thereof are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attachment region to which a second substrate is attached. A limit region, for example a region between the second substrate and the protective layer, is a region around the second substrate in or from which the protective layer is not formed or is removed. The limit region is sized so that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids, and allowing traces in the limit region to be covered by the underfill.

Description

[0001] METHODS AND APPARATUS FOR BUMP-ON-TRACE CHIP PACKAGING [0002]

Priority claim and cross-reference

This application claims priority to U.S. Patent Application No. 13 / 450,191 entitled " Methods and Apparatus for Bump-on-Trace Chip Packaging "filed April 18, Which is hereby incorporated by reference in its entirety.

An integrated circuit or chip consists of millions of active and passive devices such as transistors and capacitors. These devices are initially isolated from each other and are then interconnected to form an integrated circuit. A connector structure is also formed for the integrated circuit, which may include a bond pad or metal bump formed on the surface of the circuit. Electrical connections are made through bond pads or metal bumps to connect the chip to a package substrate or other die. Generally, a chip can be fabricated using a pin grid array (PGA) or a ball grid array (BGA) and a semiconductor device using wire bonding (WB) or flip chip (FC) They may be assembled in the same package.

Flip chip (FC) packaging techniques may use a bump-on-trace (BOT) structure to connect a chip to a package substrate where the connection is made through a metal bump, To the metal traces of the trenches. The BOT structure provides a low cost alternative to the microelectronic packaging industry. However, as the substrate structure becomes thinner, a reliability problem arises for the BOT structure.

When using the BOT structure, the bumps for the chip are soldered onto the traces on the package substrate by a reflow process. When the bump is bonded to the substrate and cooled from the reflow conditions at room temperature, the thermal force generated by the coefficient of thermal expansion (CTE) promotes substrate shrinkage and induces relative torsion on each bump. Once the stress level rises above the adhesion criterion between the substrate and the trace, a trace peel failure occurs.

A method and apparatus for attaching a first substrate to a second substrate are provided. In some embodiments, the first substrate has a protective layer, such as a solder mask, around the die attach region to which the second substrate is attached. The restriction region (for example, the region between the second substrate and the protection layer) is a region around the second substrate where the protection layer is not formed or removed. The confinement region is dimensioned such that there is sufficient clearance between the second substrate and the protective layer to reduce or prevent pores and to allow traces within the confinement region to be covered by the underfill and to place the underfill between the first substrate and the second substrate Respectively.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that according to industry standard practice, the various features are not shown to scale up. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows an embodiment of a chip on a bump-on-trace (BOT) structure for forming a flip chip (FC) package.
Figures 2A-2C illustrate an embodiment of a method and apparatus of a solder mask trench used in a BOT structure to form an FC package.
3 is a plan view of a plurality of bumps connected to a trace in a plurality of solder mask trench rings used in a BOT structure.
4A-6B are various top and cross-sectional views of intermediate process steps in accordance with some embodiments.
7 is a flow diagram illustrating a method of manufacturing according to some embodiments.

The following description provides a number of different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and devices are described below to simplify the present disclosure. These are, of course, examples only and are not intended to be limiting. For example, in the following description, the formation of the first feature on or above the second feature may include an embodiment in which the first and second features are formed in direct contact, and the additional features may include first and second May also be formed between the features so that the first and second features may not be in direct contact. In addition, the present specification may repeat drawing numbers and / or characters in various examples. This repetition is for simplicity and clarity, and does not indicate the relationship between the various embodiments and / or configurations described in themselves.

Also, spatial relative terms such as "bottom", "bottom", "bottom", "top", "top" may refer to one element (s) for another element (s) or feature (s) Or < / RTI > features of the present invention for ease of description. Spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientations shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and spatial relative descriptors used herein may be interpreted accordingly.

As illustrated below, a method and apparatus for a solder mask trench used in a BOT structure to form a semiconductor package is disclosed. A solder mask layer is formed on the trace and on the substrate. An opening in the solder mask layer, referred to as a solder mask trench, is formed to expose traces on the substrate. A chip is connected to the exposed trace in the solder mask trench. By the formation of the solder mask trenches, the traces exposed in the trenches can have a better grab force, which reduces the trace peeling failure for the semiconductor package.

1 is a schematic diagram of an exemplary embodiment of a chip 201 on a bump-on-trace (BOT) structure for forming a flip chip (FC) package. The substrate 206 may have a plurality of sub-layers. The two sublayers of the substrate 206 shown in FIG. 1 are for illustration purposes only, and are not limiting. The plurality of balls 207 under the substrate 206 may form a ball grid array (BGA). Chip 201 is connected to substrate 206 by a plurality of interconnects wherein each interconnect includes a Cu pillar bump or post 202 and a solder bump 203. A solder bump (203) is disposed on the trace (204) formed on the substrate (206). A solder mask 211 is formed on the surface of the substrate 206 covering the traces. An opening in the solder mask, referred to as a solder mask trench that exposes the trace 204, is formed. The space between the chip 201 and the substrate 206 may be filled with a compound to form an encapsulation body 205.

2A illustrates an embodiment of a single solder mask trench 210 on a substrate 206, which may be any trench in FIG. 1, wherein the trench is exposed and a connection to chip 201 is configured have. A trace 204 is formed on the surface of the substrate 206. A solder mask layer 211 may be formed on the surface of the substrate 206 and traces covering the traces. A trench may be opened into the solder mask layer 211 to form a solder mask trench 210 to expose the trace 204. [ The trenches have openings large enough such that the interconnects, such as solder balls 203, may land directly on the traces received in the openings. For example, the solder mask trench has approximately the size of the diameter of the solder bump. Traces 204 may be connected to chip 201 via interconnects. The interconnects may include posts such as solder bumps 203 and Cu pillars 202 where the solder balls 203 are placed directly on the traces 204 and surrounded by solder mask trenches. The structure shown in FIG. 2A is for illustrative purposes only, and is not limiting. Additional embodiments are contemplated.

Figure 2B shows a top view with the posts 202 on the traces 204 surrounded by the solder mask 211. Chip 201 and substrate 206 are not shown in FIG. 2B.

Figure 2C illustrates an exemplary process for fabricating the embodiment shown in Figure 2A. Details of the process shown in FIG. 2C are described below.

The process begins at step 220, where a substrate, such as the substrate 206 of FIG. 2A, is provided. The substrate 206 may provide an interface that allows mechanical support for the package and access to external components to the device in the package. The substrate 206 may comprise an active layer of doped or undoped bulk silicon, or a silicon-on-insulator (SOI) substrate. The other substrate may include a multilayer substrate, a gradient substrate, or a hybrid alignment substrate. Substrate 206 may also be a laminate substrate formed as a stack of multiple thin layers of polymeric material, such as bismaleimide triazine.

Trace 204 may be on the surface of substrate 206. Trace 204 may be for extending the footprint of the die. The width or diameter of the trace may be approximately equal to the ball (or bump) diameter, and may be two to four times narrower than the ball (or bump) diameter. For example, trace 204 may have a line width of about 10 [mu] m to 40 [mu] m and a trace pitch (P) of about 30 [mu] m to 70 [mu] m. The traces may have a narrow, wide, or tapered shape. The distal end of the trace may be of a different shape than the body of the trace. The trace body may have a substantially constant thickness. The end of the trace and the body of the trace are formed as a single piece, which is different from placing the pad on the trace. The traces may have a length that is substantially longer than the ball (or bump) diameter. On the other hand, the connection pad may have a length or width similar to the diameter of the ball or bump.

Multiple traces, each electrically isolated from each other, may be present on the substrate, and the spacing between two adjacent traces may be between about 10 [mu] m and 40 [mu] m.

Traces 204 may include conductive materials such as, for example, Al, Cu, Au, alloys thereof, other materials, or combinations thereof and / or multiple layers. Alternatively, the trace 204 may comprise other materials. In some embodiments, the dielectric layer may cover several portions of the trace 204. Trace 204 may be covered by a metallic finish, such as a layer of organic film or mixed material, such as Ni / Pd / Au, coated on traces 204.

Trace 204 and the substrate are connected only by interfacial adhesion between them, which may not be sufficient to hold the trace 204 and the substrate 206 to form a strong connection therebetween.

At step 221, a solder mask layer, such as the solder mask layer 211 shown in FIG. 2A, may be formed on the surface of the substrate 206 to cover the traces 204 and the surface of the substrate. The solder mask layer 211 includes electrical insulation resistance, chemical and corrosion resistance or protection, mechanical (scratch, abrasion) protection, boundary on the solder surface, additional grip on the trace, and improved dielectric reliability between the circuit traces on the substrate , Or may perform a number of functions. The solder mask layer is used to provide additional gripping forces between the traces 204 and the substrate 206 because the solder mask, the traces, and the substrate form a sandwich structure where the solder mask and substrate "clips" to provide.

The solder mask layer 211 may be formed in a single step by screening the wet film on the substrate surface and then curing the wet film by oven baking. The thickness of the solder mask layer 211 may be about 30 to 40 microns (typically about 35 microns). The solder mask layer may comprise a polymeric material.

In step 223, the trench may be opened in the solder mask layer 211 to form a solder mask trench 210 for exposing the trace 204, as shown in FIG. 2A. The trenches have openings large enough such that the interconnects, such as solder balls 203, may land directly on the traces received in the openings. A wider opening for hosting the solder ball may increase the connection strength between the solder ball and the trace. Thus, the size of the openings is elastic and may vary depending on the size of the solder balls used to connect the traces. The solder mask layer 211 formed by the wet film can be screened with a pattern for forming the solder mask trench 210. [ For example, a solder mask layer having solder mask trenches may be first placed on the rollers for printing on the substrate. Alternatively, a photosensitive material may be used to pattern the solder mask trench 210 into the cured film. The solder mask trenches 210 may be formed to expose the traces 204 to further form appropriate electrical connections with the die to be mounted on the substrate.

A solder flux (not shown) may be applied to the trace. The flux mainly serves to assist the flow of the solder so that the solder balls 203 make good contact with the traces on the substrate. This may be applied to any of a variety of methods, including brushing or spraying. The flux generally has an acidic component that removes the oxide barrier from the solder surface and an adhesive nature that helps prevent the chip from moving on the substrate surface during the assembly process.

At step 227, the chip 201 may be connected to the trace 204 via interconnects of the chips, as shown in FIG. 2A. As shown in FIG. 2A, the interconnects may include posts such as solder bumps 203 and Cu pillars 202. The trenches have openings large enough so that the solder balls 203 may land directly on the traces contained in the openings.

The solder bumps 203 of the chip 201 may be disposed on the traces 204 exposed by the solder mask trenches. The solder bumps 203 may comprise a material such as tin or other suitable materials such as silver, lead-free tin, copper, combinations thereof, and the like. In embodiments where the solder bumps 203 are tin solder bumps, the solder bumps 203 may be initially formed by methods such as evaporation, electrolytic plating, printing, solder transfer, or ball placement to a thickness of, for example, about 15 [ And then performing reflow to form the material into the desired bump shape. Any suitable method of manufacturing the solder bumps 203 may alternatively be used.

A chip such as chip 201 shown in Figure 2A may be connected to trace 204 by solder bump 203 and post 202. [ A post 202 may be formed on the chip 201. Post 202 may be a Cu pillar or other metal with a melting temperature above 300 ° C. The chip 201 may be aligned so that the posts 202 are disposed on the solder bumps 203. The chip may be a memory chip, or any other functional chip.

The posts 202 and the solder bumps 203 together form the interconnections of the chips. Post 202 and solder bump 203 may be formed in a plurality of shapes as appropriate to avoid nearby components and to control the area of connection between chip 201 and trace 204 or for other suitable reasons. The interconnections may be in the form of elongated hexagons, ellipses, or diamonds having two trapezoids at opposite ends of a circle, octagon, rectangle, and elongated hexagon.

In step 231, a reflow process is performed. After the chip 201 is bonded to the trace as shown in Figure 2A, heat may be applied to the chip 201 and the substrate 206 such that the solder ball 203 reflows to the chip 201 Thereby forming electrical connections between the substrates 206. In one embodiment, the heat may be about 220 < 0 > C.

In step 233, an underfill material, typically a thermosetting epoxy, may be dispensed into the gap between the chip 201 and the substrate 206. The beads of the thermosetting epoxy may be applied along one edge of the chip, where the epoxy is sucked down the chip by capillary action until the gap between the chip and the substrate is completely filled. It is important that the underfill material is uniformly distributed within the gap.

Individual beads of epoxy may also be dispensed and bonded around the perimeter of the chip 201. Thereafter, both the underfill and the primary bonded epoxy are cured by heating the substrate and the chip to an appropriate curing temperature, which forms an encapsulated body, such as the encapsulated body 205 shown in FIG. The encapsulation body 205 fills the gap between the chip 201 and the substrate 206. In this way, the process produces a mechanically, as well as electrically bonded semiconductor chip assembly when the process ends.

3 shows a top view of a substrate of a semiconductor package formed by a BOT structure. The surface of the substrate may be covered by a solder mask except for the region 301. [ The solder mask may likewise cover the surface of a substrate of another shape. There may be a plurality of solder mask trenches 311 formed on the solder mask layer. The solder mask trench surrounds the central region of the substrate and forms a plurality of solder mask trench rings. The shape of the solder mask trenches follows the contours of the traces on the substrate. Other shapes may be present instead of the formed solder mask ring. There are three such solder mask trench rings formed in Fig. There may be other numbers of solder mask trench rings formed. A plurality of posts or interconnects, such as 2021 and 2022, may be disposed on the exposed traces in the solder mask trenches. The pitch between two posts or two interconnects may be less than about 140 um.

In another embodiment, the solder mask is removed from a die attach region, such as a region where a die or other substrate may be attached, and a keep-out region (e.g., an area immediately surrounding the die attach region) . As will be described in more detail below, the solder mask material is removed so that the area immediately beneath the die and the immediately surrounding area can be removed. The size of the area from which the solder mask material is removed is greater than the size of the die. The size of the area from which the solder mask material is removed ensures that the transverse area between the edge of the die and the edge of the solder mask does not leave exposed traces and the underfill material is applied in such a way as to completely fill the area between the die and the underlying substrate .

For example, in some situations where the lateral area between the edge of the die and the edge of the solder mask is too small, the underfill material may not completely fill the area between the die and the underlying substrate, Allowing the formation of one or more voids. In other situations where the lateral area between the edge of the die and the edge of the solder mast is too large, the trace may be exposed and held. By controlling the width of the distance between the edge of the die and the edge of the solder mask and / or by controlling the ratio of the area of the area between the edge of the die to the edge of the die to the area of the die and the edge of the solder mask, To cover the traces so as to provide protection to the electrical contacts between the die and the underlying substrate and to the traces on the underlying substrate.

It should be noted that the description herein refers to a die attached to a substrate for illustrative purposes to illustrate features of various embodiments. In other embodiments, the die may be another substrate, such as a package, a packaging substrate, an interposer, a die, a printed circuit board, or the like. Similarly, the underlying substrate may be, for example, a package, a packaging substrate, an interposer, a die, a printed circuit board, and the like.

Thus, Figures 4a-b illustrate various intermediate stages in the process of forming some embodiments, wherein the "a" drawing is a plan view and the "b" to be. Referring first to Figs. 4A and 4B, a top view of the first substrate 402 and a cross-sectional view taken along line B-B of Fig. 4A are shown. The first substrate 402 may be, for example, an integrated circuit die, a packaging substrate, a wafer, a printed circuit board, an interposer, or the like. In some embodiments, a BOT configuration is used. For example, FIGS. 4A and 4B illustrate trace 401. FIG. Generally, trace 404 is intended to route the electrical signal to a desired location and / or to extend the footprint of the die. The width or diameter of the trace 404 may be approximately the same as the ball (or bump) diameter, or may be two to four times narrower than the ball (or bump) diameter. For example, trace 404 may have a line width of about 10 [mu] m to 40 [mu] m and a trace pitch P of about 30 [mu] m to 70 [mu] m. The traces may have a narrow, wide, or tapered shape. In some embodiments, the body of the traces may be of a different shape than the body of the traces, or the body of traces may have a substantially constant thickness. The end of the trace and the body of the trace are formed as a single piece, which is different from placing the pad on the trace. The traces may have a length that is substantially longer than the ball (or bump) diameter. On the other hand, the connection pad may have a length or width similar to the diameter of the ball or bump.

In some embodiments, trace 404 may comprise a conductive material such as, for example, Al, Cu, Au, alloys thereof, other materials, or combinations thereof and / or multiple layers. Alternatively, the trace 404 may comprise other materials. Trace 204 may be covered by a metallic finish such as a layer of organic film or mixed material such as Ni / Pd / Au coated on traces 404. In some embodiments, the pitch between adjacent traces may be between about 10 [mu] m and 40 [mu] m.

4A and 4B also illustrate a protective layer 406. The protective layer 406 is shown in FIG. In general, the protective layer 406 may be formed of any suitable material, such as protection from environmental contaminants, electrical insulation resistance between circuit traces on the substrate, chemical and corrosion resistance or protection, mechanical (scratch, abrasion) protection, Additional gripping power on the substrate, and improved dielectric reliability. In some embodiments, the protective layer 406 is, for example, a polymer or other dielectric material. In some embodiments, the protective layer 406 is a polymer that is formed, patterned, and then cured, for example, by screening or spin coating.

The protective layer 406 covers a portion of the trace 404, such as a portion of the trace in the peripheral region of the first substrate 402. For example, in the embodiment shown in FIG. 4A, the protective layer 406 is formed around and separated from the die attach region 408 represented by the dashed outline in FIG. 4A. As will be described in greater detail below, the die attach region 408 represents an area in which another substrate is to be placed. The protective layer 406 will protect the traces 404 from external environmental contaminants and is sized to completely fill the area between the die and the first substrate 402 while covering the exposed traces 404. The thickness of the protective layer 412 may be from about 30 microns to about 40 microns, for example about 35 microns.

Referring now to FIGS. 5A and 5B, a first substrate 402 of FIGS. 4A and 4B is shown after a second substrate 520 according to some embodiments is attached to a first substrate 402. The second substrate 520 may be, for example, a die, a substrate, a wafer, a packaging substrate, a printed circuit board, or the like. The second substrate 520 is electrically coupled to the first substrate by an electrical connector 522. In some embodiments, the electrical connector 522 includes a conductive pillar 522a (e.g., a copper pillar) and a solder material 522b coupled thereto, although other electrical connectors may be used.

In some embodiments, the first substrate 402 is an integrated circuit die, the second substrate 404 is a wafer, and these substrates are bonded to a flip-chip chip-scale package (FCCSP) . The wafer may then be singulated to form individual packages. However, other configurations may be used.

5A and 5B, a keep-out-region (KOR) 524 extends between the second substrate 520 and the protective layer 406 and extends around the second substrate 520 do. In some embodiments, KOR (524) is an inner edge of the protective layer 406 limits away comprises a region that is spaced apart from the edge of the second substrate (520), (D ₁₎ (keep-out distance KOD) . In some embodiments, the area of the KOR 524 is between about 5% and about 18% of the area of the second substrate 520. For example, if the area of the second substrate 520 is the width W ₁ times the length L ₁ , the area of the second substrate 520 (for example, the width W ₁ times the length L ₁ ) ] Is about 1:20 to about 9:50. Additionally, in some embodiments, the limiting distance D ₁ is greater than about 420 탆.

Using these guidelines (the ratio of the KOR 524 to the area of the second substrate 520 and the minimum size of the limiting distance), the underfill material is substantially free of voids and can cover the exposed traces in the KOR 524 It has been found that a sufficient distance is provided between the edges of the protective layer 406 and the second substrate 520 to allow the underfill material to be applied. As described above, having a smaller distance may result in poor filling capability between the first substrate 402 and the second substrate 520, thereby creating voids, and having a larger distance may result in a KOR 524 Lt; RTI ID = 0.0 > trace. ≪ / RTI > Maintaining the limiting distance and KOR 524 as described above solves these problems to prevent or reduce the generation of voids between the first substrate 402 and the second substrate 520 and to reduce the exposure within the KOR 524 Lt; RTI ID = 0.0 > trace. ≪ / RTI >

Figures 6A and 6B illustrate a first substrate 402 and a second substrate 520 after interposing the underfill 650 therebetween, according to some embodiments. In some embodiments, the underfill 650 includes a polymer, a thermosetting epoxy, or the like, distributed within the gap between the second substrate 520 and the protective layer 406, e.g., KOR 524. For example, in some embodiments, the underfill material is a polymeric compound having a silicon dioxide filler material. The beads of the underfill 650 may be applied along one edge of the chip where the underfill 650 is capillary action until the gap between the first substrate 402 and the second substrate 520 is fully filled And sucked down the chip.

Figure 7 is a flow chart illustrating a manufacturing process in accordance with some embodiments. The process begins at step 702 where the first substrate is provided such that the first substrate includes a die attach region, a confined region and a peripheral region, and the protective layer is disposed within a peripheral region such as that described above with reference to Figures 4A and 4B Protect the trace. In step 704, a second substrate is provided, and in step 706, a second substrate is attached to the first substrate as described above with reference to Figures 5A and 5B. The first substrate is attached to the second substrate in a manner to provide a KOR region and a limiting distance between the first substrate and the nearest edge of the protective layer. In step 708, the underfill is disposed between the first substrate and the second substrate. Maintaining the KOR and the limiting distance as described above allows the underfill to be deployed with little or no voids while providing protection to the traces in the KOR.

In an embodiment, a device is provided. The device includes a first substrate on which a trace is formed. The first substrate has a die attach region, a confined region around the perimeter of the die attach region, and a perimeter region around the perimeter of the confined region. The first substrate further comprises a protective layer overlying the trace in the peripheral region. The second substrate is electrically coupled to the first substrate in the die attach region, the underfill is interposed between the first substrate and the second substrate, the underfill extends over the trace located within the confinement region, About 5% to about 18% of the area of the substrate.

In another embodiment, a device is provided. The device includes a first substrate having a die attach region, a peripheral region, and a confining region interposed between the die attach region and the peripheral region, wherein the protective layer covers the trace in the peripheral region, Lt; / RTI > The second substrate is electrically coupled to the first substrate such that the second substrate is positioned over the die attach region of the first substrate. The die attach region corresponds to a region of the first substrate directly below the second substrate and the confinement region extends from the boundary of the protective layer to the boundary of the die attach region. The area of the confinement region is from about 5% to about 18% of the area of the second substrate.

In yet another embodiment, a method of forming a semiconductor device is provided. The method includes providing a first substrate on which a trace is formed, and forming a protective layer over the portion of the first substrate. A second substrate is attached to the first substrate. The confinement region extends between the boundary of the protective layer and the periphery of the second substrate and the area of the confinement region is between about 5% and about 18% of the area of the second substrate.

The foregoing has outlined the features of the several embodiments in order that those skilled in the art may better understand aspects of the invention. It should be understood by those skilled in the art that the present invention may be used immediately as a basis for designing or modifying other processes and structures to accomplish the same purpose of the embodiments disclosed herein and / or to achieve the same advantages . It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention and that they may make various changes, substitutions and modifications of the present specification without departing from the spirit and scope of the present invention.

201: chip 202: Cu pillar bump (post)
203: solder bump 204: trace
205: encapsulated body 206: substrate
207: ball 210: solder mask trench
211: solder mask layer 301: region
311: Solder mask trench 402: First substrate
404: trace 406: protective layer

Claims (10)

In a device,
A first substrate on which a trace is formed, the first substrate having a die attach region, a keep-out region around the periphery of the die attach region, Wherein the first substrate has a protective layer overlying a trace in the peripheral region;
A second substrate electrically coupled to the first substrate in the die attach region; And
And an underfill interposed between the first substrate and the second substrate, the underfill extending over a trace located within the confinement region,
/ RTI >
Wherein the area of the confinement region is 5% to 18% of the area of the second substrate. 2. The device of claim 1, wherein the second substrate comprises an integrated circuit die. 2. The device of claim 1, wherein the limiting distance between the edge of the second substrate and the nearest edge of the protective layer is 420 [mu] m or more. 2. The device of claim 1, wherein the underfill comprises a polymeric compound having a silicon dioxide filler material. 2. The device of claim 1, wherein the underfill completely covers the traces within the confinement region and the die attach region. 2. The device of claim 1, wherein the second substrate is attached to the first substrate using a bump-on-trace connection. 2. The device of claim 1, wherein the second substrate comprises a copper pillar directly bonded to the first trace on the first substrate using a solder material. A first substrate having a die attach region, a peripheral region, and a confining region interposed between the die attach region and the peripheral region, wherein a protective layer covers a trace in the peripheral region, The first substrate does not extend into the confinement region; And
A second substrate electrically coupled to the first substrate, wherein the second substrate is positioned above a die attach region of the first substrate;
/ RTI >
Wherein the die attach region corresponds to a region of the first substrate immediately below the second substrate,
The limiting region extending from a boundary of the protective layer to a boundary of the die attach region,
Wherein the area of the confinement region is 5% to 18% of the area of the second substrate. 9. The device of claim 8, further comprising an underfill interposed between the first substrate and the second substrate. A method of forming a semiconductor device,
Providing a first substrate on which a trace is formed;
Forming a protective layer over the portion of the first substrate; And
Attaching a second substrate to the first substrate
Lt; / RTI >
Wherein a confinement region extends between a boundary of the passivation layer and a periphery of the second substrate and the area of the confinement region is between 5% and 18% of the area of the second substrate.

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