CN105762087A - Method And Device Used For Packaging Boss Chip On Trace - Google Patents

Method And Device Used For Packaging Boss Chip On Trace Download PDF

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Publication number
CN105762087A
CN105762087A CN 201410800491 CN201410800491A CN105762087A CN 105762087 A CN105762087 A CN 105762087A CN 201410800491 CN201410800491 CN 201410800491 CN 201410800491 A CN201410800491 A CN 201410800491A CN 105762087 A CN105762087 A CN 105762087A
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Prior art keywords
substrate
region
protective
layer
keep
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CN 201410800491
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Chinese (zh)
Inventor
林彦良
黄昶嘉
郭庭豪
吴胜郁
陈承先
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台湾积体电路制造股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Abstract

Methods and apparatuses for attaching a first substrate to a second substrate are provided. In some embodiments, the first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill.

Description

用于迹线上凸块芯片封装的方法和装置 A method and apparatus for bump on trace chip package

[0001] 优先权声明和交叉引用 [0001] CROSS-REFERENCE TO PRIORITY CLAIM and

[0002] 本申请是2012年4月18日提交的标题为“提交的标题为芯片封装的方法和装置集成电路管芯。填充材料的高分子化合物。面积介于所Chip Packaging”的专利申请第13/450,191号的部分继续申请,其全部内容结合于此作为参考。 [0002] The present application is a title on April 18, 2012 entitled "filed title chip packaging method and apparatus for an integrated circuit die. The polymer compound filler. The area between Chip Packaging" Patent Application No. No. 13 / 450,191 continuation in part application, which is incorporated herein by reference.

技术领域 FIELD

[0003] 本发明涉及集成电路器件,更具体地,涉及用于迹线上凸块芯片封装的方法和装置。 [0003] The present invention relates to integrated circuit devices, and more particularly, relates to a method and apparatus for trace bumps of the chip package.

背景技术 Background technique

[0004] 集成电路或芯片由成千上万的有源和无源器件(诸如晶体管和电容器)组成。 [0004] or an integrated circuit chip made up of thousands of active and passive devices (such as transistors and capacitors) components. 这些器件最初彼此隔离,之后互连这些器件以形成集成电路。 These devices are initially isolated from each other, then these devices interconnected to form integrated circuits. 进一步形成连接件结构以用于集成电路,连接件结构可以包括在电路的表面上形成的接合焊盘或金属凸块。 Connecting member is further formed structure for an integrated circuit, the connector structure may comprise a metal bond pads or bumps formed on the surface of the circuit. 通过接合焊盘或金属凸块制成电连接件以将芯片连接至封装衬底或另一管芯。 Connector or by bonding pad is made of metal bumps to electrically connect the chip to a package substrate or other die. 通常地,可以使用引线接合(WB)或倒装芯片(FC)封装技术将芯片组装至诸如引脚网格阵列(PGA)或球栅阵列(BGA)的封装件内。 Typically, wire bonding may be used (WB) or a flip-chip (FC) package into the chip assembly technique such as a pin grid array (PGA) or ball grid array (BGA) package.

[0005] 倒装芯片(FC)封装技术可以使用迹线上凸块(BOT)结构将芯片连接至封装衬底,其中,通过金属凸块制成连接件以将芯片连接至封装衬底或管芯的金属迹线。 [0005] The flip-chip (FC) package technology can bump on trace (BOT) structure connecting the chip to a package substrate, wherein the metal bumps are made by connecting member to connect the chip to a package substrate or tube trace metal core. BOT结构为微电子封装工业提供低成本替代。 BOT structure is a microelectronic package industry to provide a low cost alternative. 然而,随着衬底结构越来越薄,BOT结构出现可靠性问题。 However, as more and more thin substrate structure, reliability problems arise BOT structure.

[0006] 当使用BOT结构时,通过回流工艺将用于芯片的凸块焊接在封装衬底上的迹线上。 [0006] When a BOT structure, by a reflow process for soldering the bumps of the chip traces on the package substrate. 当凸块连接至衬底并且通过回流条件冷却至室温时,由热膨胀系数(CTE)失配引起的热力驱使衬底缩小并且导致每个凸块的相对扭曲。 When the bumps connected to the substrate and cooled to room temperature through reflux conditions, the coefficient of thermal expansion (CTE) mismatch caused by thermal reduction and results in driving the substrate relative twisting of each of the bumps. 一旦应力水平升至超过衬底和迹线之间的粘合标准,就会发生迹线剥离故障。 Once the stress level rises above standard adhesion between the substrate and the traces, the traces separation failure occurs.

发明内容 SUMMARY

[0007] 为了解决现有技术中存在的问题,本发明提供了一种器件,包括:第一衬底,具有在所述第一衬底上形成的迹线,所述第一衬底具有管芯附接区、围绕所述管芯附接区的外围的遮挡区以及围绕所述遮挡区的外围的外围区,所述第一衬底具有位于所述外围区中的覆盖所述迹线的保护层;第二衬底,电连接至所述管芯附接区中的所述第一衬底;以及底部填充物,介于所述第一衬底和所述第二衬底之间,所述底部填充物延伸在位于所述遮挡区中的所述迹线上方;其中,所述遮挡区的面积介于所述第二衬底的面积的约5%和约18%之间。 [0007] In order to solve the problems in the prior art, the present invention provides a device, comprising: a first substrate having a trace formed on said first substrate, said substrate having a first tube die attach region, said die attach around the periphery of the contact area and the shielding area surrounding the peripheral area of ​​the peripheral region of the shield, the first substrate having a covering located in the peripheral region of the traces the protective layer; a second substrate, electrically connected to the die attach region of the first substrate; and an underfill material, interposed between the first substrate and the second substrate, the underfill is located in the shielding region extends in the trace direction; wherein the area of ​​the occlusion region between said second substrate area between about 5% and about 18%.

[0008] 在上述器件中,其中,所述第二衬底包括集成电路管芯。 [0008] In the above device, wherein said second substrate comprises an integrated circuit die.

[0009] 在上述器件中,其中,所述第二衬底的边缘和所述保护层的最接近的边缘之间的遮挡距离等于或大于约420 μ m。 [0009] In the above device, wherein the distance between the shielding edge of the second substrate and the closest edge of the protective layer is equal to or greater than about 420 μ m.

[0010] 在上述器件中,其中,所述底部填充物包括具有二氧化硅填充材料的高分子化合物。 [0010] In the above device, wherein the base filler comprises a silica filler having a polymer compound.

[0011] 在上述器件中,其中,所述底部填充物完全覆盖位于所述遮挡区和所述管芯附接区中的所述迹线。 [0011] In the above device, wherein said filler completely covers the bottom portion of the shielding region and located in the die attach region traces.

[0012] 在上述器件中,其中,所述第二衬底使用迹线上凸块连接件附接至所述第一衬底。 [0012] In the above device, wherein said second substrate trace using a bump connecting member attached to the first substrate.

[0013] 在上述器件中,其中,所述第二衬底包括使用焊料材料直接连接至所述第一衬底上的第一迹线的铜柱。 [0013] In the above device, wherein said second substrate comprises a copper post is directly connected to the first trace on said first substrate using a solder material.

[0014] 根据本发明的另一方面,提供了一种器件,包括:第一衬底,具有管芯附接区、外围区以及介于所述管芯附接区和所述外围区之间的遮挡区,其中,保护层覆盖所述外围区中的迹线,并且其中,所述保护层不延伸到所述管芯附接区和所述遮挡区内;以及第二衬底,电连接至所述第一衬底,所述第二衬底位于所述第一衬底的所述管芯附接区上方;其中,所述管芯附接区对应于所述第一衬底的直接位于所述第二衬底下方的区域;其中,所述遮挡区从所述保护层的边界延伸至所述管芯附接区的边界;其中,所述遮挡区的面积介于所述第二衬底的面积的约5%和约18%之间。 [0014] According to another aspect of the present invention, there is provided a device, comprising: a first substrate having a die attach region and a peripheral region interposed between said die attach region and said peripheral region the occlusion zone, wherein the protective layer covering the peripheral region of the traces, and wherein the protective layer does not extend to the die attach region and the shielding region; a second substrate and electrically connected to the first substrate, the second substrate located above the die attach region of the first substrate; wherein the die attach region of the first substrate corresponding to the direct a second substrate located in the region below; wherein said shielding region extends from the boundary of the protective layer to the boundary of the die attach region; wherein the occlusion region between said second area between about 5% and about 18% of the area of ​​the substrate.

[0015] 在上述器件中,其中,所述器件还包括介于所述第一衬底和所述第二衬底之间的底部填充物。 [0015] In the above device, wherein said device further comprises an underfill interposed between the first substrate and the second substrate.

[0016] 在上述器件中,其中,所述器件还包括介于所述第一衬底和所述第二衬底之间的底部填充物,其中,所述底部填充物完全覆盖所述遮挡区中的所述迹线。 [0016] In the above device, wherein said device further comprises a filler interposed between the bottom of the first substrate and the second substrate, wherein the underfill completely covered the occlusion zone in the traces.

[0017] 在上述器件中,其中,所述器件还包括介于所述第一衬底和所述第二衬底之间的底部填充物,其中,所述底部填充物包括具有二氧化硅填充材料的高分子化合物。 [0017] In the above device, wherein said device further comprises a filler interposed between the bottom of the first substrate and the second substrate, wherein the underfill composition comprises a silica filler having molecular compound materials.

[0018] 在上述器件中,其中,所述第二衬底包括集成电路管芯。 [0018] In the above device, wherein said second substrate comprises an integrated circuit die.

[0019] 在上述器件中,其中,所述第二衬底的边缘和所述保护层的最接近的边缘之间的遮挡距离等于或大于约420 μ m。 [0019] In the above device, wherein the distance between the shielding edge of the second substrate and the closest edge of the protective layer is equal to or greater than about 420 μ m.

[0020] 在上述器件中,其中,所述第二衬底使用迹线上凸块连接件附接至所述第一衬底。 [0020] In the above device, wherein said second substrate trace using a bump connecting member attached to the first substrate.

[0021] 根据本发明的又一方面,提供了一种形成半导体器件的方法,所述方法包括:提供第一衬底,所述第一衬底具有在所述第一衬底上形成的迹线;在所述第一衬底的部分上方形成保护层;以及将第二衬底附接至所述第一衬底;其中,遮挡区延伸在所述保护层的边界和所述第二衬底的外围之间,所述遮挡区的面积介于所述第二衬底的面积的约5%和约18%之间。 [0021] According to another aspect of the present invention, there is provided a method of forming a semiconductor device, the method comprising: providing a first substrate, the first substrate having a trace formed on said first substrate line; formed over portions of the protective layer of the first substrate; and a second substrate attached to the first substrate; wherein the shielding region extends at the boundary of the protective layer and the second substrate between the peripheral end, the area between the shielding region of the second substrate area between about 5% and about 18%.

[0022] 在上述方法中,其中,所述方法还包括将底部填充物布置在所述第一衬底和所述第二衬底之间。 [0022] In the above process, wherein said method further comprises the underfill disposed between the first substrate and the second substrate.

[0023] 在上述方法中,其中,所述方法还包括将底部填充物布置在所述第一衬底和所述第二衬底之间,其中,所述底部填充物完全覆盖所述遮挡区中的所述迹线。 [0023] In the above process, wherein said method further comprises the underfill disposed between the first substrate and the second substrate, wherein the underfill completely covered the occlusion zone in the traces.

[0024] 在上述方法中,其中,所述方法还包括将底部填充物布置在所述第一衬底和所述第二衬底之间,其中,所述底部填充物包括具有二氧化硅填充材料的高分子化合物。 [0024] In the above process, wherein said method further comprises the underfill disposed between the first substrate and the second substrate, wherein the underfill composition comprises a silica filler having molecular compound materials.

[0025] 在上述方法中,其中,所述第二衬底包括集成电路管芯。 [0025] In the above process, wherein said second substrate comprises an integrated circuit die.

[0026] 在上述方法中,其中,所述第二衬底的边缘和所述保护层的最接近的边缘之间的遮挡距离等于或大于约420 μ m。 [0026] In the above method, wherein the distance between the shielding edge of the second substrate and the closest edge of the protective layer is equal to or greater than about 420 μ m.

附图说明 BRIEF DESCRIPTION

[0027] 当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。 [0027] when read in conjunction with the drawings, from the following detailed description may best be understood that various aspects of the present invention. 应该注意,根据工业中的标准实践,各个部件未按比例绘制。 It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. 实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。 Indeed, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0028] 图1示出了迹线上凸块(BOT)结构上的芯片以形成倒装芯片(FC)封装件的实施例; [0028] FIG 1 shows a bump on trace (BOT) chip on the structure to form a flip-chip Example (FC) package;

[0029] 图2(a)至图2(c)示出了在BOT结构中所使用的焊料掩模沟槽的方法和装置以形成FC封装件的实施例;以及 [0029] FIG. 2 (a) to 2 (c) shows a method and apparatus in a solder mask trench BOT structures used to form Example FC package; and

[0030] 图3示出了连接至在BOT结构中所使用的多个焊料掩模沟槽环内的迹线的多个凸块的顶视图。 [0030] FIG. 3 shows a top view of a plurality of bumps connected to a plurality of solder mask trench traces within the ring structure BOT used.

[0031] 图4A至图6B示出了根据一些实施例的中间工艺步骤的各个平面图和截面图。 [0031] FIGS. 4A through 6B illustrate various plan and sectional views of intermediate steps of the process in accordance with some embodiments.

[0032] 图7是根据一些实施例的示出制造的方法的流程图。 [0032] FIG. 7 is a flowchart of a method according to some embodiments shown fabricated.

具体实施方式 detailed description

[0033] 以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。 [0033] The following disclosure provides many different embodiments or examples of the subject matter provided for implementing different features. 下面描述了组件和布置的具体实例以简化本发明。 Specific examples are described below to simplify the assembly and arrangement of the present invention. 当然,这些仅仅是实例,而不旨在限制本发明。 Of course, these are merely examples and are not intended to limit the present invention. 例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。 For example, in the following description or embodiment of the first formed member and the second member may comprise a first member in direct contact formed over the second member, and may also include a first member and a second member of the It may be formed between the additional member, so that the first member and the second member may not be in direct contact embodiment. 此外,本发明可在各个实例中重复参考标号和/或字符。 Further, the present disclosure may repeat reference numerals and / or letters in the various examples. 该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。 This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the embodiments and / or configurations discussed in the various embodiments.

[0034] 而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。 [0034] Further, for convenience of description, may be used herein "lower in ..." such as, "... in the below", "lower", "over ...", "upper" and the like terms to describe shown in FIG. the relationship of one element or the other member (or other) elements or components. 除了图中所示的方位之外,空间相对术语旨在包括器件在使用或操作中的不同方位。 In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. 装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。 Device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be made in the same manner be construed accordingly.

[0035] 如将在下面说明的,公开了用于BOT结构中所使用的焊料掩模沟槽的方法和装置以形成半导体封装件。 [0035] As will be described below, discloses a method and apparatus for solder mask trench BOT structure used to form a semiconductor package. 在迹线和衬底上形成焊料掩模层。 A solder mask layer is formed on the traces and substrate. 形成称为焊料掩模沟槽的焊料掩模层的开口,以暴露衬底上的迹线。 An opening formed in a solder mask trench called a solder mask layer to expose the traces on the substrate. 将芯片连接至暴露于焊料掩模沟槽中的迹线。 Chip connected to the solder mask is exposed to trace trenches. 由于焊料掩模沟槽的形成,暴露于沟槽中的迹线可以具有更好的抓取力,这减少了半导体封装件的迹线剥离故障。 Since the solder mask is formed trench, the trench is exposed to the traces may have a better gripping force, which reduces the traces of peeling the semiconductor package failure.

[0036] 图1是迹线上凸块(BOT)结构上的芯片201以形成倒装芯片(FC)封装件的说明性实施例的不意图。 [0036] FIG. 1 is a bump on trace (BOT) 201 on the chip to form the illustrative structure of a flip chip (FC) package is not intended embodiment. 衬底206可以具有多个子层。 Substrate 206 may have a plurality of sub-layers. 图1中不出的衬底206的两个子层仅是为了说明的目的,而不在于限制。 Two sub-layers of the substrate 206 of FIG. 1 is not merely for purposes of illustration and are not limiting. 位于衬底206下方的多个球207可以形成球栅阵列(BGA)。 Substrate 206 located below the ball 207 may be formed of a plurality of ball grid array (BGA). 芯片201通过多个互连件连接至衬底206,其中,每个互连件均包括Cu柱凸块或接线柱202以及焊料凸块203。 Chip 201 is connected to the substrate 206 through a plurality of interconnects, wherein each interconnect comprises Cu pillar bump or solder bump terminals 202 and 203. 焊料凸块203布置在迹线204上,迹线204形成在衬底206上。 Solder bumps 203 disposed on trace 204, trace 204 is formed on the substrate 206. 在衬底206的表面上形成覆盖迹线的焊料掩模211。 Covering the solder traces formed on a surface of the mask substrate 206 211. 形成焊料掩模的开口,称为焊料掩模沟槽,该开口暴露迹线204。 An opening formed in the solder mask, solder mask called a trench, exposing traces 204 of the opening. 可以用化合物填充芯片201和衬底206之间的间隔,从而形成包封体205。 It can be used to fill the space between the chip 201 and the substrate 206 compound thereby forming enclosure 205.

[0037] 图2 (a)示出了衬底206上的单个焊料掩模沟槽210的实施例,焊料掩模沟槽210可以是图1中的任何沟槽,其中,迹线暴露于焊料掩模沟槽210,并且焊料掩模沟槽210构成至芯片201的连接。 [0037] FIG. 2 (a) shows a single trench solder mask 206 on the substrate 210 of the embodiment, solder mask 210 may be any of the trenches in the trench 1, wherein the exposure to solder traces trench mask 210, and the solder mask trench configuration 210 is connected to the chip 201. 在衬底206的表面上形成迹线204。 It is formed on the substrate 206 surface trace 204. 可以在迹线上和衬底206的表面上形成覆盖迹线的焊料掩模层211。 May be formed to cover traces solder mask layer 211 and traces on the surface of the substrate 206. 可以在焊料掩模层211中开启沟槽以形成焊料掩模沟槽210,从而暴露迹线204。 It can open trench in the solder mask layer 211 in trench 210 to form a solder mask, to expose the trace 204. 沟槽具有足够大的开口,从而使得诸如焊料球203的互连件可以直接定位在开口中包含的迹线上。 A trench having an opening large enough so that interconnects such as solder balls 203 may be positioned directly trace contained in the opening. 例如,焊料掩模沟槽的尺寸为约焊料凸块的直径。 For example, solder mask size of a diameter of about trench solder bump. 迹线204可以通过互连件连接至芯片201。 Trace 204 may be connected to the chip 201 by an interconnecting member. 互连件可以包括焊料凸块203和诸如Cu柱的接线柱202,其中,焊料球203直接布置在迹线204上并且由焊料掩模沟槽围绕。 Interconnect member 203 may include solder bumps such as stud 202 Cu and columns, wherein a solder ball 203 is disposed directly on the trace 204 by a solder mask and surrounds the trench. 图2 (a)中示出的结构仅用于说明的目的,而不在于限制。 FIG 2 (a) in the structure shown for illustrative purposes only, and not limiting. 可以设想到额外的实施例。 It is contemplated that additional embodiments.

[0038] 图2(b)示出了顶视图,其中,接线柱202位于迹线204上,迹线204由焊料掩模211围绕。 [0038] FIG. 2 (b) shows a top view, wherein the terminal 202 is located on trace 204, trace 204 is surrounded by a solder mask 211. 图2(b)中未示出芯片201和衬底206。 FIG 2 (b) are not shown chip 201 and the substrate 206.

[0039] 图2(c)示出了制造图2(a)中示出的实施例的示例性工艺。 [0039] FIG. 2 (c) shows a fabrication FIG 2 (a) in the exemplary process illustrated embodiment. 下面解释了图2(c)中示出的工艺的细节。 The following explains the details of (c) in the process shown in FIG.

[0040] 工艺开始于步骤220,其中,提供诸如图2 (a)中的衬底206的衬底。 [0040] The process begins at step 220, where a substrate, such as in FIG. 2 (a) of the substrate 206. 衬底206可以为封装件提供机械支撑和接口,该接口允许外部组件访问封装件内的器件。 The substrate 206 may provide mechanical support for the package and the interface, this interface allows external access to the device components within the package member. 衬底206可以包括掺杂或未掺杂的块状硅、或绝缘体上硅(SOI)衬底的有源层。 Substrate 206 may comprise a doped or undoped bulk silicon or silicon on insulator (SOI) active layer of the substrate. 其他衬底可以包括多层衬底、梯度衬底或混合取向衬底。 Other substrate may include a multilayer substrate, the substrate or hybrid orientation substrates gradient. 衬底206还可以是形成为聚合物材料(诸如双马来酰亚胺三嗪等)的多个薄层的堆叠件的层压衬底。 Substrate 206 may also be formed as a polymeric material (such as a bismaleimide triazine) laminate substrate a plurality of thin layers of the stack.

[0041] 迹线204可以位于衬底206的表面上。 [0041] The trace 204 may be located on a surface of the substrate 206. 迹线204可以用于扩展管芯的覆盖区。 Trace 204 may be used to extend the coverage area of ​​the die. 迹线的宽度或直径可以与球(或凸块)直径大约相同,或可以几乎比球(或凸块)直径窄2至4倍。 Trace width or diameter may be about the same as the balls (or bumps) in diameter, or may almost than balls (or bumps) is narrower diameter 2 to 4 times. 例如,迹线204可以具有介于约10 μ m和40 μ m之间的线宽度以及介于约30 μ m和70μπι之间的迹线节距P。 For example, trace 204 may have a line width of between about 10 μ m and 40 μ m and between about 30 μ m and a pitch between the trace 70μπι P. 迹线可以具有窄、宽或锥形的形状。 Traces may have the shape of a narrow, wide or tapered. 迹线的端子的形状可以与迹线的主体的形状不同。 Shape of the terminal traces the shape of the body may be different from the traces. 迹线主体可以具有基本上恒定的厚度。 Traces body may have a substantially constant thickness. 迹线的端子和迹线的主体形成为一个整体,这不同于将焊盘布置在迹线上。 The terminal body and traces traces are formed as a whole, which is different from the bonding pad is arranged on the trace. 迹线可以具有基本上长于球(或凸块)直径的长度。 Trace may have a length substantially longer than the diameter of the balls (or bumps). 另一方面,连接焊盘可以具有与球或凸块直径类似的长度或宽度。 On the other hand, connection pads may have similar or the ball bump diameter length or width.

[0042] 在衬底上可以存在多条迹线,每条迹线彼此电绝缘,并且两条邻近的迹线之间的间隔可以介于约10 μπι和40 μπι之间。 [0042] The substrate may be present on a plurality of traces, each trace electrically insulated from each other, and the spacing between two adjacent traces may be between about 10 μπι and 40 μπι.

[0043] 作为实例,迹线204可以包括诸如Al、Cu、Au、它们的合金的导电材料、其他材料或它们的组合和/或多层。 [0043] As an example, trace 204 may include information such as Al, Cu, Au, alloys thereof electrically conductive material, other materials or combinations thereof and / or a multilayer. 可选地,迹线204可以包括其他材料。 Alternatively, trace 204 may comprise other materials. 在一些实施例中,介电层可以覆盖迹线204的一些部分。 In some embodiments, the dielectric layer may cover portions of the trace 204. 迹线204可以由涂布在迹线204上的金属饰面覆盖,诸如有机薄膜或混合材料(诸如Ni/Pd/Au)的层。 Trace 204 may be formed in trace metal finish coating on the cover 204, such as an organic thin film layer or a mixed material (such as a Ni / Pd / Au) is.

[0044] 迹线204和衬底仅通过它们之间的界面粘附连接,界面粘附可能不是足以构成迹线204和衬底206之间的强连接的抓取力。 [0044] The trace 204 and the substrate only by adhesion interface connected therebetween, the interfacial adhesion may not be sufficient to constitute a strong gripping force between the traces 204 and the substrate 206 is connected.

[0045] 在步骤221中,在衬底206的表面上可以形成诸如图2 (a)中示出的焊料掩模层211的焊料掩模层,焊料掩模层覆盖迹线204以及衬底的表面。 [0045] In step 221, on the surface of the substrate 206 may be formed as in FIG. 2 (a) shows a solder mask layer of solder mask layer 211, a solder mask layer 204 and the substrate trace surface. 焊料掩模层211可以执行若干功能,包括提供衬底上的电路迹线之间的电绝缘电阻、抗化学和抗腐蚀或保护、机械(划痕、磨损)保护、焊料表面上的边界、迹线上的额外的抓取力、以及改进的介电可靠性。 The solder mask layer 211 may perform several functions, including providing an electrical insulation resistance between the circuit traces on the substrate, and corrosion or chemical protection, mechanical (scratching, wear) protection, on the boundary surface of the solder, trace additional lines of gripping force, and improved dielectric reliability. 因为焊料掩模、迹线和衬底形成夹层结构,其中,焊料掩模和衬底“夹住”迹线,所以焊料掩模层提供迹线204和衬底206之间的额外的抓取力。 Because the solder mask, the traces and the substrate form a sandwich structure, wherein the solder mask and the substrate "sandwich" trace, the solder mask layer to provide additional gripping force between the substrate 206 and the traces 204 .

[0046] 通过将湿薄膜封闭(screening)在衬底表面上,然后通过烤箱固化湿薄膜,可以在单个步骤中形成焊料掩模层211。 [0046], and then the wet film through oven curing, solder mask layer 211 may be formed in a single step by a wet film blocking (Screening) on ​​the substrate surface. 焊料掩模层211的厚度可以为约30微米至40微米(通常为约35微米)。 The thickness of the solder mask layer 211 may be from about 30 to 40 microns (typically about 35 microns). 焊料掩模层可以包括聚合物材料。 The solder mask layer may comprise a polymeric material.

[0047] 在步骤223中,如图2(a)所示,可以在焊料掩模层211中开启沟槽以形成焊料掩模沟槽210,从而暴露迹线204。 [0047] In step 223, FIG. 2 (a), the trench can be opened in solder mask layer 211 in the trench 210 to form a solder mask, to expose the trace 204. 沟槽具有足够大的开口,从而使得诸如焊料球203的互连件可以直接接合在开口中包含的迹线上。 A trench having an opening large enough so that interconnects such as solder ball 203 may be directly bonded trace contained in the opening. 容纳焊料球的较宽开口可以增大焊料球和迹线之间的连接强度。 Receiving a wider opening of the solder balls may increase the connection strength between the solder balls and traces. 因此开口的尺寸是灵活的并且可以随着用于连接至迹线的焊料球的尺寸而改变。 Thus the size of the opening is flexible and can be used as the size of the traces connected to the solder balls is changed. 由湿薄膜形成的焊料掩模层211可以封闭成一图案以形成焊料掩模沟槽210。 A solder mask layer 211 is formed by a wet film may be closed into a solder mask pattern to form a trench 210. 例如,具有焊料掩模沟槽的焊料掩模层可以首先布置在辊上以印刷到衬底上。 For example, a solder mask layer has a first solder mask trench may be arranged on the printing roller onto the substrate. 可选地,光敏材料可以用于将焊料掩模沟槽210图案化为固化薄膜。 Alternatively, the photosensitive material may be used to solder mask 210 is patterned into trenches cured film. 可以形成焊料掩模沟槽210以暴露迹线204,从而进一步形成与将安装在衬底上的管芯的适当的电连接。 Solder mask trench 210 may be formed to expose the trace 204, thereby further forming the mounted die suitable electrical connector on a substrate.

[0048] 助焊剂(未示出)可以施加到迹线。 [0048] Flux (not shown) may be applied to the traces. 助焊剂主要用于帮助焊料的流动,从而使得焊料球203与衬底上的迹线接触良好。 Flux primarily to help the flow of the solder so that the solder balls 203 good contact with the traces on the substrate. 可以以包括刷涂或喷涂的各种方法的任何方法施加助焊剂。 Flux may be applied by any conventional method including brushing or spraying various methods. 助焊剂通常具有酸性成分以及附着性,酸性成分从焊料表面去除氧化物阻挡件,而附着性有助于防止芯片在组装工艺期间移动到衬底表面上。 Flux normally has an acidic component and the adhesion, the blocking member acidic component is removed from the solder surface oxides, and helps prevent adhesion of the chip to move on the substrate surface during the assembly process.

[0049] 在步骤227中,如图2(a)所示,可以通过芯片的互连件将芯片201连接至迹线204。 [0049] In step 227, FIG. 2 (a), the chip 201 may be connected to trace 204 through interconnect chips. 如图2 (a)所示,互连件可以包括焊料凸块203和诸如Cu柱的接线柱202。 As shown in FIG 2 (a), the interconnection member may include solder bumps 203 and the terminals 202 column such as Cu. 沟槽具有足够大的开口,从而使得焊料球203可以直接接合在开口中包含的迹线上。 A trench having an opening large enough so that the solder balls 203 may be directly bonded trace contained in the opening.

[0050] 可以将芯片201的焊料凸块203布置在通过焊料掩模沟槽暴露的迹线204上。 [0050] The chip 201 may be on the solder bump 203 by trace 204 disposed in a trench exposing the solder mask. 焊料凸块203可以包括诸如锡的材料、或者诸如银、无铅锡、铜、它们的组合等的其他合适的材料。 Solder bumps 203 may comprise a material such as tin, or other suitable materials such as silver, lead-free solder, copper, a combination thereof or the like. 在焊料凸块203是锡焊料凸块的实施例中,焊料凸块203可以通过以下步骤形成:首先通过诸如蒸发、电镀、印刷、焊料转印或植球的方法形成一定厚度(例如,约15 μm)的锡层,然后实施回流以将材料成形为期望的凸块形状。 In the solder bump 203 is an example of tin solder bumps, the solder bumps 203 may be formed by the following steps: firstly, such as by evaporation, electroplating, printing, solder bumping, or transfer a certain thickness (e.g., about 15 [mu] m) layer of tin and reflow the bump shape to be formed into a desired material. 可以可选地利用生产焊料凸块203的任何合适的方法。 Any suitable method for producing a solder bump 203 may alternatively be utilized.

[0051] 可以通过焊料凸块203和接线柱202将诸如图2(a)中示出的芯片201的芯片连接至迹线204。 [0051] The solder bumps 203 may be terminal 202 and the trace 204 is connected to the chip by FIG. 2 (a), the chip 201 as shown. 接线柱202可以形成在芯片201上。 Terminal 202 may be formed on the chip 201. 接线柱202可以是Cu柱或具有高于300有的熔点的其他金属。 Cu pillar post 202 may be greater than 300, or some other metals having a melting point. 芯片201可以对准,从而使得接线柱202布置到焊料凸块203上。 Chip 201 may be aligned such that the terminals 202 disposed on the solder bump 203. 芯片可以是存储芯片或任何其他功能芯片。 Chip may be a memory chip or any other chip functions.

[0052] 接线柱202和焊料凸块203 —起形成芯片的互连件。 [0052] The terminal 202 and the solder bump 203-- formed from the interconnect chip. 接线柱202和焊料凸块203可以形成为多种合适的形状以避开附近的组件、控制芯片201和迹线204之间的连接区或其他合适的理由。 Posts 202 and solder bumps 203 may be formed in a variety of suitable shape to avoid the vicinity of the assembly, or other suitable connecting region between grounds 201 and trace 204 chip control. 互连件的形状可以为圆形、八边形、矩形、细长六边形(在细长六边形的相对两端具有两个梯形)、椭圆形、棱形。 Interconnects shape may be circular, octagonal, rectangular, elongated hexagon (trapezoidal having two opposite ends of the elongated hexagon), oval, prismatic.

[0053] 在步骤231中,实施回流工艺。 [0053] In step 231, a reflow process. 在将芯片201接合至如图2(a)所示的迹线之后,可以向芯片201和衬底206施加热量,使焊料球203回流并且在芯片201和衬底206之间形成电连接件。 After bonding to FIG. 2 (a) trace shown in the chip 201 may be applying heat to the chip 206 and the substrate 201, the solder balls 203 and reflux electrical connection between the chip 201 and the substrate 206. 对于一个实施例,热量可以达到约220 —的温度。 For one embodiment, heat may reach about 220 - Temperature of.

[0054] 在步骤233中,可以将底部填充材料(通常为热固性环氧树脂)分配到芯片201和衬底206之间的间隙内。 [0054] In step 233, the underfill material may be (generally a thermosetting epoxy resin) dispensed into the gap between the chip 201 and the substrate 206. 可以沿着芯片的一个边缘施加热固性环氧树脂的小珠,其中,环氧树脂通过毛细作用被吸引到芯片下方,直到环氧树脂完全填充芯片和衬底之间的间隙。 Thermosetting epoxy resin may be applied along one edge of the chip beads, wherein the epoxy resin is attracted to the bottom of the chip by capillary action, until the epoxy resin completely fills the gap between the chip and the substrate. 底部填充材料均匀地分布在间隙中是重要的。 Underfill material uniformly distributed in the gap is important.

[0055] 环氧树脂的单独的小珠也可以分配并且接合在芯片201的外周周围。 [0055] Epoxy individual beads may also be distributed around the chip 201 and engages the outer periphery. 然后,通过将衬底和芯片加热至适当的固化温度来固化底部填充环氧树脂和外围接合环氧树脂,其形成诸如图1中示出的包封体205的包封体。 Then, the chip and the substrate by heating to a suitable curing temperature of the epoxy resin and cured underfill epoxy peripheral bond formed in FIG. 1, such as enclosure 205 shown in the enclosure. 包封体205已经填充了芯片201和衬底206之间的间隙。 Enclosure 205 has been filled with the gap between the chip 201 and the substrate 206. 以这种方式,当工艺结束时,该工艺产生机械接合以及电接合的半导体芯片组件。 In this manner, when the end of the process, the process produces a mechanical and electrical joining of a semiconductor chip bonded assembly.

[0056] 图3示出了由BOT结构形成的半导体封装件的衬底的顶视图。 [0056] FIG. 3 shows a top view of the substrate of a semiconductor package structure formed by the BOT. 除了区域301之外,衬底的表面可以由焊料掩模覆盖。 In addition to region 301, the surface of the substrate may be covered by a solder mask. 焊料掩模也可以以其他形状覆盖衬底的表面。 The solder mask may also cover the other surface of the substrate to form. 在焊料掩模层上可以形成有多个焊料掩模沟槽311。 On the solder mask layer may be formed with a plurality of grooves 311 a solder mask. 焊料掩模沟槽围绕衬底的中心区并且形成多个焊料掩模沟槽环。 Solder mask trench surrounding a central region of the substrate and forming a plurality of solder mask trench ring. 焊料掩模沟槽的形状与衬底上的迹线的轮廓一致。 Conform to a contour trace on the shape of the substrate solder mask trench. 可以存在其他形状,而不是形成的焊料掩模环。 There may be other shapes, rather than ring formed solder mask. 在图3中形成有三个这样的焊料掩模沟槽环。 FIG 3 is formed in three such solder mask trench ring. 可以形成有其他数量的焊料掩模沟槽环。 Other quantities may be formed of a solder mask trench ring. 诸如2021和2022的多个接线柱或互连件可以布置在暴露于焊料掩模沟槽内的迹线上。 And a plurality of terminals, such as 2021 or 2022 may be disposed interconnects exposure to the solder mask trench trace. 两个接线柱或两个互连件之间的节距可以小于约140 μπι。 The pitch between two terminals or two interconnects may be less than about 140 μπι.

[0057] 在其他实施例中,从管芯附接区(诸如管芯或其他衬底可以附接的区域)和遮挡区(例如,直接围绕管芯附接区的区域)去除焊料掩模。 [0057] In other embodiments, the die attach region (such as a die or other substrate may be attached region) and the occlusion zone (e.g., the region immediately surrounding the die attach region) removing the solder mask. 如下面更详细地解释的,将去除焊料掩模材料,从而使得将去除直接位于管芯下方的区域和直接围绕的区域。 As explained in more detail below, the removal of solder mask material is removed so that the die area and positioned directly surrounding the area immediately below. 去除了焊料掩模材料的区域的尺寸大于管芯的尺寸。 To the size of the size of the region of the solder mask material is greater than the addition of the die. 确定去除了焊料掩模材料的区域的尺寸,从而使得管芯的边缘和焊料掩模的边缘之间的横向区域允许底部填充材料以完全填充管芯和下面的衬底之间的区域的方式(没有留下暴露的迹线)施加。 In addition to determining the size of the region of the solder mask material, such that the lateral edges of the region between the solder mask and the die so as to allow the underfill material to completely fill the region between the die and the underlying substrate ( leaving no trace of exposure) is applied.

[0058] 例如,在管芯的边缘和焊料掩模的边缘之间的横向区域太小的一些情况下,底部填充材料可能不完全填充管芯和下面的衬底之间的区域,从而允许在管芯和下面的衬底之间形成一个或多个空隙。 For example, in the region between the lateral edges of the die and the solder mask is too small in some cases, may not completely fill the area between the die and the underlying substrate [0058] The underfill material, thereby allowing one or more voids are formed between the die and the underlying substrate. 在管芯的边缘和焊料掩模的边缘之间的横向区域太大的一些情况下,迹线可能仍暴露。 In the region between the lateral edges of the die and the solder mask is too large in some cases, the traces may remain exposed. 已经发现,通过控制管芯的边缘和焊料掩模的边缘之间的距离的宽度和/或控制管芯的边缘和焊料掩模的边缘之间的区域的面积与管芯的面积的比率,底部填充物可以完全填充管芯和下面的衬底之间的区域并且覆盖迹线,从而为管芯和下面的衬底之间的电连接件以及下面的衬底上的迹线提供保护。 It has been found, by the area ratio of the area of ​​the die area between edge width and / or solder mask edge and of the distance between the edges of the solder mask and controlling a control die die bottom the filler may completely fill the tube between the core region and the underlying substrate and covering the traces, thereby providing protection for the electrical connection between the die and the underlying substrate and the trace on the substrate below.

[0059] 应该注意,为了说明的目的以解释各个实施例的部件,在此的讨论涉及附接至衬底的管芯。 [0059] It should be noted that, for purposes of illustration to explain features of various embodiments discussed herein relate to a substrate attached to the die. 在其他实施例中,管芯可以是诸如封装件、封装衬底、中介层、管芯、印刷电路板等的另一衬底。 In other embodiments, the die may be another substrate such as a package, a package substrate, an interposer, a die, a printed circuit board or the like. 类似地,例如,下面的衬底可以是封装件、封装衬底、中介层、管芯、印刷电路板等。 Similarly, for example, the underlying substrate may be a package, a package substrate, an interposer, a die, a printed circuit board or the like.

[0060] 同样地,图4Α至图6Β示出了形成一些实施例的工艺中的各个中间阶段,其中,“Α”图是平面图,而“B”图是平图是沿着相应的“Α”图的BB线的截面图。 [0060] Similarly, FIG 4Α 6Β to illustrate various embodiments of the formation of some intermediate stages of the process in which, "Α" is a plan view of the FIG., The "B" figure is flat FIG along respective "Α "BB line sectional view of FIG. 首先参照图4Α和图4Β,示出了第一衬底402的平面图和沿着图4Α中的BB线截取的截面图。 Referring first to FIGS 4alpha and 4Β, it shows a plan view of a first substrate 402 and a cross-sectional view taken along line 4Α BB in FIG. 例如,第一衬底402可以是集成电路管芯、封装衬底、晶圆、印刷电路板、中介层等。 For example, the first substrate 402 may be an integrated circuit die, a package substrate, a wafer, a printed circuit board, the interposer and the like. 在一些实施例中,使用BOT配置。 In some embodiments, a BOT configuration. 例如,图4Α和图4Β示出了迹线404。 For example, FIGS. 4Α 4Β and trace 404 shows. 通常地,迹线404将电信号路由至期望位置和/或用于扩展管芯的覆盖区。 Typically, the electrical signal routing traces 404 to a desired position and / or to extend the coverage area of ​​the die. 迹线404的宽度或直径可以与球(或凸块)直径大约相同,或者可以几乎比球(或凸块)直径窄2至4倍。 Width or diameter of the traces 404 may be about the same as balls (or bumps) in diameter, or may be almost than balls (or bumps) is narrower diameter 2 to 4 times. 例如,迹线404可以具有介于约ΙΟμπι和40 μ m之间的线宽度以及介于约30 μ m和70 μ m之间的迹线节距P。 For example, trace 404 may have a pitch between the trace line width and between about ΙΟμπι between about 40 μ m and 30 μ m and 70 μ m P. 迹线可以具有窄、宽或锥形的形状。 Traces may have the shape of a narrow, wide or tapered. 在一些实施例中,迹线的终端可以具有与迹线的主体不同的形状,或者迹线主体可以具有基本上恒定的厚度。 In some embodiments, the terminal may have traces traces of different body shapes, body or traces may have a substantially constant thickness. 迹线的终端和迹线的主体形成为一个整体,这不同于将焊盘布置在迹线上。 Body and traces traces terminal formed integrally, which is different from the bonding pad is arranged on the trace. 迹线可以具有基本上长于球(或凸块)直径的长度。 Trace may have a length substantially longer than the diameter of the balls (or bumps). 另一方面,连接焊盘可以具有与球或凸块直径类似的长度或宽度。 On the other hand, connection pads may have similar or the ball bump diameter length or width.

[0061] 作为实例,在一些实施例中,迹线404可以包括诸如Al、Cu、Au、它们的合金的导电材料、其他材料或它们的组合和/或多层。 [0061] As an example, in some embodiments, the traces 404 may include information such as Al, Cu, Au, alloys thereof electrically conductive material, other materials or combinations thereof and / or a multilayer. 可选地,迹线404可以包括其他材料。 Alternatively, the traces 404 may comprise other materials. 迹线404可以由涂布在迹线404上的金属饰面覆盖,金属饰面诸如有机薄膜或混合材料(诸如Ni/Pd/Au)的层。 It traces 404 may be formed in trace metal finish coating on the cover 404, an organic thin film such as a metallic finish or a mixed material (such as a Ni / Pd / Au) layer. 在一些实施例中,邻近的迹线之间的节距可以介于约10 μπι和40 μπι之间。 In some embodiments, the pitch between adjacent traces may be between about 10 μπι and 40 μπι.

[0062] 图4Α和图4Β还示出了保护层406。 [0062] FIGS 4Α 4Β and also shows a protective layer 406. 通常地,保护层406提供防止环境污染物的保护、衬底上的电路迹线之间的电绝缘电阻、抗化学和抗腐蚀或保护、机械(划痕、磨损)保护、焊料表面上的边界、迹线和/或衬底上的额外的抓取力、以及改进的介电可靠性。 Typically, the protective layer 406 provides protection against environmental contaminants, the electrical insulation resistance between the circuit traces on the substrate, and corrosion or chemical protection, mechanical (scratching, wear) protection, to the solder surface boundary , traces and / or additional gripping force on the substrate, and improved dielectric reliability. 例如,在一些实施例中,保护层406是聚合物或其他介电材料。 For example, in some embodiments, the protective layer 406 is a polymer or other dielectric material. 例如,在一些实施例中,保护层406是通过封闭或旋涂、图案化以及随后的固化形成的聚合物。 For example, in some embodiments, the protective polymer layer 406 is formed by a closed or spin coating, patterning, and subsequent curing.

[0063] 保护层406覆盖迹线404的部分,诸如迹线的位于第一衬底402的外周区中的部分。 [0063] The protective layer 406 covers portions of the traces 404, such as a peripheral zone located on the first substrate portion 402 of the traces. 例如,在图4Α示出的实施例中,保护层406与由图4Α中的虚线轮廓表示的管芯附接区408分隔开并且形成在管芯附接区408周围。 For example, in the embodiment shown in FIG. 4Α embodiment, the protective layer 406 and the die attach area indicated by the dashed outline in FIG 4Α and 408 are formed spaced apart around the die attach area 408. 如下面更详细地讨论的,管芯附接区408表示在其上将布置另一衬底的区域。 As discussed in more detail below, die attach region 408 indicates a region on which another substrate is disposed in. 保护层406将保护迹线404免受外部环境污染物的影响并且调整保护层406的尺寸以允许底部填充物完全填充管芯和第一衬底402之间的区域,同时也覆盖暴露的迹线404。 The protective layer 406 guard traces 404 from external environmental contaminants and sized to allow the protective layer 406 and the bottom 402 completely fills the region between the first substrate filling the die, and also cover the exposed traces 404. 保护层406的厚度可以为约30 μm至约40 μm,诸如约35 μπι。 The thickness of the protective layer 406 may be about 30 μm to about 40 μm, such as about 35 μπι.

[0064] 现在参照图5Α和图5Β,示出了根据一些实施例的在第二衬底520已经附接至第一衬底402之后的图4Α和图4Β的第一衬底402。 [0064] Referring now to FIGS. 5Α and 5Β, shows some drawings after the second substrate 520 has been attached to the first substrate 402 according to the first embodiment and the substrate 4Α 4Β 402. 例如,第二衬底520可以是管芯、衬底、晶圆、封装衬底、印刷电路板等。 For example, the second substrate 520 may be a die, a substrate, a wafer, a package substrate, a printed circuit board. 第二衬底520通过电连接件522电连接至第一衬底。 Substrate 520 is electrically connected to a second member 522 connected to the substrate by a first electrically. 在一些实施例中,电连接件522包括导电柱522a(例如,铜柱)和连接至导电柱522a的焊料材料522b,但是可以使用其他的电连接件。 In some embodiments, the electrical connector 522 includes a conductive column 522a (e.g., copper pillar) is connected to the conductive pillar 522a and solder 522b material, but other electrical connections.

[0065] 在一些实施例中,第一衬底402是集成电路管芯,而第二衬底520是晶圆,这些衬底接合在倒装芯片芯片级封装件(FCCSP)中。 [0065] In some embodiments, the first substrate 402 is an integrated circuit die and the second substrate 520 is a wafer, the substrate is bonded in a flip-chip chip scale package (FCCSP) in. 随后可以分割晶圆以形成单独的封装件。 Then the wafer may be divided to form individual packages. 然而,可以使用其他配置。 However, other configurations may be used.

[0066] 如图5A和图5B所示,遮挡区(KOR) 524延伸在第二衬底520周围并且位于第二衬底520和保护层406之间。 [0066] FIGS 5A and 5B, the occlusion zone (KOR) 524 extending around the second substrate 520 and 406 positioned between the second substrate 520 and the protective layer. 在一些实施例中,KOR 524包括保护层406的内边缘与第二衬底520的边缘间隔开遮挡距离(KOD) 区域。 In some embodiments, KOR 524 includes an edge 406 of the inner edge of the protective layer and the second substrate 520 is spaced apart from the shield (of KOD) region. 在一些实施例中,KOR 524的面积为第二衬底520的面积的约5%至约18%之间。 In some embodiments, KOR area of ​​the second area 524 of substrate 520 is between about 5% to about 18%. 例如,第二衬底520的面积为宽度胃1乘以长度L ^KOR 524的面积与第二衬底520的面积(例如,宽度胃1乘以长度LJ的比率介于约1:20至约9:50之间。此外,在一些实施例中,遮挡距离D1大于或等于约420 μ m0 For example, the area of ​​the second substrate 520 is the width times the length of a stomach L ^ KOR area and the second area 524 of substrate 520 (e.g., length multiplied by width stomach LJ 1 ratio between about 1:20 to about between 9:50 Furthermore, in some embodiments, the occlusion distance D1 is greater than or equal to about 420 μ m0

[0067] 已经发现,使用这些方针(K0R 524的面积与第二衬底520的面积的比率以及遮挡距离的最小尺寸),在保护层406的边缘和第二衬底520的边缘之间提供足够的距离以允许施加底部填充材料,从而使得底部填充材料将基本上无空隙并且覆盖KOR 524中的暴露的迹线。 [0067] It has been found, the use of these lines (the area ratio of an area K0R 524 of the second substrate 520 and a minimum size of the shielding distance) between the edges of the protective layer 406 and the second substrate 520 to provide sufficient distance to allow the underfill material is applied, so that the underfill material substantially free of voids and covering the traces of the exposed KOR 524. 如上所讨论的,具有较小的距离可以导致第一衬底402和第二衬底520之间的填充能力差,从而产生空隙,而具有较大的距离可以导致KOR 524中的迹线暴露。 As discussed above, it may result in a smaller distance between the filling capacity of the first substrate 402 and second substrate 520 is poor, thereby creating a void, but having a greater distance may result in traces KOR 524 exposed. 保持如上所讨论的遮挡距离和KOR 524解决了这些问题,从而防止或减少第一衬底402和第二衬底520之间的空隙的出现,并且提供KOR 524中的暴露迹线的更好覆盖。 Holding occlusion distance KOR 524 as discussed solve these problems, thereby preventing or reducing the occurrence of a gap between the first substrate 402 and second substrate 520, and provide better coverage in KOR 524 exposed traces .

[0068] 图6A和图6B不出了根据一些实施例的在第一衬底402和第二衬底520之间介于底部填充物650之后的第一衬底402和第二衬底520。 [0068] FIGS. 6A and 6B and the second substrate 402 not in accordance with some of the first substrate 520 after the substrate 402 between the first 520 and the second substrate 650 between the underfill embodiment. 在一些实施例中,底部填充物650包括分配到第二衬底520和保护层406之间的间隙(例如,KOR 524)内的聚合物、热固性环氧树脂等。 In some embodiments, an underfill 650 includes a distribution to the gap (e.g., KOR 524) polymer, a thermosetting epoxy resin 406 between the substrate 520 and the second protective layer. 例如,在一些实施例中,底部填充材料是具有二氧化硅填充材料的高分子化合物。 For example, in some embodiments, the underfill material is a polymer compound having a silica filler. 可以沿着芯片的一个边缘施加底部填充物650的小珠,其中,底部填充物650通过毛细作用被吸引到芯片下方,直到底部填充物650完全填充第一衬底402和第二衬底520之间的间隙。 Underfill 650 may be applied in beads, wherein the underfill 650 is attracted to the bottom of the chip by capillary action, until the bottom of the filler 650 completely fills the first substrate 402 and second substrate 520 along one edge of the chip, the gap between.

[0069] 图7是根据一些实施例的示出制造的工艺的流程图。 [0069] FIG. 7 is a flowchart illustrating some embodiments of the manufacturing process. 该工艺开始于步骤702,其中,提供第一衬底,从而使得第一衬底包括管芯附接区、遮挡区和外围区,其中,保护层保护外围区中的迹线,诸如以上参照图4A和图4B讨论的。 The process begins at step 702, wherein the first substrate is provided, so that the first substrate includes a die attach region, occlusion region and a peripheral region, wherein the protective layer protects the peripheral region of the traces, such as described above with reference to FIG. 4A and 4B discussed. 在步骤704中,提供第二衬底,并且在步骤706中,将第二衬底附接至第一衬底,诸如以上参照图5A和图5B讨论的。 In step 704, a second substrate, and in step 706, a second substrate attached to the first substrate, such as described above with reference to FIGS. 5A and 5B discussed. 以一种方式将第一衬底附接至第二衬底,以提供第一衬底和保护层的最接近的边缘之间的KOR区和遮挡距离。 KOR area and occlusion distance between the first substrate in a manner attached to the second substrate, providing a first substrate and a protective layer closest to the edge. 在步骤708中,将底部填充物布置在第一衬底和第二衬底之间。 In step 708, the underfill disposed between the first and second substrates. 保持如以上讨论的KOR和遮挡距离允许将底部填充物布置为几乎没有空隙,同时为KOR内的迹线提供保护。 KOR and holding as discussed above allows occlusion distance underfill disposed almost no gap, while providing protection for the traces within KOR.

[0070] 在实施例中,提供一种器件。 [0070] In an embodiment, there is provided a device. 该器件包括具有形成在其上的迹线的第一衬底。 The device comprises a first substrate having formed on its traces. 第一衬底具有管芯附接区、围绕管芯附接区的外围的遮挡区以及围绕遮挡区的外围的外围区。 A first substrate having a die attach region of the peripheral region, the peripheral contact around the die attach area around the periphery of the occlusion zone and the occlusion zone. 第一衬底还包括位于外围区中的迹线上面的保护层。 The first substrate further includes a peripheral region of the traces above the protective layer. 第二衬底电连接至管芯附接区中的第一衬底,并且底部填充物介于第一衬底和第二衬底之间,底部填充物延伸在位于遮挡区中的迹线上方,其中,遮挡区的面积介于第二衬底的面积的约5%和约18%之间。 The second substrate is electrically connected to the first substrate die attach region, and underfill between the first and second substrates, the underfill extends occlusion region located side trace between, wherein about 5% and about 18% of the area of ​​the occlusion area between the second area of ​​the substrate.

[0071] 在另一实施例中,提供一种器件。 [0071] In another embodiment, there is provided a device. 该器件包括第一衬底,第一衬底具有管芯附接区、外围区以及介于管芯附接区和外围区之间的遮挡区,其中,保护层覆盖外围区中的迹线,并且其中,保护层不延伸到管芯附接区和遮挡区内。 The device includes a first substrate, a first substrate having a peripheral region of the trace die attach region, the occlusion region between the peripheral region and interposed between the die attach region and a peripheral region, wherein the protective layer covers, and wherein the protective layer does not extend to the die attach region and a shielding region. 第二衬底电连接至第一衬底,从而使得第二衬底位于第一衬底的管芯附接区上方。 The second substrate is electrically connected to the first substrate, the second substrate such that the die is located above the attachment of the first substrate contact region. 管芯附接区对应于第一衬底的直接位于第二衬底下方的区域,并且遮挡区从保护层的边界延伸至管芯附接区的边界。 Die attach region corresponding to the first region of the substrate located directly below the second substrate, and the shielding region extends from the boundary of the protective layer to the boundary of the die attach region. 遮挡区的面积介于第二衬底的面积的约5%和约18%之间。 Occlusion zone between the area of ​​the second area of ​​the substrate between about 5% and about 18%.

[0072] 在又一实施例中,提供一种形成半导体器件的方法。 [0072] In yet another embodiment, a method of forming a semiconductor device. 该方法包括提供第一衬底,第一衬底具有在其上形成的迹线,以及在第一衬底的部分上方形成保护层。 The method includes providing a first substrate, a first substrate having a trace formed thereon, and forming a protective layer over a portion of the first substrate. 将第二衬底附接至第一衬底。 A second substrate attached to the first substrate. 遮挡区延伸在保护层的边界和第二衬底的外围之间,其中,遮挡区的面积介于第二衬底的面积的约5%和约18%之间。 Occlusion zone extending between the peripheral boundary of the protective layer and the second substrate, wherein the area of ​​the occlusion area between about 5% and about 18% of the area is between the second substrate.

[0073] 上面概述了若干实施例的特征,使得本领域普通技术人员可以更好地理解本发明的方面。 [0073] The above outlined features of several embodiments so that those skilled in the art may better understand the aspects of the invention. 本领域普通技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。 Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying the embodiments described herein the same purposes and / or achieving the same advantages of the embodiments other processes and structures. 本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,他们可以对本发明做出多种变化、替换以及改变。 Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and without departing from the spirit and scope of the present invention, they can make various variations of the present invention, substitutions and alterations .

Claims (10)

  1. 1.一种器件,包括: 第一衬底,具有在所述第一衬底上形成的迹线,所述第一衬底具有管芯附接区、围绕所述管芯附接区的外围的遮挡区以及围绕所述遮挡区的外围的外围区,所述第一衬底具有位于所述外围区中的覆盖所述迹线的保护层; 第二衬底,电连接至所述管芯附接区中的所述第一衬底;以及底部填充物,介于所述第一衬底和所述第二衬底之间,所述底部填充物延伸在位于所述遮挡区中的所述迹线上方; 其中,所述遮挡区的面积介于所述第二衬底的面积的约5%和约18%之间。 1. A device, comprising: a first substrate having a trace formed on said first substrate, said first substrate having a die attach region, said die attach around a peripheral region shielding area and a peripheral area surrounding the peripheral area of ​​the occlusion, the first substrate having a protective layer covering the peripheral region of the trace; a second substrate, electrically connected to the die the attachment region of the first substrate; and an underfill material, interposed between the first substrate and the second substrate, the underfill extends in the occlusion zone located in the said side trace; wherein the area of ​​the occlusion area between about 5% and about 18% of the area between the second substrate.
  2. 2.根据权利要求1所述的器件,其中,所述第二衬底包括集成电路管芯。 2. The device according to claim 1, wherein said second substrate comprises an integrated circuit die.
  3. 3.根据权利要求1所述的器件,其中,所述第二衬底的边缘和所述保护层的最接近的边缘之间的遮挡距离等于或大于约420 μ m。 3. The device of claim 1, wherein the distance between the shielding edge of the second substrate and the closest edge of the protective layer is equal to or greater than about 420 μ m.
  4. 4.根据权利要求1所述的器件,其中,所述底部填充物包括具有二氧化硅填充材料的高分子化合物。 4. The device of claim 1, wherein the base filler comprises a silica filler having a polymer compound.
  5. 5.根据权利要求1所述的器件,其中,所述底部填充物完全覆盖位于所述遮挡区和所述管芯附接区中的所述迹线。 5. The device according to claim 1, wherein said filler completely covers the bottom portion of the shielding region and located in the die attach region traces.
  6. 6.根据权利要求1所述的器件,其中,所述第二衬底使用迹线上凸块连接件附接至所述第一衬底。 6. The device of claim 1, wherein said second substrate trace using a bump connecting member attached to the first substrate.
  7. 7.根据权利要求1所述的器件,其中,所述第二衬底包括使用焊料材料直接连接至所述第一衬底上的第一迹线的铜柱。 7. The device of claim 1, wherein said second substrate comprises using a solder material is directly connected to the copper post on the first trace of the first substrate.
  8. 8.一种器件,包括: 第一衬底,具有管芯附接区、外围区以及介于所述管芯附接区和所述外围区之间的遮挡区,其中,保护层覆盖所述外围区中的迹线,并且其中,所述保护层不延伸到所述管芯附接区和所述遮挡区内;以及第二衬底,电连接至所述第一衬底,所述第二衬底位于所述第一衬底的所述管芯附接区上方; 其中,所述管芯附接区对应于所述第一衬底的直接位于所述第二衬底下方的区域; 其中,所述遮挡区从所述保护层的边界延伸至所述管芯附接区的边界; 其中,所述遮挡区的面积介于所述第二衬底的面积的约5%和约18%之间。 8. A device, comprising: a first substrate having a die attach region, the occlusion region between the peripheral region and interposed between said die attach region and the peripheral region, wherein the protective layer covers the traces in the peripheral region, and wherein the protective layer does not extend to the die attach region and the shielding region; and a second substrate, electrically connected to the first substrate, the second a second substrate located above the die attach region of the first substrate; wherein the die attach region corresponding to the region located directly below the second substrate of the first substrate; wherein said shielding region extends from the boundary of the protective layer to the die attach region of the boundary of contact; wherein the blocking area between the region of about 5% and about 18% of the area of ​​the second substrate between.
  9. 9.根据权利要求8所述的器件,还包括介于所述第一衬底和所述第二衬底之间的底部填充物。 9. The device of claim 8, further comprising a filler is interposed between the bottom of the first substrate and the second substrate.
  10. 10.一种形成半导体器件的方法,所述方法包括: 提供第一衬底,所述第一衬底具有在所述第一衬底上形成的迹线; 在所述第一衬底的部分上方形成保护层;以及将第二衬底附接至所述第一衬底; 其中,遮挡区延伸在所述保护层的边界和所述第二衬底的外围之间,所述遮挡区的面积介于所述第二衬底的面积的约5%和约18%之间。 10. A method of forming a semiconductor device, the method comprising: providing a first substrate, the first substrate having a trace formed on said first substrate; a first portion of the substrate forming over the protective layer; and a second substrate attached to the first substrate; wherein the shielding region extends between the boundary of the periphery of the second protective layer and the substrate, the shielding region the area interposed between said second substrate area between about 5% and about 18%.
CN 201410800491 2012-04-18 2014-12-19 Method And Device Used For Packaging Boss Chip On Trace CN105762087A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5647123A (en) * 1995-10-16 1997-07-15 Motorola, Inc. Method for improving distribution of underfill between a flip chip die and a circuit board
US20100007015A1 (en) * 2008-07-11 2010-01-14 Bernardo Gallegos Integrated circuit device with improved underfill coverage
US8089148B1 (en) * 2009-08-11 2012-01-03 Amkor Technology, Inc. Circuit board and semiconductor device having the same
CN103378041A (en) * 2012-04-18 2013-10-30 台湾积体电路制造股份有限公司 Methods and apparatus for bump-on-trace chip packaging

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5647123A (en) * 1995-10-16 1997-07-15 Motorola, Inc. Method for improving distribution of underfill between a flip chip die and a circuit board
US20100007015A1 (en) * 2008-07-11 2010-01-14 Bernardo Gallegos Integrated circuit device with improved underfill coverage
US8089148B1 (en) * 2009-08-11 2012-01-03 Amkor Technology, Inc. Circuit board and semiconductor device having the same
CN103378041A (en) * 2012-04-18 2013-10-30 台湾积体电路制造股份有限公司 Methods and apparatus for bump-on-trace chip packaging

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