TWI843675B - Electronic package and electronic structure thereof - Google Patents

Abstract

An electronic structure is provided, in which a plurality of conductors are disposed on one surface of an electronic body, and epoxy resin is used as a protective layer to encapsulate the plurality of conductors, and a circuit portion is bonded to the other surface of the electronic body, and a plurality of external bumps and solder material are formed on the circuit portion. Therefore, by the protective layer, heat energy can be effectively transferred from the protective layer to the solder material during a process of heating the electronic structure, so as to avoid a problem of non-wetting of the solder material.

Description

Electronic packaging and electronic structures

The present invention relates to a semiconductor device, in particular to an electronic package and its electronic structure and manufacturing method.

In order to ensure the continued miniaturization and multifunctionality of electronic products and communication equipment, semiconductor packaging needs to develop towards miniaturization to facilitate multi-pin connections and have high functionality. For example, in advanced process packaging, commonly used packaging types include 2.5D packaging process, fan-out wiring with embedded bridge component process (abbreviated as FO-EB), etc. Among them, FO-EB has the advantages of low cost and multiple material suppliers compared to 2.5D packaging process.

Figures 1A and 1B are cross-sectional schematic diagrams of a portion of the manufacturing process of a conventional semiconductor package.

As shown in FIG. 1A , an electronic structure 1a and a carrier 9 on which an insulating layer 14 is disposed are provided, and a plurality of conductive pillars 13 are formed on the carrier 9.

The carrier 9 is, for example, a plate made of a semiconductor material (such as silicon or glass), on which a release layer 90 and a metal layer 91 such as titanium/copper are sequentially formed by coating, so that the insulating layer 14 is formed on the metal layer 91, and the insulating layer 14 is combined with a circuit layer 141, wherein the material forming the insulating layer 14 is a dielectric material.

The electronic structure 1a includes an electronic body 11, a circuit portion 12, a plurality of conductors 11a formed on the electronic body 11, and a plurality of copper bumps 12a formed on the circuit portion 12 and electrically connected to the circuit portion 12, and a solder material 12c is formed on the copper bump 12a. Then, a dielectric layer 11b made of polyimide (PI) material is formed on the electronic body 11 so that the dielectric layer 11b covers the plurality of conductors 11a, and a bonding layer 12b is formed on the circuit portion 12 so that the bonding layer 12b covers the plurality of copper bumps 12a and the solder material 12c.

The electronic body 11 is a silicon substrate having a plurality of conductive through-holes 110 penetrating the electronic body 11 to electrically connect the circuit portion 12 and the plurality of conductors 11a.

The circuit portion 12 includes at least one passivation layer 120 and a conductive trace 121 combined with the passivation layer 120, so that the conductive trace 121 electrically connects the conductive through-hole 110 and the plurality of copper bumps 12a.

As shown in FIG. 1B , the electronic structure 1a is bonded to the insulating layer 14 with the bonding layer 12b thereon, and the solder material 12c is bonded to the circuit layer 141, and then the subsequent packaging process is performed.

However, in the known semiconductor package, when the subsequent packaging process is carried out, because the electronic body 11 is covered with a dielectric layer 11b of PI material, and the thermal conductivity of PI material is relatively low (i.e., less than 1W/mK), during the heating process, heat energy will accumulate in the dielectric layer 11b of PI material and cannot be effectively transferred to the solder material 12c below, causing the solder material 12c to have a non-wetting condition.

Furthermore, during the cooling process, the dielectric layer 11b of the PI material still presents a semi-molten fluid state of the B stage, so the dielectric layer 11b still has a certain viscosity, so the adsorption fixture 70 of the removal device main body 7 used to remove the electronic structure 1a is easy to stick to the PI material during the process of separating the electronic structure 1a, causing the adsorption fixture 70 (as shown in the dotted line) to adhere to the electronic structure 1a and detach from the removal device main body 7.

Therefore, how to overcome the above-mentioned problems of knowledge and technology has become an urgent issue to be solved.

In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic structure, which includes: an electronic body, on one surface of which a plurality of conductors are provided; a protective layer, formed on the electronic body to cover the plurality of conductors, wherein the protective layer is an epoxy resin encapsulation adhesive; a circuit portion, which is combined with the other surface of the electronic body; a plurality of external bumps, which are formed on the circuit portion and electrically connected to the circuit portion, wherein a solder material is formed on the plurality of external bumps; and a bonding layer, which is formed on the circuit portion to cover the plurality of external bumps and the solder material.

The present invention also provides a method for manufacturing an electronic structure, which includes: providing an electronic body, wherein a plurality of conductors are provided on one surface, and a circuit portion is bonded to the other surface; forming a plurality of external bumps on the circuit portion, and the plurality of external bumps are electrically connected to the circuit portion, wherein a solder material is formed on the plurality of external bumps; forming a bonding layer on the circuit portion so that the bonding layer covers the plurality of external bumps and the solder material; forming an epoxy resin encapsulation adhesive on the electronic body so that the epoxy resin encapsulation adhesive covers the plurality of conductors; thermosetting the epoxy resin encapsulation adhesive; and leveling the epoxy resin encapsulation adhesive to form a protective layer.

In the aforementioned electronic structure and its manufacturing method, the thickness of the bonding layer is equal to or greater than the sum of the heights of each of the external bumps and the solder material.

In the aforementioned electronic structure and its manufacturing method, the thickness of the protective layer is greater than the thickness of the bonding layer.

In the aforementioned electronic structure and its manufacturing method, the thickness of the protective layer is 5 times the thickness of the bonding layer.

In the aforementioned electronic structure and its manufacturing method, the thickness of the protective layer is 5 to 30 microns.

In the aforementioned electronic structure and its manufacturing method, the thickness of the bonding layer is 15 to 50 microns.

In the aforementioned electronic structure and its manufacturing method, the electronic main body is a silicon substrate, which has a plurality of conductive through-holes penetrating the electronic main body to electrically connect the circuit part and the plurality of conductors.

The present invention also provides an electronic package, which includes: a coating layer; the aforementioned electronic structure is embedded in the coating layer; and a plurality of conductive pillars are embedded in the coating layer.

The aforementioned electronic package further includes a circuit structure formed on the coating layer and electrically connecting the plurality of conductive posts and the plurality of conductive bodies. Furthermore, it may include an electronic component disposed on the circuit structure and electrically connected to the circuit structure.

As can be seen from the above, the electronic package and its electronic structure and manufacturing method of the present invention mainly use epoxy resin packaging colloid with a higher thermal conductivity as a protective layer to replace the dielectric layer of the conventional PI material. Therefore, compared with the conventional technology, during the heating process of the electronic structure, the heat energy of the present invention can be effectively transferred to the external contact bump below to melt the solder material, thereby avoiding the solder material from having an undesirable condition of not being wetted.

Furthermore, during the cooling process, the epoxy resin encapsulation colloid is shaped after being thermally cured, that is, it is in a solid state, so the protective layer is no longer sticky. Therefore, compared with the conventional technology, the adsorption fixture of the removal device body used to remove the electronic structure will not stick to the glue material during the process of separating the electronic structure, so as to avoid the adsorption fixture adhering to the electronic structure and separating from the removal device body.

1a,2a:Electronic structure

11,21: Electronic subject

11a,21a: Conductor

11b: Dielectric layer

110,210: Conductive perforation

12,22: Circuit Department

12a: Copper bump

12b, 22b: Binding layer

12c, 22c: Soldering materials

120,220: Passivation layer

121,221: Conductive traces

13,23: Conductive column

14,200: Insulation layer

141,241: Circuit layer

2: Electronic packaging components

20: Circuit structure

201: Circuit redistribution layer

202: Electrical contact pad

22a: External protrusion

23a: End

24: Wiring structure

24a: First side

24b: Second side

240: Dielectric layer

25: Coating layer

25a: First surface

25b: Second surface

26: Electronic components

26a: Conductive bump

260:Soldering materials

262: Base glue

27,300: Conductive components

27a: Metal layer under the bump

270: Metal bump

271:Soldering materials

28: Packaging layer

29: Protective layer

30:Packaging substrate

31: Strong firmware

7: Remove the main body of the device

70: Adsorption fixture

8: Electronic board

9: Carrier

90: Release layer

91:Metal layer

D1,D2:Thickness

H: Total height

L, S: cutting path

Figures 1A and 1B are schematic cross-sectional views of a portion of the manufacturing process of a conventional semiconductor package.

Figures 2A to 2H are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

Figure 2A-1 is a schematic cross-sectional view of one step of the process of Figure 2A.

Figure 3 is a cross-sectional diagram of the subsequent process of Figure 2H.

The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.

It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second", "one" etc. used in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments in their relative relationships shall also be regarded as the scope of implementation of the present invention without substantially changing the technical content.

Figures 2A to 2H are cross-sectional schematic diagrams of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A , an electronic board 8 is provided, which includes a plurality of electronic structures 2a arranged in an array.

The electronic structure 2a comprises an electronic body 21, a circuit portion 22 combined with the electronic body 21, a plurality of conductors 21a formed on the electronic body 21, and a plurality of external bumps 22a formed on the circuit portion 22 and electrically connected to the circuit portion 22, wherein a solder material 22c is formed on the external bump 22a, and a bonding layer 22b is formed on the circuit portion 22 to cover the external bumps 22a and the solder material 22c, and a protective layer 29 is formed on one surface of the electronic structure 2a to cover the conductors 21a.

In this embodiment, the electronic body 21 is a silicon substrate, such as a semiconductor chip, which has a plurality of conductive through-holes 210 penetrating the electronic body 21, such as conductive through-silicon vias (TSV), to electrically connect the circuit portion 22 and the plurality of conductors 21a. For example, the circuit portion 22 is bonded to another surface of the electronic body 21 and includes at least one passivation layer 220 bonded to the electronic body 21 and at least one conductive trace 221 bonded to the passivation layer 220, so that the conductive trace 221 electrically connects the conductive through-hole 210 and the plurality of external bumps 22a. It should be understood that there are many forms of the device structure having the conductive through-hole 210, and there is no special limitation.

Furthermore, the conductor 21a and the external bump 22a are metal pillars such as copper pillars, and the bonding layer 22b is a non-conductive film (NCF). For example, the external bump 22a and the solder material 22c are first made on the circuit part 22 of the electronic structure 2a, and then the non-conductive film (the bonding layer 22b) is pasted. Therefore, when the external bump 22a adopts a small pitch, low height and high density configuration specification, selecting a non-conductive film as the bonding layer 22b is beneficial to covering the external bump 22a.

Furthermore, the thickness D2 of the bonding layer 22b is equal to or greater than the sum of the heights H of the external bump 22a and the solder material 22c, so that the bonding layer 22b completely covers the external bump 22a and the solder material 22c.

The protective layer 29 is an epoxy molding compound (EMC). For example, the protective layer 29 can be formed on the electronic board 8 by liquid compound, injection, lamination or compression molding.

In this embodiment, the thickness D1 of the protective layer 29 is greater than the thickness D2 of the bonding layer 22b. For example, the thickness D1 of the protective layer 29 is 5 times the thickness D2 of the bonding layer 22b, wherein the thickness D1 of the protective layer 29 is 5-30 micrometers (um), preferably 15-25um, and the thickness D2 of the bonding layer 22b is 15-50um, preferably 20-40um.

In addition, the manufacturing process of the protective layer 29 is to first form an epoxy resin encapsulation colloid on the electronic main body 21, as shown in FIG. 2A-1, so that the epoxy resin encapsulation colloid covers the plurality of conductive bodies 21a, and then bake the epoxy resin encapsulation colloid to thermoset the epoxy resin encapsulation colloid. Afterwards, the epoxy resin encapsulation colloid is polished and leveled to form the protective layer 29.

As shown in FIG. 2B , a carrier 9 having a plurality of conductive pillars 23 is provided, and the electronic board 8 is cut along the cutting path L shown in FIG. 2A to obtain a plurality of electronic structures 2a.

In this embodiment, the carrier 9 is, for example, a plate made of a semiconductor material (such as silicon or glass), on which a release layer 90 and a metal layer 91 such as titanium/copper are sequentially formed by coating, for example, so that a wiring structure 24 is formed on the metal layer 91.

The wiring structure 24 has a first side 24a and a second side 24b opposite to each other, and the wiring structure 24 is bonded to the metal layer 91 with its second side 24b.

Furthermore, the wiring structure 24 includes at least one dielectric layer 240 and a circuit layer 241 combined with the dielectric layer 240. For example, the material forming the dielectric layer 240 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials, and the circuit layer 241 and the dielectric layer 240 can be formed by a redistribution layer (RDL) process.

Furthermore, the conductive pillar 23 is disposed on the first side 24a of the wiring structure 24 and electrically connected to the circuit layer 241. In this embodiment, the material forming the conductive pillar 23 is a metal material such as copper or a solder material. For example, the conductive pillars 23 are formed by electroplating on the circuit layer 241 by exposure and development.

As shown in FIG. 2C , the electronic structure 2a is arranged on the carrier 9 so that the conductive pillars 23 surround the electronic structure 2a.

In this embodiment, the electronic structure 2a is bonded to the first side 24a of the wiring structure 24 by the bonding layer 22b thereon, so that the external bump 22a is bonded to the circuit layer 241 by the solder material 22c.

Since the electronic body 21 is covered with a protective layer 29 of epoxy resin encapsulation adhesive, and the thermal conductivity of epoxy resin encapsulation adhesive is relatively high (i.e., greater than 1W/mK), compared to the prior art, during the heating process of the electronic structure 2a, the heat energy will be effectively transferred to the external bump 22a below to melt the solder material 22c, thereby avoiding the solder material 22c from having a non-wetting condition.

Furthermore, during the cooling process, the epoxy resin encapsulation colloid is shaped after being thermally cured, that is, it is in a solid state, so the protective layer 29 is no longer sticky. Therefore, compared with the conventional technology, the adsorption fixture used to remove the electronic structure 2a of the removal device body will not stick to the glue during the process of separating the electronic structure 2a, so as to avoid the adsorption fixture adhering to the electronic structure 2a and separating from the removal device body.

As shown in FIG. 2D , a coating layer 25 is formed on the first side 24a of the wiring structure 24 so that the coating layer 25 covers the electronic structure 2a, the protective layer 29 and the conductive pillars 23, wherein the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the protective layer 29, the end surface of the conductor 21a and the surface of the end 23a of the conductive pillar 23 are exposed from the first surface 25a of the coating layer 25, and the coating layer 25 is bonded to the first side 24a of the wiring structure 24 with its second surface 25b.

In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, packaging glue such as epoxy, or molding compound. For example, the process of the coating layer 25 can be formed on the wiring structure 24 by liquid compound, injection, lamination, or compression molding. It should be understood that the material forming the protective layer 29 can be the same or different from the material of the coating layer 25.

Furthermore, the first surface 25a of the coating layer 25 can be made flush with the top surface of the protective layer 29, the surface of the end 23a of the conductive column 23, and the end surface of the conductor 21a by a flattening process, so that the surface of the end 23a of the conductive column 23 and the end surface of the conductor 21a expose the first surface 25a of the coating layer 25. For example, the flattening process removes part of the material of the protective layer 29, part of the material of the conductive column 23, part of the material of the conductor 21a, and part of the material of the coating layer 25 by grinding.

As shown in FIG. 2E , a circuit structure 20 is formed on the first surface 25a of the cladding layer 25 and the protective layer 29 so that the circuit structure 20 electrically connects the conductive pillar 23 and the conductive body 21a.

In this embodiment, the circuit structure 20 includes at least one insulating layer 200 and at least one circuit redistribution layer (RDL) 201 disposed on the insulating layer 200. This embodiment shows a plurality of insulating layers 200 and a plurality of circuit redistribution layers 201, wherein the outermost insulating layer 200 can be used as a solder barrier layer, and the outermost circuit redistribution layer 201 is exposed outside the solder barrier layer to serve as an electrical contact pad 202, such as a micro pad (commonly known as μ-pad).

Furthermore, the material forming the circuit redistribution layer 201 is copper, and the material forming the insulating layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., or a solder-proof material such as green paint, ink, etc.

As shown in FIG. 2F , a plurality of electronic components 26 are arranged on the circuit structure 20, and then a packaging layer 28 is used to cover the electronic components 26.

In this embodiment, the electronic component 26 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In one embodiment, the electronic component 26 is, for example, a semiconductor chip such as a graphics processing unit (GPU) or a high-bandwidth memory (HBM), and the electronic structure 2a is electrically connected to the circuit structure 20 through the conductor 21a, and then electrically connected to the electronic component 26.

Furthermore, the electronic component 26 has a plurality of conductive bumps 26a such as copper pillars, which are electrically connected to the electrical contact pad 202 through a plurality of solder materials 260 such as solder bumps, and the packaging layer 28 can simultaneously cover the electronic components 26 and the conductive bumps 26a. In other embodiments, an under bump metallurgy (UBM) (not shown) can be formed on the electrical contact pad 202 or the electronic component 26 to facilitate the bonding of the solder material 260 or the conductive bump 26a.

In addition, the packaging layer 28 is an insulating material, such as polyimide (PI), dry film, packaging colloid such as epoxy, or molding compound, which can be formed on the circuit structure 20 by lamination or molding. It should be understood that the material forming the packaging layer 28 may be the same as or different from the material of the encapsulation layer 25.

In addition, the bottom glue 262 may be formed between the electronic component 26 and the circuit structure 20 to cover the conductive bumps 26a and the solder material 260, and then the packaging layer 28 may be formed to cover the bottom glue 262 and the electronic component 26.

As shown in FIG. 2G , the carrier 9 and the release layer 90 thereon are removed, and then the metal layer 91 is removed to expose the second side 24b of the wiring structure 24.

In this embodiment, when peeling off the release layer 90, the metal layer 91 is used as a barrier to avoid damaging the dielectric layer 240 of the wiring structure 24, and after removing the carrier 9 and the release layer 90 thereon, the metal layer 91 is removed by etching to expose the circuit layer 241.

As shown in FIG. 2H , a singulation process is performed along the cutting path S shown in FIG. 2G , and a plurality of conductive elements 27 are formed on the second side 24b of the wiring structure 24 , so that the conductive elements 27 are electrically connected to the circuit layer 241 to obtain an electronic package 2 .

In this embodiment, the conductive element 27 includes a metal bump 270 such as a copper material and a solder material 271 formed on the metal bump 270. For example, an under bump metallization (UBM) 27a may be formed on the circuit layer 241 to facilitate bonding the metal bump 270. It should be understood that when the number of contacts (IO) is insufficient, the RDL process can still be used to perform a layer addition operation to reconfigure the number and position of IOs of the wiring structure 24.

Furthermore, a flattening process, such as grinding, can be used to remove part of the material of the packaging layer 28 so that the upper surface of the packaging layer 28 is flush with the upper surface of the electronic component 26, as shown in FIG. 3, so that the electronic component 26 is exposed outside the packaging layer 28.

Furthermore, as shown in FIG3 , the conductive elements 27 can be disposed on a package substrate 30. Furthermore, the package substrate 30 is subjected to a ball implantation process on the lower side to form a plurality of conductive elements 300 such as solder balls, which are used in subsequent processes. The package substrate 30 is disposed on a circuit board (not shown) with the conductive elements 300 on the lower side thereof.

In addition, a reinforcing member 31, such as the metal frame shown in FIG. 3, can be provided on the package substrate 30 as required to eliminate the problem of stress concentration and prevent the electronic package 2 from warping.

The present invention also provides an electronic structure 2a, which includes: an electronic body 21, a protective layer 29, a circuit portion 22, a plurality of external bumps 22a, and a bonding layer 22b.

The electronic body 21 has a plurality of conductive bodies 21a on one of its surfaces.

The protective layer 29 is formed on the electronic body 21 to cover the plurality of conductors 21a, wherein the protective layer 29 is an epoxy resin encapsulation colloid.

The circuit portion 22 is bonded to another surface of the electronic body 21.

The external bump 22a is formed on the circuit portion 22 and electrically connected to the circuit portion 22, wherein a solder material 22c is formed on the external bump 22a.

The bonding layer 22b is formed on the circuit portion 22 to cover the plurality of external bumps 22a and the solder material 22c.

In one embodiment, the thickness D2 of the bonding layer 22b is equal to or greater than the sum of the heights H of the external bump 22a and the solder material 22c.

In one embodiment, the thickness D1 of the protective layer 29 is greater than the thickness D2 of the bonding layer 22b.

In one embodiment, the thickness D1 of the protective layer 29 is 5 times the thickness D2 of the bonding layer 22b.

In one embodiment, the thickness D1 of the protective layer 29 is 5 to 30 microns.

In one embodiment, the thickness D2 of the bonding layer 22b is 15 to 50 microns.

In one embodiment, the electronic body 21 is a silicon substrate having a plurality of conductive vias 210 penetrating the electronic body 21 to electrically connect the circuit portion 22 and the plurality of conductors 21a.

In addition, the present invention also provides an electronic package 2, which includes: a coating layer 25, an electronic structure 2a embedded in the coating layer 25, and a plurality of conductive pillars 23.

In one embodiment, the electronic package 2 further includes a circuit structure 20 formed on the coating layer 25 and electrically connecting the plurality of conductive posts 23 and the plurality of conductive bodies 21a. Furthermore, the electronic package 2 further includes an electronic component 26 disposed on the circuit structure 20 and electrically connected to the circuit structure 20.

In summary, the electronic package and its electronic structure and manufacturing method of the present invention use epoxy resin encapsulation colloid as a protective layer to replace the dielectric layer of the conventional PI material. Therefore, in the process of heating the electronic structure, the heat energy will be effectively transferred to the external contact bump below to melt the solder material, thereby avoiding the solder material from having an undesirable condition of not being wetted.

Furthermore, during the cooling process, the epoxy resin encapsulation glue is shaped after being thermally cured, that is, it is in a solid state, so the protective layer is no longer sticky, so the adsorption fixture of the removal device body used to remove the electronic structure will not stick to the glue during the process of separating the electronic structure, so as to avoid the adsorption fixture adhering to the electronic structure and detaching from the removal device body.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

2a: Electronic structure

21: Electronic subject

21a: Conductor

210: Conductive perforation

22: Circuit Department

22a: External protrusion

22b: Binding layer

22c: Soldering material

220: Passivation layer

221: Conductive traces

29: Protective layer

8: Electronic board

D1,D2:Thickness

H: Total height

L: cutting path

Claims (10)

An electronic structure includes: an electronic body, on one surface of which a plurality of conductors are provided; a protective layer, formed on the electronic body to cover the plurality of conductors, wherein the protective layer is formed by thermosetting and flattening an epoxy resin encapsulation adhesive, and the thermal conductivity coefficient of the epoxy resin encapsulation adhesive is greater than 1W/mK; a circuit portion, which is combined with the On the other surface of the electronic body; a plurality of external bumps are formed on the circuit portion and electrically connected to the circuit portion, wherein a solder material is formed on the plurality of external bumps; and a bonding layer is formed on the circuit portion to cover the plurality of external bumps and the solder material, and the bonding layer is a non-conductive film, wherein the protective layer and the bonding layer are made of different materials. An electronic structure as described in claim 1, wherein the thickness of the bonding layer is equal to or greater than the sum of the heights of each of the external bumps and the solder material. An electronic structure as described in claim 1, wherein the thickness of the protective layer is greater than the thickness of the bonding layer. An electronic structure as described in claim 1, wherein the thickness of the protective layer is 5 times the thickness of the bonding layer. An electronic structure as described in claim 1, wherein the thickness of the protective layer is 5 to 30 microns. An electronic structure as described in claim 1, wherein the thickness of the bonding layer is 15 to 50 microns. An electronic structure as described in claim 1, wherein the electronic body is a silicon substrate having a plurality of conductive through-holes penetrating the electronic body to electrically connect the circuit portion and the plurality of conductors. An electronic package includes: a wiring structure including at least one dielectric layer and a circuit layer bonded to the dielectric layer; a coating layer formed on the wiring structure; an electronic structure as described in any one of claims 1 to 7, embedded in the coating layer so that the external bump is bonded to the circuit layer through the solder material; and a plurality of conductive posts, embedded in the coating layer and electrically connected to the circuit layer. The electronic package as described in claim 8 further includes a circuit structure formed on the coating layer and electrically connecting the plurality of conductive posts and the plurality of conductive bodies. The electronic package as described in claim 9 further includes an electronic component disposed on the circuit structure and electrically connected to the circuit structure.

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