KR20160014341A - Optoelectronic device and method for manufacturing the same - Google Patents

Optoelectronic device and method for manufacturing the same Download PDF

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KR20160014341A
KR20160014341A KR1020140096430A KR20140096430A KR20160014341A KR 20160014341 A KR20160014341 A KR 20160014341A KR 1020140096430 A KR1020140096430 A KR 1020140096430A KR 20140096430 A KR20140096430 A KR 20140096430A KR 20160014341 A KR20160014341 A KR 20160014341A
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South Korea
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electrode
semiconductor layer
conductive
conductive type
type electrode
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KR1020140096430A
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Korean (ko)
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KR101974976B1 (en
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자오싱 천
지아취안 왕
첸츠 랴오
츠야오 청
춘가이 코
첸푸 선
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에피스타 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

According to the present invention, an optoelectronic device comprises: a first semiconductor layer which has at least four boundaries, a first surface, and a second surface corresponding to the first surface, wherein any two adjacent boundaries can configure a corner; a second semiconductor layer which is formed on the first surface of the first semiconductor layer; a second-conductivity-type electrode which is formed on the second semiconductor layer; and at least two first-conductivity-type electrodes which are formed on the first surface of the first semiconductor layer, wherein the first-conductivity-type electrodes are separated from each other to form a design shape.

Description

[0001] OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric device, and more particularly to an electrode design of a photoelectric device.

The principle behind the emission of light-emitting diodes (LEDs) is that electrons emit energy in the form of light using the energy difference between the n-type semiconductor and the p-type semiconductor. Since this principle of luminescence differs from the principle of incandescence due to heat generation, the light emitting diode is called a luminescent source. In addition, light-emitting diodes are highly anticipated in today's lighting market because light-emitting diodes have the advantages of high durability, long life, light weight, and low consumption of electricity. Gradually replacing the conventional light source as a next- It is applied in various fields such as traffic signal, backlight module, street light, medical facility.

1 is a schematic view of a conventional light emitting device structure. 1, a conventional light emitting device 100 includes a transparent substrate 10, a semiconductor laminate 12 disposed on the transparent substrate 10, and at least one electrode (not shown) disposed on the semiconductor laminate 12, And the semiconductor layer 12 includes a first conductive semiconductor layer 120, an active layer 122, and a second conductive semiconductor layer 124 from top to bottom.

In addition, the light emitting device 100 may further be combined with other devices to form a light-emitting apparatus. 2 is a schematic view of a conventional light emitting device structure. As shown in FIG. 2, the light emitting device 200 includes a submount 20 of one or more circuits 202; Mount 20 and bonding and fixing the light emitting device 100 on the submount 20 so that the substrate 10 of the light emitting device 100 is mounted on the circuit 202 on the submount 20, One or more solder (22) for electrical connection with the substrate (22); And an electrical connection structure 24 for electrically connecting the electrode 14 of the light emitting device 100 and the circuit 202 on the submount 20. The submount 20 is electrically connected to the light emitting device 200 May be a lead frame or a large size mounting substrate that simplifies circuit placement and improves the heat dissipation effect.

It is an object of the present invention to provide an electrode design form of a photoelectric device.

The photoelectric device of the present invention has at least four boundaries, a first surface, a second surface corresponding to the first surface, and any two adjacent adjacent boundaries define a first A semiconductor layer; A second semiconductor layer formed on the first surface of the first semiconductor layer; A second conductive type electrode formed on the second semiconductor layer; And at least two first conductive electrodes formed on a first surface of the first semiconductor layer, wherein the first conductive electrodes are separated from each other to form a design.

1 is a side view of a conventional array photoelectric device.
2 is a schematic view of a conventional light emitting device structure.
3A is a plan structural view of a photoelectric device unit according to an embodiment of the present invention.
3B is a side view of a photoelectric device unit according to an embodiment of the present invention.
3C is a plan structural view of a photoelectric device unit according to another embodiment of the present invention.
4A to 4D are plan structural views of a photoelectric device unit according to another embodiment of the present invention.
5A to 5C are schematic views of a light emitting module.
6A to 6B are schematic views showing a light source generating apparatus.
7 is a schematic view showing a light bulb.

The present invention discloses a light emitting device and a method of manufacturing the same, and in order to understand the present invention in more detail, it is desirable to combine FIGS. 3A to 7 to refer to the following description.

3A and 3B are a plan view and a side view of an opto-electronic device 300 according to a first embodiment of the present invention. Fig. 3B is a side structural view in the direction of A-B-C in Fig. 3A. The photoelectric element 300 has a substrate 30. The substrate 30 is not limited to a single material but may be a complex substrate composed of a plurality of different materials. For example, the substrate 30 may include a first substrate (not shown) and a second substrate (not shown) bonded together.

A first semiconductor layer 311 having a first surface 3111 and a second surface 3112 corresponding to the first surface on the substrate 30 through a conventional epitaxial growth process, An active layer 312 formed on the first surface 3111 of the active layer 311 and a second semiconductor layer 313 formed on the active layer 312 are formed. Subsequently, a part of the epitaxial layer is selectively removed by photolithography to expose a part of the first semiconductor layer 311 at the boundary of the photoelectric device 300, and a trench S is formed in the photoelectric device 300 . In one embodiment, the trench S exposes a portion of the first semiconductor layer 311 and is surrounded by the second semiconductor layer 313. In one embodiment, the trench S is elongate in plan view.

The first insulating layer 341 is formed on the surface of the epitaxial layer 31 of the photoelectric element 300 and the sidewalls of the trench S by a technique such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) .

At least one first conductive type electrode 321 is formed on the exposed first semiconductor layer 311 adjacent to the boundary of the photoelectric element 300. The first first conductive type electrode 321 is not surrounded by the second semiconductor layer 313 and the second first conductive type electrode 322 is formed in the trench S in an embodiment. The first first conductive type electrode 321 and the second first conductive type electrode 322 separated in this embodiment form the electrode design form of the first conductive type electrode.

In an embodiment of the present invention, the electrode design pattern may include selection of electrode quantity, electrode shape, and electrode position to improve current diffusion in the region close to the boundary of the optoelectronic device. For example, the electrode design of the first conductive type electrode may include one or a plurality of first conductive type electrodes 321 and one or a plurality of second first conductive type electrodes 322, The first conductive type electrode 322 is surrounded by the second semiconductor layer 313 as viewed from above and has an elongated shape.

In one embodiment, the first semiconductor layer 311 of the opto-electronic device 300 has at least four boundaries, two adjacent boundaries can form a corner, and there is no conductive structure beyond the boundary. In this embodiment, the first first conductive type electrodes 321 are formed at two corners on the same boundary of the photoelectric elements 300, separated from each other, and do not cross the boundary of the photoelectric elements 300. [

In one embodiment, the projection of the first first conductive electrode 321 on the first semiconductor layer 311 may be graphic, which may be polygonal, circular, elliptical, semicircular, Plane). The second first conductive-type electrode 322 may be linear, arc-shaped, linear-arc mixed, or may have at least one branch portion. In one embodiment, the second first conductive electrode 322 may have a head portion and a tail portion, and the width of the head portion is larger than the width of the tail portion.

Next, the second conductive type electrode 33 is formed on the second semiconductor layer 313. In one embodiment, the ratio of the projected area of the second conductive type electrode 33 in the first semiconductor layer 311 to the trademarked area of the second semiconductor layer 313 is 90 to 100%.

Next, on the first first conductive type electrode 321, the second first conductive type electrode 322, the second conductive type electrode 33, and a part of the second insulating layer 341, Layer 342 may be formed. The second insulating layer 342 may include a first opening 3421 for electrically connecting the second conductive electrode 33 to a fourth electrode 36 to be formed later and a second insulating layer 342, May have a second opening 3422 for electrically connecting the first first conductive electrode 321 to a third electrode 35 formed later. In one embodiment, the first insulating layer 341 or the second insulating layer 342 may completely cover the exposed first semiconductor layer 311.

In one embodiment, the first insulating layer 341 or the second insulating layer 342 may be a transparent insulating layer. The material of the first insulating layer 341 or the second insulating layer 342 may be an oxide, a nitride, or a polymer. The oxide may be aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ) It may include titanium dioxide (TiO 2), tantalum pentoxide (tantalum pentoxide, Ta 2 O 5 ), or aluminum oxide (AlO x), the nitride can include aluminum nitride (AlN), silicon nitride (SiN x) Have; The polymer may comprise a material such as polyimide or benzocyclobutane (BCB) or a combination thereof. In one embodiment, the first insulating layer 341 or the second insulating layer 342 may be a distributed Bragg reflector structure.

Finally, a third electrode 35 is formed on the second insulating layer 342, the first first conductive type electrode 321, and the second first conductive type electrode 322, Electrically connected to the first conductive type electrode 321 and the second first conductive type electrode 322 and the fourth electrode is formed on the second insulating layer 342 and the second conductive type electrode 33 And is electrically connected to the second conductive electrode 33. In one embodiment, the ratio of the projected area of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 is 80 to 100%.

In one embodiment, the third electrode 35 may cover only a portion of the first first conductive electrode 321, and in another embodiment the third electrode 35 may cover a portion of the first first conductive electrode 321 321).

In one embodiment, the height from the top edge of the third electrode 35 to the top edge of the substrate 30 is H1 and the height from the top edge of the fourth electrode 36 to the top edge of the substrate 30 is H2 , H1 is substantially the same as H2. In one embodiment, the difference between H1 and H2 is less than 5-10%. By controlling the difference between H1 and H2, it is possible to reduce the probability of a broken line when the photoelectric element 300 later forms a flip chip structure with a mount board or a circuit element, thereby increasing the product yield. In one embodiment, the boundary between the third electrode 35 and the fourth electrode 36 has a minimum distance D1, D1 is greater than 50 占 퐉, and in one embodiment D1 is 50 to 200 占 퐉, Lt; / RTI >

The first conductive type electrode 321, the second first conductive type electrode 322, the second conductive type electrode 33, the third electrode 35 and the fourth electrode 36 May have a multi-layer structure, and / or include a reflective layer (not shown), and may have a reflectance of 80% or more with respect to the light beam emitted from the active layer 312. In one embodiment, the first first conductive type electrode 321, the second first conductive type electrode 322, and the third electrode 35 may be formed in the same process. In one embodiment, the light rays emitted from the optoelectronic device 300 are incident on the first first conductive type electrode 321, the second first conductive type electrode 322, the second conductive type electrode 33, And may be reflected by the electrode 35 or the fourth electrode 36 to leave the photoelectric device 300 in the direction of the substrate 30. [

The first conductive type electrode 321, the second first conductive type electrode 322, the second conductive type electrode 33, the third electrode 35 and the fourth electrode (not shown) 36 may be made of a metal such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium Sn), an alloy thereof, or a laminated combination thereof.

In one embodiment, a mounting board or circuitry (not shown) may be provided to provide a first mounting plate electrode (not shown) and a second mounting plate electrode (not shown) on the mounting plate or circuit element in a wire bonding or soldering manner, Can be formed. The first mounting plate electrode and the second mounting plate electrode can form a flip chip structure with the third electrode 35 and the fourth electrode 36 of the photoelectric element 300.

A first control layer (not shown) may be formed between the first first conductive electrode 321 and / or the second first conductive electrode 322 and the third electrode 35 in one embodiment And the first control layer is electrically connected to the first first conductive type electrode 321 and / or the second conductive type electrode 322 and the third electrode 35. In one embodiment, a second control layer (not shown) may be formed between the second conductive electrode 33 and the fourth electrode 36, and the second control layer may be formed between the second conductive electrode 33 and the second electrode 4 electrode 36, as shown in Fig. In this embodiment, the first regulating layer and the second regulating layer may each have a height, and the heights of the first regulating layer and the second regulating layer may be different from each other due to the formation positions of the first regulating layer and the second regulating layer, And the height of H2. Accordingly, the height difference between the H1 and the H2 can be reduced by designing the formation heights of the first adjustment layer and / or the second adjustment layer, respectively, so that the photoelectric device 300 can later be mounted on the mount plate or the circuit element and the flip chip structure It is possible to reduce the disconnection probability at the time of forming and further increase the product yield. In one embodiment, the projected area of the first control layer on the first semiconductor layer 3111 is larger than the projected area of the third electrode 35 on the first semiconductor layer 311, or the projected area of the second control layer The projected area on the first semiconductor layer 311 is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311. [ In one embodiment, preferred materials for the first or second control layer include, for example, gold, silver, copper, chromium, aluminum, platinum, , Nickel (Ni), titanium (Ti), tin (Sn) and the like, alloys thereof or a laminated combination thereof. In one embodiment, the first tuning layer or second tuning layer may be a multi-layer structure and / or may comprise a reflective layer (not shown) and may have a reflectivity of at least 80% for the light emitted from the active layer 312 have.

3C is a plan view of the electrooptic device 400 according to the second embodiment of the present invention. The manufacturing method of the photoelectric device, the materials for use, the reference numerals and the like in this embodiment are the same as those in the first embodiment, and will not be described further. In an embodiment of the present invention, the electrode design type may include selection of the electrode quantity, the electrode shape, and the electrode position so as to improve current diffusion in the region close to the boundary of the optoelectronic device 400.

In one embodiment, the first semiconductor layer 311 of the opto-electronic device 400 has at least four boundaries, and two adjacent boundaries can form a corner, and there is no conductive structure beyond the boundary. In this embodiment, the first first conductive type electrode 321 is formed at an arbitrary corner of the first semiconductor layer 311, the second insulating layer 342 is formed on the first first conductive type electrode 321, And a second opening 3422 for electrically connecting the third electrode 35 formed later. The second first conductive type electrode 322 is formed on the first semiconductor layer 311 and is surrounded by the second semiconductor layer 313 and the second insulating layer 342 is formed on the second semiconductor layer 311, Shaped electrode 322 and a third opening 3423 for electrically connecting the third electrode 35 to be formed subsequently.

In this embodiment, the projection of the first first conductive type electrode 321 on the first semiconductor layer 311 can be a graphic shape, which is polygonal, circular, elliptical, semicircular, or circular arc. The second first conductive type electrode 322 has an elongated shape, and the shape thereof may be a linear shape, arcuate shape, a mixed shape of a linear shape and an arc shape, or may have at least one branched portion. In one embodiment, the second first conductive electrode 322 may have a head portion and a tail portion, and the width of the head portion is larger than the width of the tail portion.

In this embodiment, a third first conductive type electrode 323 is formed on the first semiconductor layer 311 exposed next to the boundary of the photoelectric element 400. The third first conductive electrode 323 is not surrounded by the second semiconductor layer 313 and the second insulating layer 342 is not surrounded by the third first conductive electrode 323 And a fourth opening 3424 for electrically connecting the third electrode 35 to be formed. A fourth first conductive type electrode 324 is formed on the exposed first semiconductor layer 311 beside the boundary of the photoelectric element 400. [ In one embodiment, the fourth first conductive electrode 324 is not surrounded by the second semiconductor layer 313, the second insulating layer 342 is surrounded by the fourth first conductive electrode 324, And a fifth opening 3425 for electrically connecting the third electrode 35 to be formed.

In this embodiment, the projection of the third first conductive type electrode 323 on the first semiconductor layer 311 can be formed into a graphic shape, which is polygonal, circular, elliptical, semicircular, or circular arc. The fourth first conductive type electrode 324 may be linear, arc-shaped, linear and arc-shaped, or may have at least one branch portion. In one embodiment, the fourth first conductive electrode 324 may have a head portion and a tail portion, and the width of the head portion may be greater than the width of the tail portion. The shape of the third first conductive type electrode 323 and the shape of the fourth first conductive type electrode 324 are different in one embodiment.

According to the product design requirement in one embodiment, the first first conductive type electrode 321 and the third first conductive type electrode 323 may be formed beside the same boundary of the photoelectric element 400, Are separated from each other. In one embodiment, the first first conductive type electrode 321 and the fourth first conductive type electrode 324, or the third first conductive type electrode 323 and the fourth conductive type electrode 324, And is not formed next to the same boundary of the photoelectric elements 400. [

The head portion of the fourth first conductive electrode 324 may be covered by the third electrode 35 and the tail portion of the fourth first conductive electrode 324 may be covered by the fourth electrode 36 ). ≪ / RTI > The projected area of the third electrode 35 on the first semiconductor layer 311 is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311, And the projected area of the fourth electrode 36 on the first semiconductor layer 311 is between 110 and 120%. In one embodiment, the extending directions of the tees of the second first conductive type electrode 322 and the fourth first conductive type electrode 324 are substantially parallel to each other.

4A is a plan view of an opto-electronic device 500 according to a third embodiment of the present invention. The manufacturing method of the photoelectric device, the materials for use, the reference numerals and the like in this embodiment are the same as those in the first embodiment, and will not be described further. In an embodiment of the present invention, the electrode design type may include selection of electrode quantity, electrode shape, and electrode position to improve current spreading in the region close to the boundary of the optoelectronic device 500.

In this embodiment, the four boundaries of the photoelectric element 500 form a rectangle, and two adjacent boundaries can form a corner, and there is no conductive structure beyond the boundary. The boundary has a first long side B1, a second long side B3, a first short side B2 and a second short side B4. In one embodiment, the length of the first long side B1 or the second long side B3 is greater than the first short side B2 or the second short side B4. In this embodiment, the projection of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 is arranged along the first long side B1 or the second long side B3.

In this embodiment, the two first separated first conductive type electrodes 321 are formed at two corners of the first short side B2, and the second insulating layer 342 is formed at the two first corners of the first short side B2, Shaped electrode 321 and a second opening 3422 for electrically connecting the third electrode 35 to be formed subsequently. The two fourth first conductive type electrodes 324 are positioned on the first semiconductor layer 311 exposed next to the boundary between the first long side B1 and the second long side B3. In this embodiment, the third first conductive type electrode 323 is formed on the first short side B2 and the second insulating layer 342 is formed after the third first conductive type electrode 323 And a fourth opening 3424 for electrically connecting the third electrode 35 to the first electrode 342. The fourth conductive type electrode 324 is not surrounded by the second semiconductor layer 313 and the second insulating layer 342 is formed by the fourth conductive type electrode 324 and the third And may have a third opening 3423 for electrically connecting the electrode 35.

In one embodiment, the distance between the third first conductive type electrode 323 and the first two first conductive type electrodes 321 is substantially the same. In addition, the first first conductive-type electrode 321, the fourth first conductive-type electrode 324, and the third electrode 35 may be formed in the same step.

In this embodiment, the projection of the first first conductive type electrode 321 on the first semiconductor layer 311 can be a graphic shape, which is polygonal, circular, elliptical, semicircular, or circular arc. The projection of the third first conductive type electrode 323 on the first semiconductor layer 311 can take the shape of a polygon, a circle, an ellipse, a semicircle, or an arc surface. The fourth first conductive type electrode 324 has an elongated shape and may be linear, arc-shaped, linear and arc-like mixed, or may have at least one branch portion. In one embodiment, the fourth first conductive electrode 324 includes a head portion and a tail portion, and the width of the head portion may be larger than the width of the tail portion. The shape of the third first conductive type electrode 323 and the shape of the fourth first conductive type electrode 324 are different in one embodiment.

In one embodiment, the head portion of the fourth first conductive electrode 324 faces the first short side B2 and the tail portion faces the second short side B4. The head portion of the fourth first conductive type electrode 324 may be covered by the third electrode 35 and the tail portion of the fourth first conductive type electrode 324 may be covered by the fourth electrode 36). In one embodiment, the teem extension directions of the two fourth first conductive electrodes 324 are substantially parallel to each other. The projected area of the third electrode 35 on the first semiconductor layer 311 is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311, And the projected area of the fourth electrode 36 on the first semiconductor layer 311 is 110 to 120%.

4B is a plan view of an opto-electronic device 600 according to a fourth embodiment of the present invention. The manufacturing method of the photoelectric device, the materials for use, the reference numerals and the like in this embodiment are the same as those in the first embodiment, and will not be described further. In an embodiment of the present invention, the electrode design type may include selection of the electrode quantity, the electrode shape, and the electrode position so as to improve current diffusion in the region close to the boundary of the opto-electronic device 600.

In this embodiment, the four boundaries of the photoelectric element 600 form a rectangle, and two adjacent boundaries can form a corner, and there is no conductive structure beyond the boundary. The photoelectric element 600 has a first long side B1, a second long side B3, a first short side B2 and a second short side B4. In one embodiment, the length of the first long side B1 or the second long side B3 is greater than the first short side B2 or the second short side B4. In this embodiment, the projection of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 is arranged along the first long side B1 or the second long side B3.

In this embodiment, at least one first conductive type electrode 321 is included. Four first conductive type electrodes 321 may be formed at four corners of the first semiconductor layer 311 and the second insulating layer 342 may be formed of a first conductive type And a second opening 3422 for electrically connecting the electrode 321 and the third electrode 35 to be formed later. Two second first conductive electrodes 322 are formed on the first semiconductor layer 311 and are surrounded by the second semiconductor layer 313 and the second insulating layer 342 is formed on the second semiconductor layer 311. [ And a third opening 3423 for electrically connecting the first conductive type electrode 322 and the subsequently formed third electrode 35 to each other.

In this embodiment, the projection of the first first conductive type electrode 321 on the first semiconductor layer 311 can be a graphic shape, which is polygonal, circular, elliptical, semicircular, or circular arc. The projection of the second first conductive type electrode 322 on the first semiconductor layer 311 can be a graphic shape, which is polygonal, circular, elliptical, semicircular, or circular arc. In one embodiment, the projected shapes of the two second first conductive electrodes 322 on the first semiconductor layer 311 may be the same or different.

The third electrode 35 in this embodiment includes two extensions 351 and the two extensions 351 may form a substantially notch R and the fourth electrode 36 may have a notch (R). In addition, the first first conductive-type electrode 321, the second first conductive-type electrode 322, and the third electrode 35 may be formed in the same step.

4C is a plan view of an electrooptic device 700 according to a fifth embodiment of the present invention. The manufacturing method of the photoelectric device, the materials for use, the reference numerals and the like in this embodiment are the same as those in the first embodiment, and will not be described further. In an embodiment of the present invention, the shape of the electrode design may include selection of the electrode quantity, the electrode shape, and the electrode position so as to improve current diffusion in the region close to the boundary of the optoelectronic device 700.

In one embodiment, the first semiconductor layer 311 of the opto-electronic device 700 has at least four boundaries, two adjacent boundaries can form a corner, and there is no conductive structure beyond the boundary. The first insulating layer 342 includes four first conductive type electrodes 321 formed at four corners of the first semiconductor layer 311 and the second insulating layer 342 includes four first conductive type electrodes 321 formed at four corners of the first semiconductor layer 311, The second electrode 342 may be provided with a second opening 3422 for electrically connecting the third electrode 35 to be formed later. A plurality of second first conductive electrodes 322 are formed on the first semiconductor layer 311 and are surrounded by the second semiconductor layer 313 and the second insulating layer 342 is formed on the second semiconductor layer 311. [ And a fourth opening 3424 for electrically connecting the first conductive type electrode 322 and the third electrode 35 formed later. A plurality of third first conductive type electrodes 323 are formed on the first semiconductor layer 311 exposed beside the boundary of the photoelectric element 700. [ In other words, the third first conductive type electrode 323 is not surrounded by the second semiconductor layer 323, and one or a plurality of the third conductive layers 323 is formed beside any one boundary of the first semiconductor layer 311, 1 conductive type electrode 323. The second insulating layer 342 may have a third opening 3423 for electrically connecting the second first conductive electrode 322 to a third electrode 35 formed later.

In this embodiment, the projection of the first first conductive type electrode 321 on the first semiconductor layer 311 can be a graphic shape, which is polygonal, circular, elliptical, semicircular, or circular arc . The projection of the second first conductive type electrode 322 on the first semiconductor layer 311 can be a graphic shape, which is polygonal, circular, elliptical, semicircular, or circular arc. In one embodiment, the second first conductive electrode 322 may have an elongated shape and the extending direction may be parallel to the extending direction of the extending portion 351. The second first conductive type electrode 322 may be linear, arc-shaped, linear-arc hybrid, or at least one branch. In one embodiment, the projected areas of the plurality of second conductive type electrodes 322 on the first semiconductor layer 311 may be the same or different. The projection of the third first conductive type electrode 323 on the first semiconductor layer 311 can take the shape of a polygon, a circle, an ellipse, a semicircle, or an arc surface.

In this embodiment, the third electrode 35 includes three extensions 351, the three extensions 351 can form substantially two notches R, An electrode 36 may be formed in the two notches R. In this embodiment, at least one second conductive type electrode 322 may be formed in the extended portion 351.

The first first conductive type electrode 321, the second first conductive type electrode 322 and the third first conductive type electrode 323 are formed on the first semiconductor layer 311 in the first embodiment, The projection shapes may be the same or different. In addition, the first first conductive type electrode 311, the second first conductive type electrode 322, the third first conductive type electrode 323, and the third electrode 35 are formed in the same step .

4D is a plan view of an electrooptic device 700 'according to a sixth embodiment of the present invention. The present embodiment is a possible variation of the fifth embodiment, and the manufacturing method, the material used, the electrode design, the reference numerals, and the like of the photoelectric element are the same as those of the fifth embodiment.

The second insulating layer 3421 'of the photoelectric element 700' in the present embodiment includes a plurality of first openings 3421 'for electrically connecting the second conductive type electrode 33 to the subsequently formed fourth electrode 36' '). The second insulating layer 342 may include a plurality of first openings 3421 to reduce the difference in heights of the third electrode 35 and the fourth electrode 36, And the flip chip type structure, the product yield is increased.

5A is a perspective view showing the exterior of the light emitting module. The light emitting module 800 includes a mount 502, a photoelectric element (not shown), a plurality of lenses 504 and 506 , 508 and 510 and two power supply terminals 512 and 514, respectively. The light emitting module 800 may be connected to a light emitting unit 540 described later.

Figs. 5B-5C are cross-sectional views showing the light emitting module 800, and Fig. 5C is an enlarged view of the area E in Fig. 5B. The mount 502 may include a top mount 503 and a bottom mount 501 and the surface of the bottom mount 501 may be in contact with the top mount 503. A lens 504 and a lens 508 are formed on the top mount 503. The upper mount 503 may form at least one through hole 515 and an opto-electronic device 300 or another opto-electronic device (not shown) formed in accordance with an embodiment of the present invention may be provided in the through hole 515 And is in contact with the lower mount 501 and is also wrapped by the rubber material 521. [ There is a lens 508 on the rubber material 521, and the material of the rubber material 521 may be a silicone resin, epoxy resin or other material. In one embodiment, a reflection layer may be formed on the two sidewalls of the through hole 515 to increase the luminous efficiency. The metal layer 517 may be formed on the lower surface of the lower mount 501 to improve the heat radiation efficiency.

6A and 6B are schematic diagrams showing a light source generating apparatus 900. The light source generating apparatus 900 includes a light emitting module 800, a light emitting unit 540, and an electric power supply system And a control element (not shown) for controlling the electric power supply system. The light source generator 900 may be a lighting device such as a streetlight, a differential or an indoor illumination light source, or may be a backlight source of a traffic signal or a flat display backlight module.

7 is a schematic view showing a light bulb. The bulb 1000 includes a housing 921, a lens 922, a lighting module 924, a support frame 925, a radiator 926, a connection 927 and an electrical connection 928. The illumination module 924 includes a mount 923 and includes at least one opto-electronic device 300 of the above embodiments or other opto-electronic devices (not shown) on the mount 923.

Specifically, the substrate 30 is a growth and / or mounting foundation. The candidate material may include a conductive substrate or a non-conductive substrate, a light-transmitting substrate or a non-light-transmitting substrate. The conductive substrate material may be at least one selected from the group consisting of germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), silicon (Si), lithium aluminum oxide (LiAlO 2 ), zinc oxide ), Aluminum nitride (AlN) metal. The light-transmitting substrate material may be at least one selected from the group consisting of sapphire, lithium aluminum oxide (LiAlO 2 ), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, diamond- (spinel, MgAl 2 O 4 ), aluminum oxide (Al 2 O 3 ), silicon oxide (SiO x ) and lithium gallium oxide (LiGaO 2 ).

The epitaxial laminate 31 includes a first semiconductor layer 311, an active layer 312, and a second semiconductor layer 313. The first semiconductor layer 311 and the second semiconductor layer 313 may be, for example, a cladding layer or a confinement layer, and may have a single or multi-layer structure. The first semiconductor layer 311 and the second semiconductor layer 313 may have different electrical characteristics, polarities or dopants, and their electrical characteristics may be selected from at least any two combinations of p-type, n-type and i- Electrons and holes are provided, and electrons and holes are combined in the active layer 312 to emit light. The material of the first semiconductor layer 311, the active layer 312 and the second semiconductor layer 313 may include III-V semiconductor materials such as Al x In y Ga (1-xy) N or Al x In y Ga (1-xy) P where 0? X, y? 1; (x + y)? Depending on the material of the active layer 312, the epitaxial laminate may include red light having a wavelength of 610 nm to 650 nm, green light having a wavelength of 530 nm to 570 nm, blue light having a wavelength of 450 nm to 490 nm, or ultraviolet light having a wavelength of less than 400 nm Release.

In another embodiment of the present invention, the opto-electronic device 300, 400, 500, 600, 700, 700 'may be an epitaxial element or a light emitting diode and its emission frequency spectrum may be a single or multiple layers of epitaxial layers It can be controlled by changing physical or chemical elements. The single or multilayer epitaxial laminate material is selected from the group consisting of aluminum (Al), gallium (Ga), indium (In), phosphorus (P), nitrogen (N), zinc (Zn) . The structure of the active layer 312 is, for example, a single heterostructure (SH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW) structure. Further, by adjusting the logarithm of the quantum well of the active layer 312, the emission wavelength can be changed.

In an embodiment of the present invention, a buffer layer (not shown) may be selectively formed between the first semiconductor layer 311 and the substrate 20. This buffer layer is a material system interposed between the two material systems to "transfer" the material system of the substrate 30 to the first semiconductor layer 311. In the structure of the light emitting diode, the buffer layer is a material layer that reduces lattice mismatch between the two materials. On the other hand, the buffer layer may be a single or multiple structure for combining two materials or two separated structures, and the material of the buffer layer may be selected from organic materials, inorganic materials, metals and semiconductors, and the structure may be a reflective layer, A conductive layer, an ohmic contact layer, a deformation resistance layer, a stress release layer, a stress adjustment layer, a bonding layer, a wavelength conversion layer, and a mechanical fixing structure . In one embodiment, the material of the buffer layer may be selected from aluminum nitride or gallium nitride, and the buffer layer may be formed by a method of sputtering or atomic layer deposition (ALD).

A contact layer (not shown) may be selectively formed between the second semiconductor layer 313 and the second conductive electrode 33. Specifically, the contact layer may be an optical layer, an electrical layer, or a combination thereof. Herein, the term "change" means changing the optical characteristics of at least one of electromagnetic radiation or light rays, and the characteristics include frequency, wavelength, intensity, flux amount, efficiency, color temperature, rendering index, light field And an angle of view, but is not limited thereto. The electrical layer may have a tendency for a change or a change to occur in at least one of numerical, density, distribution of voltage, resistance, current, or capacitance between any opposing sides of the contact layer. The constituent material of the contact layer may be an oxide, a conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a metal that transmits relatively light, a metal having a transmittance of 50% or more, Ceramics, semiconductors, doped semiconductors, and undoped semiconductors. In some applications, the material of the contact layer is at least one of indium tin oxide, tin cadmium oxide, antimony tin oxide, zinc indium oxide, zinc oxide aluminum and zinc tin oxide. In the case of a metal that emits light relatively, its thickness is approximately 0.005 mu m to 0.6 mu m.

It is to be understood that the drawings and description above correspond to only specific embodiments, but that the elements, methods, design principles, and technical principles described or disclosed in the embodiments are not necessarily limited to the specific examples, Optionally referenced, replaced, combined, adjusted or combined as necessary. Although the present invention has been described above, the scope, order of implementation or materials used and manufacturing process and method of the present invention are not limited thereto. Various modifications and alterations of the present invention are within the spirit and scope of the present invention.

100, 200, 300, 400, 500, 600, 700, 700 '
10: transparent substrate
12: Semiconductor stacking
14, E1, E2: electrode
30: substrate
U: Photoelectric element unit
31: epitaxial lamination
311: a first semiconductor layer
312: active layer
313: second semiconductor layer
S: Trench
341: first insulating layer
342: second insulating layer
3421: first opening
3422: Second opening
3423: third opening
3424: fourth opening
3425: fifth opening
321: first first conductive-type electrode
322: a second first conductive-type electrode
323: a third first conductive electrode
324: fourth first conductive electrode
33: second conductive electrode
35: third electrode
B1: 1st long stool
B3: second long stool
B4: 1st short side
351: elongated extension
R: Notch
36: fourth electrode
800: Light emitting module
501: Lower mount
502: Mount
503: Upper mount
504, 506, 508, 510: lens
512, 514: power supply terminal
515: Through hole
519: Reflective layer
521: Rubber material
540: housing
900: Light source generating device
1000: Light bulb
721: Housing
722: lens
724: Lighting module
725: Support frame
726: Radiator
727: Connection
728: electrical connection
ABC: Direction
D1: Distance
H1, H2: Height

Claims (10)

A first semiconductor layer having at least four boundaries, a first surface, a second surface corresponding to the first surface, and any two adjacent ones of the boundaries may form a corner;
A second semiconductor layer formed on the first surface of the first semiconductor layer;
A second conductive type electrode formed on the second semiconductor layer; And
At least two first conductive type electrodes formed on the first surface of the first semiconductor layer;
/ RTI >
Wherein the first conductive electrodes are separated from each other to form a design shape,
Photoelectric device. The method according to claim 1,
The above-
(1) one or a plurality of first first conductivity type electrodes located on at least one of the corners of the first semiconductor layer;
(2) one or a plurality of second first conductivity type electrodes surrounded by the second semiconductor layer;
(3) one or a plurality of third first conductivity type electrodes located on at least one of the boundaries of the first semiconductor layer;
(4) one or a plurality of fourth first conductivity type electrodes located at least one of the boundaries of the first semiconductor layer and having a shape different from that of the third first conductive type electrode;
≪ RTI ID = 0.0 > of: < / RTI > 3. The method of claim 2,
Wherein the second first conductive type electrode and / or the fourth first conductive type electrode are elongated in shape and / or the second first conductive type electrode and / or the fourth first conductive type electrode The shape of the electrode may be a linear, arcuate, a mixed linear and arcuate shape, has at least one branch, and / or has a head and a tail. 3. The method of claim 2,
The projection of the first first conductive-type electrode, the second first conductive-type electrode, or the third first conductive-type electrode on the first semiconductor layer may be graphic, and the graphic may be polygonal, An optoelectronic device having a circular, elliptical, semicircular or circular arc surface. 3. The method of claim 2,
A third electrode and a fourth electrode, wherein the third electrode is electrically connected to the first conductive electrode, and the fourth electrode is electrically connected to the second conductive electrode. 6. The method of claim 5,
Wherein the fourth conductive type electrode has a head portion or a tail portion, and the tail portion is not covered by the fourth electrode. 6. The method of claim 5,
The ratio of the projected area of the third electrode and the fourth electrode on the first semiconductor layer is 80 to 100%, and / or the minimum distance between the third electrode and the fourth electrode is greater than 50 占 퐉 And / or said third electrode comprises a plurality of extensions, said extensions substantially forming a notch, and said fourth electrode being located within said notch. 6. The method of claim 5,
A first control layer formed between the first conductive type electrode and the third electrode and electrically connecting the first conductive type electrode and the third electrode; And
A second adjusting layer formed between the second conductive type electrode and the fourth electrode and electrically connecting the second conductive type electrode and the fourth electrode;
Further comprising:
Wherein a projected area of the second control layer on the first semiconductor layer is larger than a projected area of the third electrode on the first semiconductor layer or a projected area of the second control layer on the first semiconductor layer Is larger than the projected area of the fourth electrode on the first semiconductor layer. 6. The method of claim 5,
Wherein the first semiconductor layer comprises a first boundary and a second boundary smaller in length than the first boundary,
Wherein the second first conductive-type electrode or the fourth first conductive-type electrode has a head portion and a tail portion, and the extension direction of the second first conductive-type electrode or the fourth first conductive- Wherein projections of the third electrode and the fourth electrode on the first semiconductor layer are arranged along the first boundary. 6. The method of claim 5,
Wherein the third electrode has a first top edge, the distance from the first top edge to the second surface of the first semiconductor layer is H1, the fourth electrode has a second top edge, 2 distance from the top edge to the second surface of the first semiconductor layer is H2, and H1 is substantially equal to H2.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100814464B1 (en) * 2006-11-24 2008-03-17 삼성전기주식회사 Nitride semiconductor light emitting device
KR20120086876A (en) * 2011-01-27 2012-08-06 엘지이노텍 주식회사 A light emitting device
KR20120136814A (en) * 2011-06-10 2012-12-20 엘지이노텍 주식회사 A light emitting device package
JP2013168598A (en) * 2012-02-17 2013-08-29 Toshiba Corp Semiconductor light-emitting element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100814464B1 (en) * 2006-11-24 2008-03-17 삼성전기주식회사 Nitride semiconductor light emitting device
KR20120086876A (en) * 2011-01-27 2012-08-06 엘지이노텍 주식회사 A light emitting device
KR20120136814A (en) * 2011-06-10 2012-12-20 엘지이노텍 주식회사 A light emitting device package
JP2013168598A (en) * 2012-02-17 2013-08-29 Toshiba Corp Semiconductor light-emitting element

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