KR20150145341A - Light emitting diode, Package and Method for manufacturing for the same - Google Patents

Abstract

The present invention relates to a light emitting diode, a package and a manufacturing method thereof. More specifically, the light emitting diode comprises: a substrate; a semiconductor layered structure formed by layering an n-type semiconductor layer, an activation layer, and a p-type semiconductor layer on the substrate; a p-type electrode and an n-type electrode connected to the p-type semiconductor layer and the n-type semiconductor layer, respectively; an interlayer insulation layer disposed on the p-type electrode and the n-type electrode and provided with an organic insulation layer made of an organic material; and a p-type and an n-type boding metal electrically connected to the p-type electrode and the n-type electrode, respectively. A reflective electrode is used to increase light emitting efficiency. Flexibility of the interlayer insulation layer and excellent thermal stability of the organic material are used to alleviate stress by heat and pressure.

Description

[0001] The present invention relates to a light emitting diode (LED), a package,

The present invention relates to a light emitting diode, a package, and a manufacturing method thereof. More particularly, the present invention relates to a light emitting diode, a package, and a method of manufacturing the same. More particularly, A package, and a method of manufacturing the same.

A light emitting diode (LED) is a semiconductor light emitting device that converts electrical energy into light energy. It is a device that emits light by pumping current to a compound semiconductor terminal and emitting light by the combination of electrons and holes in the p-n junction or in the active layer. In addition, since the light emitting diode has a longer lifetime and lower power consumption than conventional light sources such as incandescent lamps and fluorescent lamps, and it directly converts electric energy into light energy, it has advantages of high luminous efficiency, safety, They are applied to various fields such as LCD display, car headlight, street light, traffic light, light source for optical communication, and decorative lighting.

The conventional top emitter diode has a problem in that light is reflected by the top emitter diode structure due to an electrode or the like on the top surface of the semiconductor laminate and is not emitted. In order to solve this problem, Korean Patent No. 10-0447413 (Aug. 26, 2004) proposes a flip-chip structure in which light is emitted from a substrate by inverting the chip in a structure for emitting light through a semiconductor stacked upper surface However, since the light emitted from the active layer is emitted only in a direction opposite to the substrate, the light emitted from the active layer is emitted in a smaller amount than that of the light emitting diode in the top, but the semiconductor layer is weak in heat and pressure. There is a problem that defects are generated due to heat and pressure generated.

Therefore, in the related art, it is required to develop a method of protecting the semiconductor layer from heat and pressure stress while preventing loss of light emitted in a direction opposite to the substrate in a flip chip structure light emitting diode.

(Registered Patent) Korean Patent No. 10-0447413

The present invention provides a light emitting diode, a package, and a method of manufacturing the same, which can improve light emitting efficiency by using a reflective electrode and can relieve stress caused by heat and pressure by using an organic material having excellent ductility and thermal stability in an interlayer insulating layer, There is a purpose.

A light emitting diode according to an embodiment of the present invention includes a substrate; A semiconductor stacked structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked on the substrate; A p-type electrode and an n-type electrode respectively connected to the p-type semiconductor layer and the n-type semiconductor layer; An interlayer insulating layer provided on the p-type electrode and the n-type electrode, the interlayer insulating layer including an organic insulator layer made of an organic material; And a p-type and an n-type bonding metal provided to be electrically connected to the p-type electrode and the n-type electrode, respectively.

The p-type electrode may be a reflective electrode forming a reflective surface,

The organic material may include at least one of polyimide, polycarbonate, polyamide, polyethylene terephthalate, poly-4-vinylphenol (PVP), and polyethersulfone However,

Wherein the interlayer insulating layer further comprises an inorganic insulator layer and may be formed in a laminated structure of the organic insulator layer and the inorganic insulator layer,

The inorganic insulator layer may include at least one of silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ )

The thickness of the inorganic insulator layer may be thinner than the thickness of the organic insulator layer.

According to another embodiment of the present invention, the light emitting diode package may be bonded to the submount by flip chip bonding.

According to another aspect of the present invention, there is provided a method of fabricating a light emitting diode, comprising: sequentially laminating an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate to form a semiconductor stacked structure; Partially etching the active layer and the p-type semiconductor layer such that a part of the n-type semiconductor layer is exposed; Forming a p-type electrode and an n-type electrode on the p-type semiconductor layer and the exposed n-type semiconductor layer, respectively; Forming an interlayer insulating layer on the p-type electrode and the n-type electrode, the interlayer insulating layer including an organic insulator layer made of an organic material; Forming a via hole; And forming p-type and n-type bonding metals to be electrically connected to the exposed surfaces of the p-type electrode and the n-type electrode, respectively.

The p-type electrode may be a reflective electrode forming a reflective surface,

In the step of forming the via hole, when the organic material is a photosensitive material, the interlayer insulating layer may be patterned by photolithography to form a via hole. When the organic material is a non-photosensitive material, A via hole can be formed by etching the insulating layer using an etching mask,

Wherein the interlayer insulating layer further comprises an inorganic insulator layer and can be formed in a laminated structure of the organic insulator layer and the inorganic insulator layer,

The thickness of the inorganic insulator layer may be smaller than the thickness of the organic insulator layer.

The method of manufacturing a light emitting diode package according to another embodiment of the present invention may further include bonding the light emitting diode manufactured by the manufacturing method to a submount by a flip chip bonding method.

In the light emitting diode according to the present invention, it is possible to increase the luminous efficiency by using the p-type electrode as the reflective electrode and to reduce the parasitic capacitance while blocking the leakage current by using an organic material having insulation property but low dielectric constant. , Organic materials are excellent in ductility and thermal stability, so that stress due to heat and pressure can be relieved during packaging of light emitting diodes, thereby improving packaging reliability.

1 is a plan view showing a structure of a light emitting diode according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line A-A 'and B-B' of FIG. 1, according to an embodiment of the present invention;
3 is a cross-sectional view illustrating steps of a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. In the description, the same components are denoted by the same reference numerals, and the drawings are partially exaggerated in size to accurately describe the embodiments of the present invention, and the same reference numerals denote the same elements in the drawings.

A flip-chip light emitting diode is a light emitting diode that emits light from a substrate by inverting the chip rather than emitting light through the top surface of the semiconductor stacked layer. The electrode is not reflected and the light is not emitted. In order to emit light to the substrate as described above, a transparent substrate capable of transmitting light emitted from the pn junction or in the active layer must be used, and in order to increase the efficiency of light emission, Reflective layer.

In addition, the flip chip structure has the advantage that the distance between the active layer in which heat is actually generated and the heat sink or submount is close to allow the heat to be released more easily.

FIG. 1 is a plan view showing a structure of a light emitting diode according to an embodiment of the present invention. FIG. 2 is a sectional view taken along line A - A 'and B - B' in FIG. 1 according to an embodiment of the present invention, 2 (a) is a cross-sectional view taken along the line A-A ', and FIG. 2 (b) is a cross-sectional view taken along the line B-B'.

1 and 2, a light emitting diode 100 according to an embodiment of the present invention includes a substrate 210, an n-type semiconductor layer 221, an active layer 222, and a p-type semiconductor layer A p-type electrode 230 and an n-type electrode 240 connected to the p-type semiconductor layer 223 and the n-type semiconductor layer 221, a p-type electrode 230 and an n- An interlayer insulating layer 250 provided on the p-type electrode 230 and the n-type electrode 240 and including an organic insulator layer made of an organic material, And a p-type and an n-type bonding metal 260 provided to be electrically connected to each other.

First, the semiconductor laminated structure 220 is sequentially formed on the substrate 210 through which light is transmitted.

The substrate 210 is a substrate suitable for growing a semiconductor single crystal. The substrate 210 is formed using a transparent material including sapphire. In addition to sapphire, the substrate 210 may include at least one selected from the group consisting of ZnO, GaN, SiC, AlN) or the like. Meanwhile, in order to improve lattice matching with the substrate formed of a material such as sapphire on the substrate 210, a buffer layer made of an AlN / GaN layer or a GaN layer may be formed. However, in the embodiment of the present invention, Will not be described in detail.

The semiconductor laminated structure 220 is formed by sequentially stacking the n-type semiconductor layer 221, the active layer 222, and the p-type semiconductor layer 223 sequentially. Hereinafter, a gallium nitride semiconductor will be mainly described as an embodiment, but the material is not particularly limited.

The n-type semiconductor layer 221 is formed on the substrate 210 and may be made of a gallium nitride-based semiconductor material. More specifically, the n-type semiconductor layer 221 may be a GaN layer doped with an n-type conductivity type impurity or a GaN / AlGaN layer. As the n-type conductivity type impurity, Si, Ge, or Sn may be used , And Si are mainly used.

The active layer 222 may be formed on the n-type semiconductor layer 221 and may be formed of an InGaN / GaN layer having a multi-quantum well structure.

The p-type semiconductor layer 223 is formed on the active layer 222 and may be formed of a gallium nitride-based semiconductor material. More specifically, the p-type semiconductor layer 223 may be formed of a GaN layer or a GaN / AlGaN layer doped with a p-type conductivity-type impurity, and Mg, Zn, Be or the like may be used as the p- , And Mg are mainly used. A part of the p-type semiconductor layer 223 and the active layer 222 are removed by MESA etching to expose a part of the n-type semiconductor layer 221 on the bottom surface.

The p-type electrode 230 is formed on the p-type semiconductor layer 223. The p-type electrode 230 may be formed of a reflective electrode using a highly reflective metal such as Ag, Al, Au, Cr, Ir, Mg, Nd, Ni, Pd, Pt, Rh, The reflective electrode reflects light emitted from the active layer in a direction opposite to the substrate, toward the substrate. The p-type electrode 230 may be formed of two or more alloys of metals having high reflectivity, or may be formed of a laminate structure of different metals, or may be formed of ITO, IZO, ZnO, or In ₂ O _3, As shown in FIG. An adhesive layer for improving adhesion to the p-type semiconductor layer 223, a connection layer for allowing ohmic connection, and the like may be further stacked. The p-type electrode 230 is formed to have a smaller area than the p-type semiconductor layer 223 or to have the same area as the p-type semiconductor layer 223 so that the p-type semiconductor layer 223 is not exposed. The reason why the p-type semiconductor layer 223 is formed so as not to be exposed is to increase the reflection surface to maximize the light reflected by the reflection surface.

The n-type electrode 240 is formed on the n-type semiconductor layer 221 exposed by the etching process. The n-type electrode 240 may include an n-type pad electrode and an n-type contact electrode. The n-type contact electrode extends from the n-type pad electrode to one side of the n-type electrode 240, Is contacted with a portion of the layer (221).

Interlayer Dielectric (ILD) or Intermetal Dielectric (IMD) 250 is provided on the p-type electrode 230 and the n-type electrode 240. The interlayer insulating layer 250 may be formed by insulating the n-type electrode 240 from the p-type electrode 230 and between the p-type and n-type electrodes, (For example, a p-type semiconductor and an n-type bonding metal) having different characteristics from the n-type and p-type semiconductors, the n-type and n-type bonding metals And the p-type semiconductor, the n-type and p-type bonding metal (for example, the n-type semiconductor and the p-type semiconductor, the n-type bonding metal and the p-type bonding metal). In addition, the interlayer insulating layer 250 may also protect the semiconductor layers from heat and pressure that are required to bond the LED 100 according to the present invention to the submount in a flip chip manner. When the dielectric constant of the interlayer insulating layer is high, a capacitor (parasitic capacitor) is naturally formed between the upper and lower portions of the interlayer insulating layer and the semiconductor layer (or metal layer). When the interlayer insulating layer is formed of an organic material having a low dielectric constant, parasitic capacitance Can be reduced.

The interlayer insulating layer 250 may include an organic insulator layer that is excellent in durability and ductility, is excellent in insulation characteristics, and can form a thick film. The organic insulator layer is made of an organic material and functions as a stress buffer for relieving stress caused by heat and pressure when packaging the light emitting diode. The organic material may be selected from among polyimide, polycarbonate, polyamide, polyethylene terephthalate, poly-4-vinylphenol (PVP), and polyethersulfone (PES) For example, polyimide has an insulating property of 1 x 10 ¹⁶ to 2 x 10 ¹⁶ Ω · cm, and is effective not only for interrupting the leakage current between the layers but also for packaging the light emitting diode with a modulus of elasticity of 3 to 4 GPa Or a stress buffer layer capable of relieving stress caused by heat and pressure generated when a high voltage is applied to the light emitting diode. The dielectric constant of the organic material (for example, polyimide: 2.73) is lower than that of an inorganic material (for example, SiO _{2 having} a dielectric constant of 3.9) such as SOG, a silicon oxide film, To reduce the parasitic capacitance.

The thickness of the organic insulator layer may be at least 0.5 mu m to suppress the leakage current to some extent. The thicker the organic insulator layer, the better the leakage current characteristic and the stress relaxation property. However, if the organic insulator layer is too thick, The thickness of the organic insulator layer can be selected in the range of 0.5 to 30 占 퐉 because of the difficulty in forming the interlayer wiring portion and securing the bonding metal step coverage.

In addition, the interlayer insulating layer 250 may be formed of a single layer of the organic insulator layer, and may further include an inorganic insulator layer, and may be formed of a laminated structure of the inorganic insulator layer and the organic insulator layer. The laminated structure of the inorganic insulator layer and the organic insulator layer may be laminated with the organic insulator layer / the inorganic insulator layer or the inorganic heat insulator layer / the organic insulator layer / the inorganic insulator layer, but the number, order and materials are not particularly limited. In the case where the organic insulator layer and the organic insulator layer are formed in a laminated structure, the insulator is primarily insulated by the organic insulator layer upon application of a high voltage, and a low- The secondary insulation is performed with the inorganic insulator layer more denser than the insulation layer, so that the leakage current can be drastically lowered.

The thickness of the inorganic insulator layer may be less than the thickness of the organic insulator layer. If the thickness of the inorganic insulator layer and the organic insulator layer are increased, the effect of suppressing the leakage current is improved. However, in the case of the inorganic insulator layer, the durability, ductility, and heat resistance required to buffer stress, Elasticity and the like are insufficient as compared with the organic insulator layer, the inorganic insulator layer can be thick enough to secondarily lower the leakage current, and the thickness of the organic insulator layer can be made thick. In addition, stress due to heat and pressure generated during packaging of the light emitting diode is generally applied from the upper portion of the light emitting diode, so that the organic insulator layer may be formed at the upper end of the lamination structure to effectively relieve stress applied from above. If the thickness of the organic insulator layer is too thick for high leakage current characteristics and stress relaxation, it is difficult to form a high-density interlayer wiring portion and to secure bonding metal step coverage, so that the thickness of the organic insulator layer is 30 mu m Should not exceed.

In addition, the inorganic insulator layer can be made of silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like, which is capable of forming a uniform thin film and facilitating the patterning process, ) And tantalum oxide (Ta ₂ O ₅ ), and the thickness of the inorganic insulator layer can be selected from 0.05 to 0.3 μm.

A part of the n-type electrode 240 and a part of the p-type electrode 230 are exposed on the bottom surface of the n-type electrode 240, Type and p-type bonding metal 260 formed after filling the via hole with a metal material so as to be electrically connected to the p-type electrode 230 and the p-type electrode 230, respectively. The n-type bonding metal 261 is electrically connected to the n-type electrode 240, and the upper surface of the forming layer can be flat. In addition, the reflective electrode may reflect light that is not reflected by the reflective electrode. The p-type bonding metal 262 is electrically connected to the p-type electrode 230 and allows the top surface of the forming layer to be flat. In addition, like the n-type electrode 240, it can also function to reflect light leaking without being reflected by the reflective electrode.

The light emitting diode 100 according to the embodiment of the present invention may be bonded to the submount by flip-chip bonding to be packaged. The submount includes a submount substrate, first and second bonding layers formed on the submount substrate so as to correspond to n-type and p-type electrodes of the light emitting diode 100, and first and second bonding layers And may include first and second solder formed respectively. The submount substrate may be a substrate made of silicon or an oxide film capable of forming a nitride film, and the first and second bonding layers are excellent in electrical conductivity and have adhesiveness to the first and second solders It can be made of good metal. The first and second bonding layers may be formed of any one of Au, Ti, Pt, and Cr, or at least two or more alloys (e.g., Cr / Au, Ti / Pt / Au, 1 and the second solder are for bonding the n-type and p-type electrodes of the light emitting diode 100 to the first and second bonding layers and may be made of an alloy excellent in melting and thermal conductivity, (For example, Au / Sn, Pt / Au / Sn, Cr / Au / Sn, etc.) of Pt, Au, Mo and Sn. Further, the sub-mount may further include a barrier formed on the submount substrate so as to be positioned between the first and second solder for enhancing the bonding force with the LED 100, but the shape is not particularly limited . In addition, the flip chip bonding may apply heat to the submount substrate, apply pressure to the substrate toward the LED 100, and bond the LED 100 and the submount substrate with energy generated by heat and pressure , The ultrasonic wave may be added to the thermocompression bonding to quickly process the process, and the method is not limited thereto.

FIG. 3 is a cross-sectional view showing a step of a method of manufacturing a light emitting diode according to another embodiment of the present invention. FIG. 3 (a) is a sectional view showing a step of forming a semiconductor laminated structure on a substrate, A step of forming a p-type electrode and an n-type electrode on the semiconductor layer and the n-type semiconductor layer, respectively, and Fig. 3C is a sectional view showing a step of forming an interlayer insulating layer and forming a via hole in the interlayer insulating layer And FIG. 3 (d) is a cross-sectional view showing a step of forming an n-type bonding metal on the exposed surface of the n-type electrode.

3, a method of fabricating a light emitting diode according to another embodiment of the present invention includes sequentially stacking an n-type semiconductor layer 321, an active layer 322, and a p-type semiconductor layer 323 on a substrate 310 , Partially etching the active layer (322) and the p-type semiconductor layer (323) to expose a part of the n-type semiconductor layer (321) Type electrode 330 and the n-type electrode 340 on the exposed n-type semiconductor layer 323 and the exposed n-type semiconductor layer 321, forming the p-type electrode 330 and the n-type electrode 340 on the exposed p- Forming an interlayer insulating layer 350 including an organic insulator layer made of an organic material and exposing a portion of the p-type electrode 330 and the n-type electrode 340, Type electrode 330 and the exposed surface of the n-type electrode 340. The p-type electrode 330 and the n- It may include the step of forming the n-type bonding metal (360).

The p-type electrode 330 can be formed as a reflective electrode using a metal having high reflectivity such as Ag, Al, Au, Cr, Ir, Mg, Nd, Ni, Pd, Pt, Rh, Ti, The reflective electrode reflects light emitted from the active layer in a direction opposite to the substrate, toward the substrate. The detailed description of the p-type electrode 330 is the same as that of the light emitting diode according to another embodiment of the present invention.

In the method of manufacturing a light emitting diode according to another embodiment of the present invention, the step of forming a via hole 370 in the interlayer insulating layer 350 to form an interlayer wiring layer in the interlayer insulating layer may include forming an interlayer insulating layer 350 ) Is formed using a photosensitive organic material (for example, polyimide) or a case where a non-photosensitive organic material (for example, polyimide) is used.

In one embodiment, when the organic insulator layer of the interlayer insulating layer 350 is formed using a photosensitive polyimide, the polyimide may be cured by spin coating, The intermediate layer is patterned by a photolithography method, and a via hole 370 formed by patterning is filled with a metal material to form an interlayer wiring portion. The photolithography method uses the photosensitive property of an organic material. The photolithography method selectively exposes and exposes a radiation such as visible light, ultraviolet light, X-ray, e-beam, etc., and then exposes the exposed portion of the photosensitive polyimide layer to a developing solution, The via hole can be formed by dissolving and patterning the exposed portion while leaving the exposed portion. When the organic insulator layer of the interlayer insulating layer 350 is formed using photosensitive polyimide, an etching mask and a complicated etching process are not needed, which is advantageous in that the process cost and process time can be reduced.

In another embodiment, in the case where an organic insulator layer is formed using a non-photosensitive polyimide, the polyimide spin coating process is the same as the case where the organic insulator layer is formed using the photosensitive polyimide described above, Thereafter, the organic insulator layer is etched by using an etch mask having a pattern formed on the polyimide layer, and a metal material is filled in the via hole 370 formed by etching to form an interlayer wiring portion. Then, a bonding metal 360 is formed on the interlayer wiring portion . When the photoresist film is used as a mask, the etching mask is etched using a chemical solution along a pattern formed on the photoresist film, and finally, a photoresist Should be removed.

The interlayer insulating layer 350 may be formed as a single layer of the organic insulator layer, or may include an inorganic insulator layer, and may have a laminated structure of an inorganic insulator layer and the organic insulator layer. In this case, the method may further include forming an inorganic insulator layer (e.g., SiO ₂ layer) by physical vapor deposition and chemical vapor deposition before forming the organic insulator layer. The thickness of the inorganic insulator layer may be smaller than the thickness of the organic insulator layer. The detailed description of the interlayer insulating layer 350 is the same as that of the light emitting diode according to another embodiment of the present invention.

In addition, a method of manufacturing a light emitting diode according to another embodiment of the present invention may further include bonding a light emitting diode manufactured by the method of the present invention to a submount by a flip chip bonding method. In the flip chip bonding method, a heat is applied to the submount substrate, a pressure is applied to the substrate side of the light emitting diode manufactured by the manufacturing method of the light emitting diode, and the light emitting diode and the submount substrate are bonded to each other by energy generated by heat and pressure. , The ultrasonic wave may be added to the thermocompression bonding to quickly process the process, and the method is not limited thereto. The detailed description including the submount is the same as that of the light emitting diode according to another embodiment of the present invention.

The term " on " used in the above description includes a case of being formed in an upper part although not in direct contact with the case of forming by direct contact, and it may be formed partially or entirely on the entire upper surface And it is used in the sense that it is on the upper side of the position or in direct contact with the upper surface.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limited to the embodiments set forth herein. Those skilled in the art will appreciate that various modifications and equivalent embodiments may be possible. Accordingly, the technical scope of the present invention should be defined by the following claims.

100: light emitting diode 210, 310:
220, 320: semiconductor laminated structure 221, 321: n-type semiconductor layer
222, 322: active layer 223, 323: p-type semiconductor layer
230, 330: p-type electrode 240, 340: n-type electrode
250, 350: interlayer insulating layer 260, 360: bonding metal
261: n-type bonding metal 262: p-type bonding metal
370: Via hole

Claims (14)

Board;
A semiconductor stacked structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked on the substrate;
A p-type electrode and an n-type electrode respectively connected to the p-type semiconductor layer and the n-type semiconductor layer;
An interlayer insulating layer provided on the p-type electrode and the n-type electrode, the interlayer insulating layer including an organic insulator layer made of an organic material; And
And a p-type and n-type bonding metal provided to be electrically connected to the p-type electrode and the n-type electrode, respectively.
The method according to claim 1,
And the p-type electrode is a reflective electrode forming a reflective surface.
The method according to claim 1,
The organic material may be at least one selected from the group consisting of polyimide, polycarbonate, polyamide, polyethyleneterephthalate, poly-4-vinylphenol (PVP), polyethersulfone diode.
The method according to claim 1,
Wherein the interlayer insulating layer further comprises an inorganic insulator layer and is formed by a laminated structure of the organic insulator layer and the inorganic insulator layer.
The method of claim 4,
Wherein the inorganic insulator layer comprises at least one of silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), and tantalum oxide (Ta ₂ O ₅ ).
The method of claim 4,
Wherein the thickness of the inorganic insulator layer is thinner than the thickness of the organic insulator layer.
A light emitting diode package, wherein the light emitting diode of any one of claims 1 to 6 is bonded to a submount by flip chip bonding.
Forming an n-type semiconductor layer, an active layer and a p-type semiconductor layer sequentially on a substrate to form a semiconductor laminated structure;
Partially etching the active layer and the p-type semiconductor layer such that a part of the n-type semiconductor layer is exposed;
Forming a p-type electrode and an n-type electrode on the p-type semiconductor layer and the exposed n-type semiconductor layer, respectively;
Forming an interlayer insulating layer on the p-type electrode and the n-type electrode, the interlayer insulating layer including an organic insulator layer made of an organic material;
Forming a via hole in the interlayer insulating layer such that a part of the p-type electrode and the n-type electrode are exposed, respectively; And
And forming p-type and n-type bonding metals to be electrically connected to the exposed surfaces of the p-type electrode and the n-type electrode, respectively.
The method of claim 8,
And the p-type electrode is a reflective electrode forming a reflective surface.
The method of claim 8,
The step of forming the via-
Wherein when the organic material is a photosensitive material, the interlayer insulating layer is patterned by a photolithography method to form a via hole.
The method of claim 8,
The step of forming the via-
Wherein when the organic material is a non-photosensitive material, the interlayer insulating layer is etched using an etching mask to form a via hole.
The method of claim 8,
Wherein the interlayer insulating layer further includes an inorganic insulator layer, and the organic insulator layer and the inorganic insulator layer are stacked.
The method of claim 12,
Wherein the thickness of the inorganic insulator layer is smaller than the thickness of the organic insulator layer.
The method of manufacturing a light emitting diode package according to any one of claims 8 to 13, further comprising the step of bonding a light emitting diode manufactured by the manufacturing method according to any one of claims 8 to 13 to a submount by a flip chip bonding method.

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