KR20150132242A - 컨텍스트―종속 명령들을 위한 성능의 최적화 - Google Patents

컨텍스트―종속 명령들을 위한 성능의 최적화 Download PDF

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Publication number
KR20150132242A
KR20150132242A KR1020157027770A KR20157027770A KR20150132242A KR 20150132242 A KR20150132242 A KR 20150132242A KR 1020157027770 A KR1020157027770 A KR 1020157027770A KR 20157027770 A KR20157027770 A KR 20157027770A KR 20150132242 A KR20150132242 A KR 20150132242A
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South Korea
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instruction
entry
command
current value
value
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KR1020157027770A
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Korean (ko)
Inventor
다렌 유진 스트리트
브라이언 마이클 스템펠
토마스 필립 스피어
로드니 웨인 스미스
마이클 스코트 맥클베인
케네스 알렌 독서
제임스 노리스 다이펜더퍼
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퀄컴 인코포레이티드
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Publication of KR20150132242A publication Critical patent/KR20150132242A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
KR1020157027770A 2013-03-15 2014-03-14 컨텍스트―종속 명령들을 위한 성능의 최적화 Withdrawn KR20150132242A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/841,576 2013-03-15
US13/841,576 US9823929B2 (en) 2013-03-15 2013-03-15 Optimizing performance for context-dependent instructions
PCT/US2014/029876 WO2014145160A1 (en) 2013-03-15 2014-03-14 Optimizing performance for context-dependent instructions

Publications (1)

Publication Number Publication Date
KR20150132242A true KR20150132242A (ko) 2015-11-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157027770A Withdrawn KR20150132242A (ko) 2013-03-15 2014-03-14 컨텍스트―종속 명령들을 위한 성능의 최적화

Country Status (6)

Country Link
US (1) US9823929B2 (enExample)
EP (1) EP2972790A1 (enExample)
JP (1) JP2016512908A (enExample)
KR (1) KR20150132242A (enExample)
CN (1) CN105190540B (enExample)
WO (1) WO2014145160A1 (enExample)

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US9348589B2 (en) 2013-03-19 2016-05-24 Apple Inc. Enhanced predicate registers having predicates corresponding to element widths
US9817663B2 (en) 2013-03-19 2017-11-14 Apple Inc. Enhanced Macroscalar predicate operations
US10684859B2 (en) * 2016-09-19 2020-06-16 Qualcomm Incorporated Providing memory dependence prediction in block-atomic dataflow architectures
US10592246B2 (en) * 2017-07-12 2020-03-17 International Business Machines Corporation Low latency execution of floating-point record form instructions
US10360036B2 (en) 2017-07-12 2019-07-23 International Business Machines Corporation Cracked execution of move-to-FPSCR instructions
US11068612B2 (en) 2018-08-01 2021-07-20 International Business Machines Corporation Microarchitectural techniques to mitigate cache-based data security vulnerabilities
US11868777B2 (en) 2020-12-16 2024-01-09 Advanced Micro Devices, Inc. Processor-guided execution of offloaded instructions using fixed function operations
US12073251B2 (en) * 2020-12-29 2024-08-27 Advanced Micro Devices, Inc. Offloading computations from a processor to remote execution logic
US12197378B2 (en) 2022-06-01 2025-01-14 Advanced Micro Devices, Inc. Method and apparatus to expedite system services using processing-in-memory (PIM)
US12050531B2 (en) 2022-09-26 2024-07-30 Advanced Micro Devices, Inc. Data compression and decompression for processing in memory
US12147338B2 (en) 2022-12-27 2024-11-19 Advanced Micro Devices, Inc. Leveraging processing in memory registers as victim buffers
US12265470B1 (en) 2023-09-29 2025-04-01 Advanced Micro Devices, Inc. Bypassing cache directory lookups for processing-in-memory instructions
US12455826B2 (en) 2024-03-29 2025-10-28 Advanced Micro Devices, Inc. Dynamic caching policies for processing-in-memory

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
DE69425311T2 (de) 1993-10-18 2001-03-15 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Mikroprozessor mit spekulativer Befehlsausführung
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US5854921A (en) 1995-08-31 1998-12-29 Advanced Micro Devices, Inc. Stride-based data address prediction structure
US6405305B1 (en) 1999-09-10 2002-06-11 Advanced Micro Devices, Inc. Rapid execution of floating point load control word instructions
US6983358B2 (en) * 2001-10-23 2006-01-03 Ip-First, Llc Method and apparatus for maintaining status coherency between queue-separated functional units
US7093111B2 (en) 2003-07-31 2006-08-15 International Business Machines Corporation Recovery of global history vector in the event of a non-branch flush
US7249243B2 (en) * 2003-08-06 2007-07-24 Intel Corporation Control word prediction and varying recovery upon comparing actual to set of stored words
US7500087B2 (en) 2004-03-09 2009-03-03 Intel Corporation Synchronization of parallel processes using speculative execution of synchronization instructions
JP5326374B2 (ja) * 2008-06-19 2013-10-30 富士通セミコンダクター株式会社 プロセッサ、性能プロファイリング装置、性能プロファイリングプログラムおよび性能プロファイリング方法
US8880854B2 (en) 2009-02-11 2014-11-04 Via Technologies, Inc. Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register
JP5526626B2 (ja) * 2009-06-30 2014-06-18 富士通株式会社 演算処理装置およびアドレス変換方法
US20110047358A1 (en) 2009-08-19 2011-02-24 International Business Machines Corporation In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication
US8819397B2 (en) 2011-03-01 2014-08-26 Advanced Micro Devices, Inc. Processor with increased efficiency via control word prediction

Also Published As

Publication number Publication date
CN105190540A (zh) 2015-12-23
EP2972790A1 (en) 2016-01-20
US9823929B2 (en) 2017-11-21
WO2014145160A1 (en) 2014-09-18
JP2016512908A (ja) 2016-05-09
US20140281405A1 (en) 2014-09-18
CN105190540B (zh) 2018-04-03

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PA0105 International application

Patent event date: 20151006

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid