CN105190540B - 优化用于上下文相关指令的性能 - Google Patents

优化用于上下文相关指令的性能 Download PDF

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Publication number
CN105190540B
CN105190540B CN201480013934.7A CN201480013934A CN105190540B CN 105190540 B CN105190540 B CN 105190540B CN 201480013934 A CN201480013934 A CN 201480013934A CN 105190540 B CN105190540 B CN 105190540B
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CN
China
Prior art keywords
instruction
entry
value
current value
processor
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Expired - Fee Related
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CN201480013934.7A
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English (en)
Chinese (zh)
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CN105190540A (zh
Inventor
达朗·尤金·施特雷特
布莱恩·迈克尔·斯坦普尔
托马斯·菲利普·施派尔
罗德尼·韦恩·史密斯
迈克尔·斯科特·麦克勒瓦伊内
肯尼思·艾伦·达克塞
詹姆斯·诺里斯·迪芬德尔费尔
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN105190540A publication Critical patent/CN105190540A/zh
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Publication of CN105190540B publication Critical patent/CN105190540B/zh
Expired - Fee Related legal-status Critical Current
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
CN201480013934.7A 2013-03-15 2014-03-14 优化用于上下文相关指令的性能 Expired - Fee Related CN105190540B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/841,576 2013-03-15
US13/841,576 US9823929B2 (en) 2013-03-15 2013-03-15 Optimizing performance for context-dependent instructions
PCT/US2014/029876 WO2014145160A1 (en) 2013-03-15 2014-03-14 Optimizing performance for context-dependent instructions

Publications (2)

Publication Number Publication Date
CN105190540A CN105190540A (zh) 2015-12-23
CN105190540B true CN105190540B (zh) 2018-04-03

Family

ID=50629006

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480013934.7A Expired - Fee Related CN105190540B (zh) 2013-03-15 2014-03-14 优化用于上下文相关指令的性能

Country Status (6)

Country Link
US (1) US9823929B2 (enExample)
EP (1) EP2972790A1 (enExample)
JP (1) JP2016512908A (enExample)
KR (1) KR20150132242A (enExample)
CN (1) CN105190540B (enExample)
WO (1) WO2014145160A1 (enExample)

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US9298456B2 (en) * 2012-08-21 2016-03-29 Apple Inc. Mechanism for performing speculative predicated instructions
US9817663B2 (en) 2013-03-19 2017-11-14 Apple Inc. Enhanced Macroscalar predicate operations
US9348589B2 (en) 2013-03-19 2016-05-24 Apple Inc. Enhanced predicate registers having predicates corresponding to element widths
US10684859B2 (en) * 2016-09-19 2020-06-16 Qualcomm Incorporated Providing memory dependence prediction in block-atomic dataflow architectures
US10592246B2 (en) 2017-07-12 2020-03-17 International Business Machines Corporation Low latency execution of floating-point record form instructions
US10360036B2 (en) 2017-07-12 2019-07-23 International Business Machines Corporation Cracked execution of move-to-FPSCR instructions
US11068612B2 (en) 2018-08-01 2021-07-20 International Business Machines Corporation Microarchitectural techniques to mitigate cache-based data security vulnerabilities
US11868777B2 (en) 2020-12-16 2024-01-09 Advanced Micro Devices, Inc. Processor-guided execution of offloaded instructions using fixed function operations
US12073251B2 (en) * 2020-12-29 2024-08-27 Advanced Micro Devices, Inc. Offloading computations from a processor to remote execution logic
US11625249B2 (en) 2020-12-29 2023-04-11 Advanced Micro Devices, Inc. Preserving memory ordering between offloaded instructions and non-offloaded instructions
US12498969B2 (en) * 2022-04-21 2025-12-16 Microsoft Technology Licensing, Llc. Distributed, decentralized traffic control for worker processes in limited-coordination environments
US12197378B2 (en) 2022-06-01 2025-01-14 Advanced Micro Devices, Inc. Method and apparatus to expedite system services using processing-in-memory (PIM)
US12050531B2 (en) 2022-09-26 2024-07-30 Advanced Micro Devices, Inc. Data compression and decompression for processing in memory
US12147338B2 (en) 2022-12-27 2024-11-19 Advanced Micro Devices, Inc. Leveraging processing in memory registers as victim buffers
US12265470B1 (en) 2023-09-29 2025-04-01 Advanced Micro Devices, Inc. Bypassing cache directory lookups for processing-in-memory instructions
US12455826B2 (en) 2024-03-29 2025-10-28 Advanced Micro Devices, Inc. Dynamic caching policies for processing-in-memory

Citations (3)

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US20090158012A1 (en) * 1995-08-16 2009-06-18 Microunity Systems Engineering, Inc. Method and Apparatus for Performing Improved Group Instructions
CN101776989A (zh) * 2009-02-11 2010-07-14 威盛电子股份有限公司 乱序执行微处理器及提升效能的方法、执行方法
US20120226891A1 (en) * 2011-03-01 2012-09-06 Advanced Micro Devices, Inc. Processor with increased efficiency via control word prediction

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EP0649086B1 (en) 1993-10-18 2000-07-19 National Semiconductor Corporation Microprocessor with speculative execution
US5854921A (en) 1995-08-31 1998-12-29 Advanced Micro Devices, Inc. Stride-based data address prediction structure
US6405305B1 (en) 1999-09-10 2002-06-11 Advanced Micro Devices, Inc. Rapid execution of floating point load control word instructions
US6983358B2 (en) * 2001-10-23 2006-01-03 Ip-First, Llc Method and apparatus for maintaining status coherency between queue-separated functional units
US7093111B2 (en) 2003-07-31 2006-08-15 International Business Machines Corporation Recovery of global history vector in the event of a non-branch flush
US7249243B2 (en) * 2003-08-06 2007-07-24 Intel Corporation Control word prediction and varying recovery upon comparing actual to set of stored words
US7500087B2 (en) 2004-03-09 2009-03-03 Intel Corporation Synchronization of parallel processes using speculative execution of synchronization instructions
JP5326374B2 (ja) * 2008-06-19 2013-10-30 富士通セミコンダクター株式会社 プロセッサ、性能プロファイリング装置、性能プロファイリングプログラムおよび性能プロファイリング方法
JP5526626B2 (ja) * 2009-06-30 2014-06-18 富士通株式会社 演算処理装置およびアドレス変換方法
US20110047358A1 (en) 2009-08-19 2011-02-24 International Business Machines Corporation In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090158012A1 (en) * 1995-08-16 2009-06-18 Microunity Systems Engineering, Inc. Method and Apparatus for Performing Improved Group Instructions
CN101776989A (zh) * 2009-02-11 2010-07-14 威盛电子股份有限公司 乱序执行微处理器及提升效能的方法、执行方法
US20120226891A1 (en) * 2011-03-01 2012-09-06 Advanced Micro Devices, Inc. Processor with increased efficiency via control word prediction

Also Published As

Publication number Publication date
CN105190540A (zh) 2015-12-23
KR20150132242A (ko) 2015-11-25
WO2014145160A1 (en) 2014-09-18
US20140281405A1 (en) 2014-09-18
EP2972790A1 (en) 2016-01-20
JP2016512908A (ja) 2016-05-09
US9823929B2 (en) 2017-11-21

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Granted publication date: 20180403