KR20150130331A - Light emitting diode semiconductor structures having active regions comprising ingan - Google Patents

Abstract

The semiconductor structure includes an active region between the layers of a plurality of InGaN. The active region may be composed of at least substantially InGaN. The plurality of layers of InGaN comprises at least one well layer comprising In _w Ga _{1 - w} N, and at least one barrier layer comprising In _b Ga _{1 - b} N near at least one well layer. In some embodiments, the value of w in the well layer In _w Ga _1-w N is about 0.10 or more, or some embodiments In about 0.40 can be up to, at least one of In _b Ga of the barrier layer ₁ in the _{- b} The value of _{b in} N may be greater than or equal to about 0.01 and less than or equal to about 0.10. A method of forming a semiconductor structure includes growing such a layer of InGaN to form an active region of a light emitting device, e.g., an LED. The luminous device includes such an LED.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode (LED) semiconductor structure having an active region including an INGAN (Light Emitting Diode SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN)

The present disclosure relates to a light emitting device manufactured from such a semiconductor structure having a semiconductor structure and an active region including InGaN, a method of manufacturing such a light emitting device, and an apparatus including such a light emitting device.

Light emitting devices, such as light emitting diodes (LEDs), are electronic devices that emit electromagnetic radiation in the form of visible light when a voltage is applied across the active area of the LED between the anode and cathode. The LED typically comprises one or more layers of semiconductor material in which the electrons supplied from the anode and the holes supplied from the cathode recombine. Because electrons and holes recombine within the active region of the LED, energy is emitted in the form of photons emitted from the active region of the LED.

LEDs may be fabricated to include a wide variety of semiconductor materials, including, for example, III-V semiconductor materials, and II-V semiconductor materials. The wavelength of light emitted from any particular LED is a function of the amount of energy emitted when electrons and holes recombine. Thus, the wavelength of light emitted from the LED is a function of the relative difference in energy between the energy level of the electrons and the energy level of the holes. The energy level of electrons and the energy level of holes are at least partially related to the composition of the semiconductor material, the doping form and concentration of the semiconductor material, the recombination (i. E., Crystal structure and orientation), and the quality of the semiconductor material to be. Thus, the wavelength of the light emitted from the LED can be selectively adjusted by selectively adjusting the composition and configuration of the semiconductor material in the LED.

It is known in the art to fabricate LEDs comprising III-V semiconductor materials, such as Group III nitride materials. Such Group III nitride LEDs are known to emit radiation in the blue and green visible regions of the electromagnetic radiation spectrum and are known to be capable of operating at relatively high power and luminosity.

This summary is provided to introduce the selection of concepts in a simplified form. This concept is described in greater detail in the detailed description of exemplary embodiments of the disclosure below. This summary is not intended to identify key features or basic features of the claimed subject matter and is not intended to be used to limit the scope of the claimed subject matter.

In some embodiments, the present disclosure is an active that is placed on top of the base layer, the base layer areas, an electron blocking layer, a p- type In _p Ga _{1 - p} N bulk layer, and the p- type In _c Ga _{1 - c} N contact Layer. ≪ / RTI > The active region comprises a plurality of layers of InGaN comprising at least one well layer comprising In _w Ga _{1 - w} N and at least one barrier layer comprising In _b Ga _{1 - b} N, w is 0.10? w? 0.40, and b is 0.01? b? The electron blocking layer is disposed over the active region opposite to the base layer. The electron blocking layer comprises In _e Ga _{1- e} N, wherein e is 0.00? E? 0.02. The p-type In _p Ga _{1 - p} N bulk layer is disposed on the electron blocking layer, and _p in the In _p Ga _{1 - p} N bulk layer is 0.01? p? The p-type In _c Ga _{1 - c} N contact layer is disposed on the _p -type In _p Ga _{1 - p} N bulk layer and _c in the In _c Ga _{1 - c} N contact layer is 0.00? c?

In a further embodiment, the present disclosure includes a light emitting device fabricated from such a semiconductor structure.

For example, in some embodiments, the present disclosure provides a semiconductor device comprising a base layer, an active region disposed over the base layer, an electron blocking layer disposed over the active region, a p-type In _p Ga _{1 - p} N And a p-type In _c Ga _{1 - c} N contact layer disposed on the p-type In _p Ga _{1 - p} N bulk layer. The active region includes at least one InGaN well layer and a plurality of layers of InGaN comprising at least one InGaN barrier layer disposed directly on the at least one well layer. The critical strain energy of the light emitting device may be about 1800 or less.

In a further embodiment, the present disclosure provides a method of manufacturing a semiconductor device comprising the steps of providing a base layer, growing a layer of InGaN to form an active region on the base layer, growing an electron blocking layer on the active region opposite the base layer , And growing a p-type In _c Ga _{1 - c} N contact layer on the _p -type In _p Ga _1-p N bulk layer, wherein c is a semiconductor structure with 0.00? C? Lt; / RTI > Growing a layer of a plurality of InGaN layers includes growing at least one In _w Ga _{1 - w} N well layer and growing at least one In _b Ga _{1 - b} N barrier layer, , w is 0.10? w? 0.40, and b is 0.01? b?

In yet another embodiment, the present disclosure includes a container that is at least substantially transparent to the visible wavelength of electromagnetic radiation, and luminary devices that include one or more LEDs as described herein in a container. For example, an LED in a container may include an anode contact, a cathode contact, and an active area between the anode contact and the cathode contact. The active region includes a plurality of layers of InGaN, and in some embodiments may be composed at least substantially of InGaN. The plurality of layers of InGaN comprise at least one well layer comprising In _w Ga _{1 - w} N and at least one barrier layer comprising In _b Ga _{1 - b} N near at least one well layer, , W is 0.05? W? 0.25, and b is 0.01? B?

1A is a simplified side view of a semiconductor structure including at least one InGaN well layer and at least one InGaN barrier layer in an active region of a semiconductor structure according to an embodiment of the present disclosure;
1B is a simplified diagram illustrating the relative difference in the energy levels of the conduction band in the energy band diagram for the various materials of the various layers of the semiconductor structure of FIG. 1A.
FIG. 2A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A but further including an electron stopping layer between the base layer and the active region of the semiconductor structure.
Figure 2b is a simplified conduction diagram for the semiconductor structure of Figure 2a.
FIG. 3A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A but further including a strain relief layer between the base layer and the active region of the semiconductor structure.
Figure 3b is a simplified conduction diagram for the semiconductor structure of Figure 3a.
4A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A but further including an additional thin GaN barrier layer within the active region of the semiconductor structure.
Figure 4b is a simplified conduction diagram for the semiconductor structure of Figure 4a.
5A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A but further including a well overflow structure within the active region of the semiconductor structure.
Figure 5b is a simplified conduction diagram for the semiconductor structure of Figure 5a.
6A is a simplified top view of an intermediate semiconductor structure that may be employed to fabricate a growth template used in the fabrication of a semiconductor structure in accordance with an embodiment of the method of the present disclosure.
Figure 6B is a partial side cross-sectional view of the intermediate semiconductor structure of Figure 6A.
6C is a partial side cross-sectional view of a growth template that may be employed to fabricate a semiconductor structure in accordance with an embodiment of the method of the present disclosure.
Figure 6d shows a layer of a growth stack epitaxially deposited on a growth template.
7 is a partial side cross-sectional view of a light emitting device fabricated in a semiconductor structure according to an embodiment of the method of the present disclosure;
8 is a partial side cross-sectional view of an additional light emitting device fabricated from a semiconductor structure according to an embodiment of the method of the present disclosure;
9 is a graph illustrating the relationship between total strain energy and internal quantum efficiency of a semiconductor structure formed in accordance with an embodiment of the method of the present disclosure;
10A is a simplified side view of an already known LED comprising an InGaN well layer and a GaN barrier layer in the active region of the LED.
Figure 10B is a simplified conduction diagram for the LED of Figure 10A.
11A is a graph showing a calculated band edge for a valence band and a conduction band due to a zero applied voltage across the active region of the LED of FIG. 10A, and the calculation is obtained using a calculation model of the LED.
11B is a graph similar to that of Fig. 11A, but showing the calculated band edge for the valence band and conduction band with a current density of 125 A / cm < ² > flowing across the active region of the LED due to the applied voltage of the active region .
11C is a graph showing the calculated intensity of emission radiation as a function of wavelength for each InGaN quantum well layer in the LED of FIG. 11A.
11D is a graph showing the calculated carrier injection efficiency as a function of the current density applied over the active region of the LED of FIG. 11A.
12A is a simplified side view of the LED of this disclosure, which is similar to that of FIG. 1A and includes an InGaN well layer and an InGaN barrier layer in the active region of the LED.
Figure 12B is a simplified conduction diagram of the LED of Figure 12A.
13A is a graph showing calculated band edges for a valence band and a conduction band having a zero applied voltage across the active region of the LED of FIG. 12A, and the calculation is obtained using a calculation model of the LED.
13B is a graph similar to FIG. 13A, but showing a calculated band edge for a valence band and a conduction band with a current density of 125 A / cm < ² > flowing across the active area of the LED due to the applied voltage across the active area .
13C is a graph showing the calculated intensity of emission radiation as a function of wavelength for each InGaN quantum well layer in the LED of Fig. 13A. Fig.
13D is a graph illustrating the calculated carrier injection efficiency as a function of the applied current density over the active region of the LED of FIG. 13A.
13E is a graph showing the internal quantum efficiency calculated as a function of the calculated current density over the active area of the LED of FIG. 13A.
14 shows an example of a light emitting device including the LED of the present disclosure.

The examples provided herein are not intended to be taken to be an actual illustration of any particular semiconductor material, structure, or device, but merely to describe an embodiment of the disclosure.

IA illustrates an embodiment of a semiconductor structure 100. FIG. The semiconductor structure 100 includes a plurality of group III nitride layers (e.g., indium nitride, gallium nitride, aluminum nitride, and alloys thereof) and is comprised of a base layer 102 an active region 106 disposed between the p-type contact layer 104 and the base layer 102 and the p-type contact layer 104, an active region 106 comprising a plurality of layers of InGaN, ). In addition, the active region 106 includes at least one InGaN well layer and at least one InGaN barrier layer. In some embodiments, the active region 106 (at least in the absence of a dopant) may be composed at least substantially of InGaN. The semiconductor structure 100 includes an electron blocking layer 108 disposed on the active region 106, a p-type bulk layer 110 disposed on the electron blocking layer 108, and p -Type contact layer 104 disposed over the p-type bulk layer 110. The p-

Base layer 102 is optional In _n Ga _{1 - n} N base layer may comprise 112 At this time, In _n Ga _{1 -} growth plane (growth plane) of the _n N base layer 112, Is a polar plane with a growth plane lattice parameter greater than about 3.186 angstroms. A light emitting device, such as a light emitting diode, may be fabricated from the semiconductor structure 100, as described in detail herein below. In brief, however, a first electrode contact may be formed over a portion of the In _n Ga _{1 -n} N base layer 112 and a second electrode contact may be formed over a portion of the p-type contact layer 104 So that an electrical voltage can be applied across the active region 106 between the electrode contacts whereby electromagnetic radiation (e.g., visible light) is emitted from the semiconductor structure 100 To be released from the device.

An embodiment of the semiconductor structure of the present disclosure, including an active region comprising at least one InGaN well layer and at least one InGaN barrier layer, may be formed by various types of methods for growing or forming a Group III nitride layer such as InGaN . ≪ / RTI > As a non-limiting example, several Group III nitride layers may be formed by chemical vapor deposition (CVD) processes, metalorganic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE) (ALD) process, a hydride vapor phase epitaxy (HVPE) process, a molecular beam epitaxy (MBE) process, an atomic layer deposition (ALD) process, ) Process, a chemical beam epitaxy (CBE) process, or the like.

In some embodiments, in the name of Letertre et al., U.S. Patent Application Publication No. US 2010/0176490 A1, published July 15, 2010, U.S. Patent Application, published May 6, 2010 under the name of Arena U.S. Patent Application Publication No. US 2012/0211870, published on Aug. 23, 2012, and U.S. Pat. No. 6,131,123, issued on September 6, 2012, in the name of Figuet, The method disclosed in one or both of the application serial number US 2012/0225539 can be used to grow or otherwise deposit multiple layers of Group III nitride. Such a method may enable the fabrication of a Group III nitride layer, such as an InGaN layer (and other optional Group III nitride layers) having the composition and thickness described below. Such a method can then be used to form a growth template 113 from which a Group III nitride layer can be formed.

An example of such a method that can be used to fabricate a growth template 113, such as that shown in Fig. 1A, in accordance with an embodiment of the present disclosure is briefly described.

The semiconductor structure 100 of FIG. 1A includes a plurality of layers of Group III nitride formed over the growth template 113. In some embodiments, the growth template 113 includes a growth substrate 658 and a GaN seed layer 656 disposed over the growth substrate 658, wherein the growth of the GaN seed layer Planes include polar planes. The growth template 113 may further include a Group III nitride nucleation layer 660 disposed between the growth substrate 658 and the GaN seed layer 656.

Growth substrate 658 may include a homogenous material (homogenous material) or heterologous (i. E., Multiple) materials (heterogeneous (ie, composite) material). As a non-limiting example, the growth substrate 658 may be formed of a material selected from the group consisting of sapphire, silicon, group III-arsenides, quartz, SiO ₂ , fused silica (SiO ₂ ) (E.g., sold under the trademark ZERODUR® by Schott North America, Inc. of Duryea, PA), fused silica glass composites (eg, SiO ₂ -TiO ₂ or Cu ₂ -Al ₂ O ₃ -SiO ₂ , aluminum nitride (AlN), or silicon carbide (SiC). In some embodiments, the growth substrate includes a c-plane sapphire, wherein the growth plane 659 of the sapphire includes a c-plane.

The Group III nitride nucleation layer 660 may be formed by a deposition method and process as known in the art such as a chemical vapor deposition (CVD) process, a metalorganic chemical vapor deposition (MOCVD) process, A vapor phase epitaxy (VPE) process, an atomic layer deposition (ALD) process, a hydride vapor phase epitaxy (HVPE) process, a molecular beam epitaxy (MBE) process , An atomic layer deposition (ALD) process, a chemical beam epitaxy (CBE) process, or the like.

Group III nitride nucleation layer 660 may comprise, for example, aluminum nitride (AlN), indium nitride, or gallium nitride. Group III nitride nucleation layer 660 may be formed to have an average layer thickness of less than about 100 nanometers (100 nm), less than about 20 nanometers (25 nanometers), or even less than about 10 nanometers (10 nanometers) . Group III nitride nucleation layer 660 may also include an intentional or unintentional dopant. A Group III nitride nucleation layer 660 may be disposed directly on the growth substrate 658 or between the growth substrate 658 and the GaN seed layer 656. The Group III nitride nucleation layer may be formed, for example, by a chemical vapor deposition process performed at a deposition temperature of about 700 DEG C or less. The Group III nitride generating layer 660 may be annealed at a temperature greater than about 700 ° C to improve the crystalline properties of the Group III nitride nucleation layer 660. For example, (I.e., heated).

The GaN seed layer 656 may be disposed on the growth substrate 658. The growth plane 662 of the GaN seed layer 656 may include polar growth (e.g., gallium polarity or nitrogen polarity) planes. In some embodiments, the growth plane 662 of the GaN seed layer 656 may comprise a gallium polarity growth plane. In another embodiment, the GaN seed layer 656 may be formed, for example, by a deposition process, such that the GaN seed layer 656 is formed in the state of tensile strain. In other words, a GaN seed layer 656 can be formed, and as a result, the crystal lattice at the growth plane 662 substantially matches the crystal lattice of the growth substrate 658. For example, the lattice constant of the growth plane 662 of the GaN seed layer 656 may have an average lattice value, such as about 3.186 Angstroms.

The GaN seed layer 656 may be formed by any suitable deposition method and process known in the art such as a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition process (MOCVD), a vapor phase epitaxy (VPE) process, (ALD) process, a hybrid vapor phase epitaxy (HVPE) process, a molecular beam epitaxy (MBE) process, an atomic layer deposition (ALD) process, a chemical beam epitaxy (CBE) process, and the like. For example, the GaN seed layer 656 may be formed using a chemical vapor deposition process, wherein the deposition process is performed at a temperature below about 1100 ° C.

The GaN seed layer 656 may be formed to have an average layer thickness T s ranging from about 1 micrometer (1 탆) to about 7 micrometers (7 탆). As one specific, non-limiting example, the average layer thickness ( Ts ) may be equal to about 4 micrometers (4 micrometers). The GaN seed layer 656 may also include intentional or unintentional dopants. For example, the GaN seed layer 656 may be doped to an n-type by doping with an element that is an electron donor, such as silicon or germanium. The concentration of the dopant in the GaN seed layer 656 may range from about 3e ¹⁷ cm ^-3 to about 1e ²⁰ cm ^-3 , or from about 5e ¹⁷ cm ^-3 to about 4e ¹⁹ cm ^-3 . The growth rate of the GaN seed layer 656 may be in a range between about 25 nanometers per minute (25 nm / min) and about 50 nanometers per minute (50 nm / min).

The GaN seed layer 656 may be disposed directly on the Group III nitride nucleation layer 660, which is opposite the growth substrate 658. Therefore, a GaN seed layer 656 may be disposed between the nucleation layer 660 and the active region 106.

In a further embodiment, the growth template 113 may have the structure described below with reference to Figs. 6A-6C and may be formed using a method such as described further below.

6A is a top view of an intermediate semiconductor structure 650 used to form the growth template 113 (FIG. 6C) from which one or more semiconductor structures of the present disclosure and a subsequent light emitting device may be fabricated, and FIG. 6B Sectional view of a portion of an intermediate semiconductor structure 650 used to form the growth template 113. [ The growth template 113 may be fabricated as disclosed in the aforementioned U.S. Patent Application Publication No. US 2010/0176490 A1 and / or U.S. Patent Application Publication No. US 2010/0109126. As disclosed therein, the intermediate semiconductor structure 650 includes a sacrificial substrate 652, a layer of compliant material 654 disposed over the sacrificial substrate 652, And one or more In _s Ga _{1 - s} N seed layers 656. One or more In _s Ga _{1 - s} N seed layer 656 may be used as that can be formed and then the various layers of the semiconductor structure 100 "seed (seed)" described herein.

The initial In _s Ga _{1 -s} N seed layer can be formed on the initial growth substrate, and thereafter the ion implantation, bonding and subsequent isolation of a portion of the initial In _s Ga _{1 -s} N seed layer (not shown) may be transferred to the sacrificial substrate 652 using a method such as separation. Characterized in that it contains the early growth substrate, In _s Ga _1-s N seed layer is stained method (stained manner) to the factory In _s Ga _1-s N seed layer and the growth plane lattice mismatch (growth plane lattice mismatch) to form And a growth substrate. For example, the initial growth substrate may comprise a sapphire substrate comprising a gallium polar GaN seed layer, and the resulting In _s Ga _{1 - s} N seed layer may be strained by gallium polarity In _s Ga _{1 - s} N Seed layer.

The initial In _s Ga _{1 - s} N seed layer may be formed or grown such that the In _s Ga _{1 - s} N seed layer comprises a growth plane comprising the pole planes of group III-nitride. For example, the growth plane may be formed such that the In _s Ga _{1 - s} N seed layer includes a gallium-pole plane. In addition, early In _s Ga _1-s N seed layer In _s Ga _{1 -} may be grown or formed in the composition of the seed layer such that N _s 0.02≤s≤0.05. As one specific non-limiting example, the value at the In _s Ga _{1 - s} N seed layer may be equal to about 0.03. In addition, the In _s Ga _{1 - s} N seed layer can be grown or grown to a thickness of about 200 nanometers (200 nm) or more. However, In _s Ga _{1 - s} N seed layer, In _s Ga _{1 - s} N a variation of the seed layer having a thickness that can be mitigated by the formation of additional defects, In _s Ga _{1 - s} N seed layer, the critical thickness Is formed in such a manner that it does not exceed the In _s Ga _{1 - s} N seed layer. This phenomenon is generally referred to in the art as phase separation. Therefore, the In _s Ga _{1 -s} N seed layer may contain a modified high-quality seed material.

By way of example and as not limiting, as the SMART-CUT process, the process known in the industry, the bonding layer as a sacrificial substrate (652) In _s Ga ₁ using a layer of flexible material (654) _{- s} N seed layer (656 ). ≪ / RTI > Such processes are described, for example, in US Pat. No. RE39,484 to Bruel, US Patent No. 6,303,468 to Aspar et al., US Patent No. 6,335,258 to Aspar et al., 6,756,286 to Moriceau et al., 6,809,044 to Aspar et al. 6,946,365 to Aspar et al.

The sacrificial substrate 652 may comprise a homogeneous material or a heterogeneous (i.e., composite) material. By way of non-limiting example, the support substrate 652 may be formed of a material selected from the group consisting of sapphire, silicon, Group III-abundance, quartz (SiO ₂ ), fused silica (SiO ₂ ) of PA in ®, Schott North America, Inc. sold by) the dureyi (Duryea), fused silica glass composite material (such as, for example, SiO ₂ -TiO ₂ or Cu ₂ -Al ₂ O ₃ -SiO ₂ ), Aluminum nitride (AlN), or silicon carbide (SiC).

The layer of flexible material 654 may comprise, for example, a material having a glass transition temperature (T _g ) of less than or equal to about 800 ° C. The layer of flexible material 654 may have a thickness in the range of about 0.1 占 퐉 to about 10 占 퐉, particularly about 1 占 퐉 to about 5 占 퐉. As a non-limiting example, the layer of the flexible material 100 may be formed of a material selected from the group consisting of oxides, phosphosilicate glass (PSG), borosilicate (BSG), borophosphosilicate glass (BPSG), polyimide polyimide, doped or undoped quasi-inorganic siloxane, spin-on-glass (SOG), inorganic spin-on-glass -, or butyl), and doped or undoped silicates.

The layer of flexible material 654 may be formed by reflowing a layer of flexible material 654, for example, at least one In _s Ga _{1 -s} N seed layer 656 at least partially relaxing the crystal lattice strain For example, in an oven, furnace, or deposition reactor, at a temperature sufficient to reduce the viscosity of the layer of flexible material 654. By reducing the viscosity of the layer of flexible material 654, the tensile strain in the In _s Ga _{1 -s} N seed layer 656 can be at least partially relaxed or even eliminated, To form an In _s Ga _{1 - s} N seed layer 656 containing a growth plane lattice parameter greater than 3.189 Angstroms.

Therefore, by relaxing at least a portion of the lattice strain in In _s Ga _{1 - s} N, the growth plane lattice parameter can be obtained above about 3.189 angstroms in In _s Ga _{1 - s} N. A growth plane lattice parameter of greater than 3.189 Angstroms may correspond to an equilibrium growth plane lattice constant for wurtzite GaN. Therefore, according to some embodiments of the present disclosure, one or more GaN layers formed on or on the In _s Ga-1 _s N layer of the present disclosure may be formed without strain, that is, substantially without lattice strain have.

One or more In _s Ga _{1 - s} N for at least partial relaxation of the seed layer 656, In _s Ga _{1 -s} N seed layer 656 may be transferred onto the support substrate, and then the flexible material (654) And the sacrificial substrate 652 may be removed to form the growth template 113 as shown in Figure 6C. 6B and 6C, the at least partially relaxed In _s Ga _{1 -s} N seed layer 656 can be attached to the support substrate 659 and the sacrificial substrate 652 and the flexible material 654 may be removed using one or more of a method such as laser lift-off, wet etching, dry etching, and chemical mechanical polishing .

The support substrate 659 may comprise a homogeneous material or a heterogeneous (i.e., composite) material. As a non-limiting example, the support substrate 659 is sapphire, silicon, a group III- arsenide, quartz (SiO _2), fused silica (SiO ₂₎ glass, glass-ceramic composites (e.g., for example, a trademark ZERODUR of PA in ®, Schott North America, Inc. sold by) the dureyi (Duryea), fused silica glass composite material (such as, for example, SiO ₂ -TiO ₂ or Cu ₂ -Al ₂ O ₃ -SiO ₂ ), Aluminum nitride (AlN), or silicon carbide (SiC).

6C, in some embodiments, the growth template 113 may optionally include a layer of dielectric material 661 that overlies the support substrate 659. As shown in FIG. Layer of dielectric material 661 is selectively major surface of the supporting substrate (659) (major surface) or one or more of In _s Ga _{1 -} may be formed on _s N seed layer 656, at this time, the dielectric material (661) Is used as a bonding layer to bond the supporting substrate 659 to the supporting substrate 659. The layer of dielectric material 661 may include, for example, silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ), or silicon dioxide (SiO ₂ ) , For example, using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Thus, the growth template 113, the support substrate 659 and the supporting substrate (659) In _s Ga ₁ disposed above as shown in Figure 6c _- comprises N _s seed layer 656.

In addition, In _s Ga _{1 -} a composition 0.02≤s≤0.05 range of N _s seed layer 656 _{- s} N seed layer 656 may be formed on a supporting substrate (659), so that In _s Ga ₁ Can be. As of a particular non-limiting example, In _s Ga _{1 - s s} N value from the seed layer 656 may be as about 0.03. Furthermore, the In _s Ga _{1 - s} N seed layer 656 may have a polar growth plane 662 comprising a growth plane lattice parameter greater than or equal to about 3.189 Angstroms. The In _s Ga _{1 - s} N seed layer may also be formed with a total layer thickness ( T _s ) of about 100 nanometers (100 nm) or more.

The growth template 113 can form a portion of the base layer 102 of FIG. 1A and includes a growth substrate 658, a Group III nitride nucleation layer 660, and a GaN seed layer 656 can do. Base layer 102 is in some embodiments, also optional In _n Ga _{1 -} may include _n N base layer 112, at this time, In _n Ga _{1 - n} N base layer adjacent GaN seed layer The specific crystallinity properties of which are inherited. Therefore, In _n Ga _{1 - n} N base layer 112 also having a growth plane lattice parameter of at least about 3.186 Angstroms, for polarity growth plane, such as may include a gallium polarity growth plane.

The In _n Ga _{1 - n} N base layer 112 may comprise a layer of In _n Ga _{1 - n} N, where n is 0.00? N? 0.10, or 0.02? N? 0.08. As one specific, non-limiting example, the value of n in the In _n Ga _1n N base layer 112 may be equal to about 0.05. In _n Ga _{1 - n} N base layer 112 is about 10 nanometers (10 nm) and about 3000 between nanometers (3,000 nm), or from about 10 nanometers (10 nm) and about 1000 nanometers (1,000 nm) Lt; _{RTI ID} = 0.0 & _gt ; ( Tn ) < / RTI > Alternatively, the In _n Ga _{1 - n} N base layer 112 may be doped. For example, the In _n Ga _{1 -n} N base layer 112 may be doped to an n-type doped with an element that is an electron donor, such as silicon or germanium. In _n Ga _{1 - n} N dopant concentration in the base layer 112 is about ¹⁷ cm ^-3 to about 3e 1e ²⁰ may be in the range of cm ^-3, or between about ¹⁷ 5e cm < ^-3 > to about 1e ¹⁹ cm < ^-3 >.

The first electrode contact may be formed over at least a portion of the base layer 102 after forming at least one of the various other layers of the semiconductor structure 100 comprising InGaN for manufacturing a light emitting device from the semiconductor structure 100 have.

The completed base layer 102, as shown in Fig. 1a, growth template 113 and the optional In _n Ga ₁ as described herein above _- include _n N base layer 112. The various Group III nitride layers of the semiconductor structure 100 may be grown or formed in a layer-by-layer process, which will be described in more detail later herein. In some embodiments, base layer 102 may comprise a base from which other layers of semiconductor structure 100 may grow or form. Thus, the various Group III nitride layers of the semiconductor structure 100 may be oriented such that the base layer 102 is actually positioned on the bottom during fabrication, but sequentially starting with the base layer 102 ≪ / RTI > can be grown or formed and can be moved from the left side to the right side from the perspective view of Fig. In other words, the structure can be oriented counterclockwise 90 degrees in the direction of Figure 1a during manufacture.

Active region 106 is disposed between base layer 102 and p-type contact layer 104, as discussed in more detail below. The active region 106 includes at least one InGaN well layer 114 and at least one InGaN barrier layer 116. In some embodiments, the active region 106 may be composed at least substantially of InGaN (if no dopant is present) and the indium content of the InGaN well layer 114 is strictly less than the indium content of the InGaN barrier layer 116 more. In particular, the active region 106 may include at least one well layer 114 comprising In _w Ga _{1 - w} N, where w is 0.10? W? 0.40, or in some embodiments , 0.12? W? 0.25, or, in another embodiment, w is equal to about 0.14. Active region 106 is also In _b Ga _{1 - b} include at least one barrier layer 116 containing N, and at this time, and b <w, and 0.01≤b≤0.10, or in some embodiments 0.03 b 0.08, or in another embodiment b is equal to about 0.05. In some embodiments, the InGaN barrier layer 116 may be near (e.g., immediately adjacent) the at least one InGaN well layer 114.

When the active region 106 of the semiconductor structure is fabricated in a light emitting device such as a light emitting diode (LED), electrons and holes are regions of a semiconductor structure that recombine with each other to produce photons, which are emitted from the LEDs. In some embodiments, the photons are emitted in the form of visible light. At least some of the visible light may have wavelengths or wavelengths in the electromagnetic radiation spectrum range from about 380 nanometers (380 nm) to about 560 nanometers (560 nm).

The active region 106 of the semiconductor structure 100 includes at least one InGaN well layer 114 and at least one InGaN barrier layer 116 and in some embodiments ) InGaN. &Lt; / RTI &gt; Thus, the active region 106 may be made essentially of InGaN in some embodiments. The active region 106 comprises a pair of one or more adjacent layers comprising one well layer 114 and one barrier layer 116 wherein each well layer 114 is formed of In _w Ga _{1 - w} N, where w is 0.10? w? 0.40 and each barrier layer 116 comprises In _b Ga _{1 -b} N, where b is 0.01? b? 0.10, and b &lt; w.

1A and 1B, although in an additional embodiment, the active region 106 of the semiconductor structure 100 may include more than one pair of active layers, Region 106 includes one (1) pair of active layers (well layer 114 and barrier layer 116). For example, the active region 106 of the semiconductor structure 100 may include twenty-five (25) active layers in one (1) adjacent pairs, each pair including a well layer 114 and a barrier layer 116 such that the active region 106 includes an alternating well layer 114 and a stack of barrier layers 116 (in an embodiment that includes one or more pairs). It is understood, however, that the number of barrier layers 116 may not be the same as the number of well layers 114. The well layers 114 may be separated from each other by a barrier layer 116. Thus, the number of barrier layers 116 may be equal to, one more, or one less than the number of well layers 114 in some embodiments.

1A, each well layer 114 is between about 1 nanometer (1 nm) and about 1000 nanometers (1,000 nanometers), about 1 nanometer (1 nanometers) and about 100 nanometers (100 nanometers ), Or even an average layer thickness ( T _W ) between about 1 nanometer (1 nm) and about 10 nanometers (10 nm). The well layer 114 may include quantum wells in some embodiments. In such an embodiment, each well layer 114 may have an average layer thickness ( T _W ) of about 10 nanometers (10 nm) or less. In another embodiment, well layer 114 may not include quantum wells and each well layer 114 may have an average layer thickness T _{W of} greater than about 10 nanometers (10 nm) . In such an embodiment, the active region 106 may include what is referred to in the art as a " double heterostructure. &Quot; Each barrier layer 116 may be between about 1 nanometer (1 nm) and about 50 nanometers (50 nanometers), or even about 1 nanometer (50 nanometers), although the barrier layer 116 may be thicker (1 nm) and an average layer thickness ( T _B ) of between about 10 nanometers (10 nm).

One or both of the well layer 114 and the barrier layer 116 may be doped. For example, one or both of the well layer 114 and the barrier layer 116 may be doped n-type by doping an element such as silicon or germanium, which is an electron donor. The concentration of dopant in the well layer 114 is about ¹⁷ cm ^-3 to 3e may be in the range of about 1e ¹⁹ cm ^-3, or in some embodiments about 3e ¹⁷ cm ^-3 to about ¹⁷ cm 5e ^{- 3} &lt; / RTI &gt; Similarly, the concentration of the dopant in the barrier layer 116 may range from about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 , or in some embodiments from about 1e ¹⁸ cm ^-3 to about 3e of ¹⁸ cm ^-3 it may be in the range.

One or both of the well layer 114 and the barrier layer 116 may have a Wurtzite crystal structure. Additionally, in some embodiments, one or both of the well layer 114 and the barrier layer 116 are parallel to the interface or interface between the barrier layer 116 and the well layer 114 of greater than about 3.186 Angstroms A polar growth surface such as a gallium polar growth surface, which may have an average lattice constant in one growth plane. More particularly, in some embodiments, the average growth plane lattice constant ( c ) may be between about 3.186 Angstroms and about 3.2 Angstroms.

The active region 106 comprising at least one well layer and at least one barrier layer is between about 40 nanometers (40 nm) and about 1000 nanometers (1,000 nanometers), about 40 nanometers (40 nanometers) and about 750 nanometers And may have an average overall thickness between nanometers (750 nm), or even between about 40 nanometers (40 nanometers) and about 200 nanometers (200 nanometers).

1A, the semiconductor structure 100 may include additional layers between the active region 106 and the p-type contact layer 104, and / or between the active region 106 and the base layer 102, As shown in FIG. For example, in some embodiments, the semiconductor structure 100 may include a spacer layer 118 between the active region 106 and the base layer 102.

An optional spacer layer 118 In _sp Ga _{1 -} may comprise a layer of _sp N, at this time, sp is 0.01 ≤ sp ≤ 0.10, or 0.03 ≤ a sp ≤ 0.06, or sp is equal to about 0.05. The spacer layer 118 relative to the base layer 102, and in some embodiments, In _n Ga _{1 -} that for _n N base layer 112, may have a different composition (and therefore, different lattice parameter), Can be used to provide a more gradual transition between the base layer 102 and the active region 106 layer. Thus, In Ga _{1 sp -} N _sp spacer layer 118 may be directly disposed between the base layer 102 and the active region 106 in some embodiments. By providing a more gradual transition between the base layer 102 and the active region 106, the stress in the crystal lattice of the various layers of InGaN, and therefore the defects that can be attributed to such stresses, can be reduced. In _sp Ga _{1 -} between _sp N spacer layer 118 is approximately one nanometer (1 nm), and between about 100 nanometers (100 nm), or about 1 nanometer (1 nm) and about 100 nanometers (25nm) Of the average thickness ( T _sp ). As one specific non-limiting example, the average layer thickness ( T _sp ) may be equal to about 10 nanometers (10 nm).

Alternatively, In Ga _{1 sp -} N _sp spacer layer 118 it may be doped. For example, the In _sp Ga _{1 -sp} N spacer layer 118 may be doped with an element that is an n-type electron donor, such as silicon or germanium doping. The concentration of the dopant in the spacer layer 118 may be between about 3e ¹⁷ cm ^-3 and about 1e ¹⁹ cm &lt; ^-3 &gt;. As one specific non-limiting example, the concentration of the dopant in the spacer layer 118 may be equal to about 2e ¹⁸ cm ^-3 .

1A, the semiconductor structure 100 may further include an optional In _cp Ga _{1 - cp} N cap layer 120 disposed between the active region 106 and the p-type contact layer 104 have. The optional In _cp Ga _{1 - cp} N cap layer 120 may comprise a layer of In _cp Ga _{1 - cp} N, where cp is 0.01? Cp? 0.10, or 0.03? Cp? 0.07. As one specific non-limiting example, the value of cp may be equal to about 0.05. In _cp Ga _{1 - cp} N cap layer 120 may be used to avoid the dissolution (dissolution) and / or evaporation (evaporation) of indium in the lower layers (underlying layers) of the active region 106 during subsequent processing at elevated temperatures And / or may function in the same way as the spacer layer.

In _cp Ga _{1 - cp} N cap layer 120 is approximately one nanometer (1 nm) and about 100 nanometers (100 nm), or between about 1 nanometer (1 nm) to about 25 nanometers (25 nm) It can have an average thickness (T _cp) between. As one specific non-limiting example, T _cp may be equal to about 10 nanometers (10 nm) in some embodiments. Optionally, cap layer 120 may be doped. For example, cap layer 120 may be doped p-type by an element that is an electron acceptor, such as magnesium, zinc, and carbon doping. However, in other embodiments, the cap layer 120 may be doped to the n-type. The concentration of dopant in the cap layer 120 may be in the range of about ¹⁷ cm ^-3 to about 3e 1e ¹⁹ cm ^-3, or can be in the range of about 1e ¹⁸ cm ^-3 to about 5e ^18, cm ^-3 have. As one specific non-limiting example, the concentration of dopant in cap layer 120 may be equal to about 2e ¹⁸ cm ^-3 in some embodiments.

The semiconductor structure 100 of the present disclosure may further comprise one or more electron blocking layers (EBLs) disposed between the active region 106 and the p-type contact layer 104. Such an electron blocking layer can act to confine electrons in the active region 106 and prevent the energy level of the band edge of the conduction band, which can prevent overflow of carriers from the active region 106, May comprise a relatively high material compared to the band edge of the conduction band in the region 106. [

As a non-limiting example, FIG. 1A illustrates an electron blocking layer 108 over a cap layer 120 that is opposite the active region 106. In an embodiment including a p-type bulk layer 110, an electron blocking layer 108 may be disposed directly between the cap layer 120 and the p-type bulk layer 110, as shown in Figure 1A .

The electron blocking layer 108 comprises Group III nitride. As a non-limiting example, the electron blocking layer 108 may be composed at least substantially of In _e Ga _1-e N (where no dopant is present), where 0.00 _e 2.02, , It may be constituted at least substantially by GaN (if no dopant is present). In another embodiment, the electron blocking layer 108 may be composed at least substantially of Al _e Ga _1-e N, where 0.00? E? 0.20. In some embodiments, the electron blocking layer 108 (if no dopant is present) may be constituted at least substantially by Al _e Ga _1-e N.

The electron blocking layer 108 may be doped p-type by one or more dopants selected from the group consisting of magnesium, zinc, and carbon. The concentration of one or more dopants in the electron blocking layer 108 is about ¹⁷ 1e may be in the range of about ²¹ cm ^-3 from 1e cm _^-3, or may be equal to about In 3e ¹⁹ cm ^-3 to some embodiments . In some embodiments, the electron blocking layer 108 may have an average layer thickness ( T _e ) ranging from about 5 nanometers (5 nm) to about 50 nanometers (50 nm), or in some embodiments May have an average layer thickness ( T _e ) such as about 20 nanometers (20 nm).

In a further embodiment of the semiconductor structure 100 of the present disclosure, the semiconductor structure 100 may have an electron blocking layer similar to the electron blocking layer 108, inset, 122, a superlattice structure comprising alternating layers of various materials. For example, the electron blocking layer 108 may have a superlattice structure comprising alternating layers of GaN 124 and In _e Ga _{1- e} N 124, where e is in the range of 0.01 &lt; = e &lt; = 0.02 to be. In another embodiment, the electron blocking layer may have a superlattice structure comprising alternating layers of GaN 124 and Al _e Ga _1-e N 126, where e is 0.01? E? 0.20 . In such a superlattice structure, each of the layers may have an average layer thickness of about 1 nanometer (1 nm) to about 20 nanometers (20 nm).

The semiconductor structure 100 of the present disclosure may further include a p-type bulk layer 110 disposed between the electron blocking layer 108 and the p-type contact layer 104, as discussed above. Such a p-type bulk layer may comprise a p-doped Group III nitride material, such as p-doped In _p Ga _1-p N. Such a p-type bulk layer may be used, for example, as a source of a hole carrier and to enhance electrical conductivity and light extraction from the active region 106 and from the active region 106. Incorporation of indium into the p-type bulk layer 110 can help in carrier flow synchronization and carrier confinement in the active area.

The p-type bulk layer 110 may be constituted at least substantially of In _p Ga _{1 - p} N (where no dopant is present), where p is 0? P? 0.08, preferably 0.01? p? In one particular non-limiting example, the p-type bulk layer 110 may be composed at least substantially of In _p Ga _{1 - p} N, where p is equal to about 0.02. The p-type bulk layer 110 may be doped p-type by one or more dopants selected from the group consisting of magnesium, zinc, and carbon. The concentration of the one or more dopants in the p-type bulk layer 110 may range from about 1 e ¹⁷ cm ^-3 to about 1 e ²¹ cm ^-3 . As one specific non-limiting example, the concentration of the dopant in the p-type bulk layer 110 may be equal to about 3e ¹⁹ cm ^-3 . In some embodiments, the p-type bulk layer 110 may have an average layer thickness ( T _p ) ranging from about 50 nanometers (50 nm) to 600 nanometers (600 nm). As one specific non-limiting example, the p-type bulk layer 110 may have an average layer thickness ( T _p ) such as about 175 nanometers (175 nm).

The semiconductor structure 100 may further include a p-type contact layer 104 disposed on the p-type bulk layer 110, opposite the electron blocking layer 108. The p-type contact layer 104 may comprise Group III nitride. Such a p-type contact layer may be used, for example, to improve the conductivity of holes to the active region 106. [ The p-type contact layer 104 is formed from a high concentration of one or more dopants, such as a p-type dopant (e. g., a p-type dopant), to limit the electrical resistance of the electrode contact formed over a portion of the p- . &Lt; / RTI &gt;

As a non-limiting example, the p-type contact layer 104 may comprise p-type doped In _c Ga _{1 - c} N. For example, the p-type contact layer 104 may be composed at least substantially of In _c Ga _{1 - c} N (where no dopant is present), where c is 0.01? C? In an embodiment, the p-type contact layer 104 (if no dopant is present) may be constituted at least substantially by GaN. The inclusion of indium in the p-type contact layer 104 is beneficial in that it produces a low operating voltage for the device and can reduce the energy barrier by the metal electrode formed on the device do. The p-type contact layer 104 may be p-type doped by one or more dopants selected from the group consisting of magnesium, zinc, and carbon. The concentration of the one or more dopants in the p-type contact layer 104 may range from about 1 e ¹⁷ cm ^-3 to about 1 e ²¹ cm ^-3 . As one specific non-limiting example, the concentration of one or more dopants in the p-type contact layer 104 may be equal to about 1e ²⁰ cm ^-3 . The p-type contact layer 104 may have an average layer thickness ( T _c ) ranging from about 2 nanometers (2 nm) to about 50 nanometers (50 nm). As one specific non-limiting example, the p-type contact layer 104 may have an average layer thickness ( T _c ) such as about 15 nanometers (15 nm). As shown in FIG. 1A, a p-type contact layer 104 may be formed directly on the p-type bulk layer 110.

As will be described in more detail below, the completed semiconductor structure 100 may be used in the manufacture of one or more semiconductor light emitting devices, such as LEDs. In short, the electrodes contact the base layer (102) over a portion of the semiconductor layer, for example, In _n Ga _{1 a-may} be formed over at least a portion of the _n N base layer 112, part or on GaN seed layer 656 of, Additional electrode contacts can be formed over at least a portion of the p-type contact layer 104 to provide a resultant emission resulting from electromagnet radiation, in which the charge carrier can be in the form of visible light. To be injected into the region 106.

1B is a simplified diagram illustrating the energy levels (in the energy band diagram) of the conduction band 128 for various semiconductor materials in the various layers of the semiconductor structure 100 of FIG. 1A (growth substrate 658 and Group III Note that nitride nucleation layer 660 is omitted). 1B is vertically aligned with the semiconductor structure 100 of FIG. The vertical dashed line in FIG. 1B aligns with the interface between the various layers of the semiconductor structure 100 of FIG. 1A. The vertical axis in FIG. 1B is energy, and the high energy level is vertically positioned above the low energy level. It should be noted that Figure IB shows a non-limiting example of the conduction band energy levels for the exemplary semiconductor structure 100. As a result, relative positions of the relative horizontal conduction band energy levels can vary as a function of at least the composition of the individual semiconductor layers and the doping, and the composition ranges of the various semiconductor layers are in the ranges as described above. Thus, FIG. 1B can be used to view the relative differences in the energy levels of conduction band 128 in the various layers of semiconductor structure 100. The energy level of the conduction band 128 in the well layer 114 may be lower than the energy level of the conduction band 128 in the other layer of the semiconductor structure 100,

As is known in the art, for a Group III nitride layer, such as InGaN, the energy level of the conduction band 128 is a function of a number of variables including, but not limited to, indium content and dopant level. The energy level of the conduction band 128 in the well layer 114 may be greater than the energy level of the conduction band 128 in the barrier layer 116. [ Level. As a result, a charge carrier (e. G., Electrons) may accumulate in the well layer 114 during operation of the light emitting device fabricated from the semiconductor structure 100, and the barrier layer 116 may &lt; May function to impede movement of the carrier (e.g., electrons). Thus, in some embodiments, the indium content in each well layer 114 may be higher than the indium content in each barrier layer 116. For example, the difference between indium content in each well layer 114 and indium content in each barrier layer 116 may be greater than or equal to about 0.05 (i.e., w - b &gt; / = 0.05) (I.e., w - b &gt; = 0.20). In some embodiments, the dopant concentration in the barrier layer 116 may be different from the dopant concentration in the well layer 114. High doping concentrations can cause defects in the crystal structure of InGaN, and such defects can result in non-radiative combinations of electron-hole pairs. In some embodiments, the dopant concentration in the well layer 114 is greater than the non-emissive combination of electron-hole pairs in the well layer 114 relative to the ratio of non-radiative combinations of electron-hole pairs in the barrier layer 116 Lt; RTI ID = 0.0 &gt; 116 &lt; / RTI &gt; In another embodiment, the dopant concentration in the barrier layer 116 may be higher than the dopant concentration in the well layer 114.

1B, the energy barrier provided by the electron blocking layer 108 may be applied to the electron blocking layer 108 and the cap layer 120 (or the electron blocking layer 108 at the side closest to the active region 106) (The other layer immediately adjacent to the conductive layer 128). The height of the energy barrier can be changed by changing the composition of the electron blocking layer 108. For example, as shown in FIG. 1B, the conduction energy level 130 (indicated by the solid line) (if no dopant is present) may represent the conduction band energy level for the electron blocking layer consisting of at least substantially GaN . The conduction band energy level in the electron blocking layer is at least substantially equal to that of the GaN electron blocking layer as shown by the conduction band energy level 132 (shown by the dashed line) by forming an electron blocking layer consisting essentially of In _e Ga _1-e N E, where 0.01 &lt; / = e &lt; / = 0.02. In another embodiment, the conduction band energy level is at least substantially proportional to the conduction band energy level 134 (shown by the dashed line) by forming an electron blocking layer comprised substantially of Al _e Ga _1-e N, Layer, where e is 0.01 &lt; = e &lt; = 0.20. The energy level of the conduction band in the electron blocking layer can therefore be varied to provide the desired conduction band off-set between the other Group III nitride layer of the semiconductor structure 100 and the electron blocking layer 108 have.

In embodiments of the semiconductor structure 100 having a superlattice structure in which the electron blocking layer 108 comprises alternating layers of various materials, the conduction band energy levels may be the same as the period shown in inset 136 of FIG. And may be increased and decreased in a periodic like manner. For example, the electron blocking layer 108 may have a superlattice structure comprising alternating layers of GaN 138 and Al _e Ga _1-e N 140, where e is in the range of 0.01 & Or alternatively, the superlattice structure may comprise alternating layers of GaN and In _e Ga _1-e N, where e is 0.01? E? 0.02. The magnitude of the conduction band energy off-set between alternating layers of various materials can be selected by the difference in composition between the GaN layer and the Al _e Ga _1-e N or In _e Ga _1-e N layers.

The semiconductor structure of the present disclosure may further include an electron stopping layer disposed between the active region 106 of the semiconductor structure and the base layer 102 of the semiconductor structure. Such an electron stopping layer can function to further confine electrons in the active region of the energy band edge of the conduction band and can prevent carrier overflow from the active region and improve the uniformity of the carriers in the active region It may include a relatively high n- doped group III nitride material than the band edge of the conduction band in the base layer _n n _{- (uniformity), in n Ga} 1 offering.

By way of non-limiting example, FIGS. 2A and 2B illustrate an embodiment of a semiconductor structure 200 including such an electron stopping layer 202. The semiconductor structure 200 is similar to the semiconductor structure 100 and includes an active region (not shown) including one or more InGaN well layers 114 and one or more InGaN barrier layers 116 as described above in connection with the semiconductor structure 100 106). The semiconductor structure 200 also includes a base layer 102, a spacer layer 118, a cap layer 120, an electron blocking layer 108, a p-type bulk layer (not shown) as described above with respect to the semiconductor structure 100 110 and a p-type contact layer 104. Disposed between the _n N base layer 112 and spacer layer 118, _E-stop layer 202 of the semiconductor structure 200 includes a base layer 102 and is disposed between the active region (106), In _n Ga ₁ .

The electron stopping layer 202 comprises Group III nitride. As a non-limiting example, the electron stopping layer 202 may comprise n-type doped AlGaN. For example, in some embodiments, the electron stop layer 202 (if a dopant is present) may be at least substantially made up of the Al Ga _{1-st st} N, at this time, st is 0.01≤st≤0.20 to be. In another embodiment, the electron stopping layer 202 comprises a superlattice structure comprising alternating layers of Al _st Ga _{1 -st} N 206 and a layer of GaN 208 as shown in inset 204 , Where 0.01? St? 0.20. The semiconductor structure 200 may include any number of alternating layers of layers of Al _st Ga _{1 -st} N 206 and GaN 208 (e.g., from about one (1) to about twenty (20) have. The layers 206 and 208 in such a superlattice structure may have an average layer thickness of about 1 nanometer (1 nm) to about 100 nanometers (100 nm).

The electron stopping layer 202 may be doped n-type by one or more dopants selected from the group consisting of silicon and germanium. The concentration of one or more dopants in the electron stop layer 202 may be from about 0.1e ¹⁸ cm ^-3 in the range of 20e ¹⁸ cm ^-3. In some embodiments, the electron stopping layer 202 may have an average layer thickness ( T _st ) ranging from about 1 nanometer (1 nm) to about 50 nanometers (50 nm).

FIG. 2B is a simplified conduction diagram and shows the relative energy levels of the conduction band 228 for various materials of the semiconductor structure 200. FIG. 2B, the energy level of the conduction band 228 in at least a portion of the electron stopping layer 202 of the semiconductor structure 200 (FIG. 2B) The energy level of the conduction band 228 in the layer 102 and / or the energy level of the conduction band 228 in the spacer layer 118 is relatively high. The electron stop layer 202 comprises alternating layers of layers of Al _st Ga _{1 -st} N 206 and GaN 208, where 0.01? St? 0.20, inset 210 of FIG. In an embodiment including a superlattice structure such as that in which the conduction band energy level is changed periodically.

In a further embodiment, the semiconductor structure of the present disclosure may include one or more layers of material between the active region and the base layer, which are employed to facilitate fabrication of the semiconductor structure. For example, in some embodiments, the semiconductor structure of the present disclosure, and one or more light emitting devices fabricated from such a structure, may include at least one strain relief layer (not shown) disposed between the active region and the base layer 102 Where strain relief layers may be constructed and configured to accommodate deformation of the crystal lattice of the crystal structure of the various layers of the semiconductor structure between the base layer 102 and the p-type contact layer, The layer may be epitaxially grown over the layer-by-layer process.

As a non-limiting example, FIGS. 3A and 3B illustrate an embodiment of a semiconductor structure 300 that includes such a strain relief layer 302. Semiconductor structure 300 is similar to semiconductor structure 100 and includes an active region (not shown) comprising at least one InGaN well layer 114 and at least one InGaN barrier layer 116 as described above in connection with semiconductor structure 100 106). Semiconductor structure 300 also includes a base layer 102, a spacer layer 118, a cap layer 120, an electron blocking layer 108, a p-type bulk layer (not shown), as described above with respect to semiconductor structure 100 110 and a p-type contact layer 104. The strain relief layer 302 of the semiconductor structure 300 is disposed between the base layer 102 and the spacer layer 118. In the embodiment of Figures 3a and 3b, the strain relief layer 302 In _n Ga _{1 -} is disposed directly between the _n N base layer 112 and the In _{sp sp} Ga1- N spacer layer 118.

The strain relief layer 302 may comprise Group III nitride. As a non-limiting example, strain relief layer 302 includes alternating layers of In _sra Ga _1-sra N 306 and In _srb Ga _{1 -srb} N 308, where 0.01 sra Lt; = 0.10, 0.01 &lt; = sb &lt; / = 0.10. Also, sra can be larger than srb. Semiconductor structure 300 In _sra Ga _{1 -} to _srb N (308), an arbitrary number of alternating layers of (e. G., From about twenty (20) from about one (1) _{- sra} N layer 306 and the In _srb Ga ₁ ). The layers 306 and 308 in such a superlattice structure may have an average layer thickness of about 1 nanometer (1 nm) to about 20 nanometers (20 nm).

The strain relief layer 302 may be doped n-type by one or more dopants selected from the group consisting of silicon and germanium. The concentration of one or more dopants in the strain reducing layer 302 may be from about 0.1e ¹⁸ cm ^-3 in the range of 20e ¹⁸ cm ^-3. In some embodiments, strain relief layer 302 may have an average layer thickness ranging from about 1 nanometer (1 nm) to about 50 nanometers (50 nm).

3B is a simplified conduction diagram and shows the relative energy levels of the conduction band 328 for various materials in the semiconductor structure 300. FIG. 3B, the energy level of the conduction band 328 in at least a portion of the strain relief layer 301 (FIG. 3A) of the semiconductor structure 300 is greater than the energy level of the In the energy level of the conduction band 328 in the _n Ga _{1 - n} N base layer 112 and / or the energy level of the conduction band 328 in the spacer layer 118 may be relatively low. The energy level of the conduction band 328 in at least a portion of the strain relief layer 302 (Figure 3A) of the semiconductor structure 300 is greater than the energy level of the conduction band 328 in the InGaN base layer 112 and / Or the energy level of the conduction band 328 in the spacer layer 118 may be relatively high. As shown in inset 310 in Figure 3b, the strain relief layer are alternating layers In _sra Ga _{1 - sra} N layer 306 and the _{In srb Ga 1-srb N (} 308) comprising a superlattice structure including In an embodiment, the conduction band energy level may change periodically.

4A and 4B illustrate another embodiment of the semiconductor structure 400 of the present disclosure. The semiconductor structure 400 is similar to the semiconductor structure 100 and includes an active region (not shown) including one or more InGaN well layers 114 and one or more InGaN barrier layers 116 as described above with respect to the semiconductor structure 100 406). The semiconductor structure 400 also includes a base layer 102, a spacer layer 118, a cap layer 120, an electron blocking layer 108, a p-type bulk layer (not shown), as described above with respect to the semiconductor structure 100 110 and a p-type contact layer 104. The active region 406 of the semiconductor structure 400 further includes an additional GaN barrier layer 402. Each of the additional GaN barrier layers 402 may be disposed between the InGaN well layer 114 and the InGaN barrier layer 116. The additional GaN barrier layer 402 may also function to confine electrons within the well layer 114, where electrons may tend to recombine further with holes and may result in increased radiation emission probability have.

In some embodiments, each GaN barrier layer 402 may be doped n-type by one or more dopants selected from the group consisting of silicon and germanium. For example, the concentration of one or more dopant in the GaN barrier layer 402 may be from about 1.0e ¹⁷ cm ^-3 in the range of 50e ¹⁷ cm ^-3. In some embodiments, each GaN barrier layer 402 may have an average layer thickness T _b2 ranging from about 0.5 nanometers (0.5 nm) to about 20 nanometers (20 nm).

FIG. 4B is a simplified conduction diagram and shows the relative energy levels of conduction band 428 for various materials in semiconductor structure 400. FIG. 4A, the energy level of the conduction band 428 in the GaN barrier layer 402 (FIG. 4A) is greater than the energy level of the conduction band 428 in the InGaN barrier layer 116 And the energy level of the conduction band 428 in the InGaN well layer 114 may be relatively high.

FIGS. 5A and 5B illustrate another embodiment of the present disclosure including semiconductor structure 500. FIG. In this embodiment, the method disclosed in U.S. Patent Application No. 13 / 362,866, filed January 31, 2012, in the name of Arena et al., May be used to form the active region 506. The semiconductor structure 500 is similar to the semiconductor structure 100 and includes an active region (not shown) including one or more InGaN well layers 514 and one or more InGaN barrier layers 516 as described above with respect to the semiconductor structure 100 506). The semiconductor structure 500 also includes a base layer, a spacer layer, a cap layer, an electron blocking layer, a p-type bulk layer 100 and a p-type contact layer as described above with respect to the semiconductor structure 100. For clarity, surrounds the active region 506 is only the layer is shown, these layers are optional spacer layer 118 and cap layer 120 and the In _n Ga _{1 - n} N base layer 112 and an electron blocking layer ( 108 &lt; / RTI &gt; If a selective layer is omitted from the semiconductor structure 500, the active region 506 may be disposed directly between the base layer 102 and the electron blocking layer 108.

The active region 506 of the semiconductor structure 500 is similar to the active region 100 of the semiconductor structure but further comprises two or more InGaN barrier layers wherein the band gap energy between the subsequent barrier layers is shown in Figures 5A and 5B. 5b from the right to the left, i. E. From the cap layer 120 to the spacer layer 118. As shown in Fig. This configuration of the active region 506 in the semiconductor structure 500 can prevent carrier overflow out of the active region 506 and help confine the charge carriers within the active region 500, Thereby increasing the efficiency of the light emitting device manufactured from the structure 500.

Barrier region (516 _AC) is each band may have a selected material composition and structural configuration to provide a respective barrier region (516 _AC) having the gap energy (550 _AC), this time, the band-gap energy of the semiconductor Is given by the energy difference between the valence band energy (552) and conduction band energy (528) of each of the semiconductor materials including the structure (500). In be smaller than the gap energy (550 _B) and the second barrier regions (516 _B)-gap energy (550 _A) of the second barrier regions (516 _B) band at - the first barrier region (516 _A) bands at the band-gap energy (550 _B) of the band in a third barrier zone (516 _C) as shown in the energy band diagram of Figure 5b - may be less than the energy gap (550 _C). Furthermore, each of the band-gap energies of the quantum well region 552 _AC may be substantially the same and may be less than each of the band-gap energies 516 _AC of the barrier region 550 _AC .

_A hole energy barrier 554 _A between the first quantum well 514 _A and the second quantum well 514 _{B is} formed between the second quantum well 516 _B and the third quantum well 516 _C , It may be less than the energy barrier (554 _B). In other words, the hole energy barrier 554 _AC across the barrier region 516 _AC may increase stepwise across the active region 506 in the direction of the spacer layer 118 from the cap layer 120. The electron hole energy barrier 554 _AC is the energy difference of the valence band 552 across the interface between the quantum well region 514 _AC and the adjacent barrier region 516 _AC . Increasing the electron hole energy barrier 554 _AC across the barrier region 516 _AC moving from the cap layer 120 toward the spacer layer 108 results in an increase in hole uniformity within the active region 506 Thereby improving the efficiency during operation of the light emitting device fabrication from the semiconductor structure 500.

As mentioned above, barrier region 516 _AC may have a material composition and a structural configuration selected to provide their respective, respective band-gap energies 550 _AC to each of barrier regions 516 _{AC .} By way of example and not as limitation, each of the barrier region (516 _AC) is the third III- nitride material, such as Ga ₁ In _{b3 - b3} may include N, at this time, b3 is at least about 0.01. In _b3 Ga ₁ of the barrier region (516 _{AC) -} (one to i.e., decrease the value of b3) will be to reduce the indium content in the _b3 N is the band of the barrier region (516 _AC) - thereby increasing the gap energy. Thus, the second barrier regions (516 _B) can have a low indium content of the first barrier region (516 _A), a third barrier zone (516 _C) is a low indium content for the second barrier regions (516 _B) Lt; / RTI &gt; In addition, barrier region 516 _AC and well region 514 _AC may be doped and have an average layer thickness as described above for semiconductor structure 100.

As mentioned above, according to an embodiment of the present disclosure, the active region 106 (of FIG. 1A) may include at least one InGaN well layer and at least one InGaN barrier layer, and in some embodiments , At least substantially InGaN (e.g., which may be essentially composed of InGaN if no dopant is present). A number of already known light emitting device structures including an InGaN well layer include a GaN (at least substantially indium-free) barrier layer. The difference in the energy levels of the conduction band between the InGaN well layer and the GaN barrier layer is relatively high and, according to the teachings of this technique, can provide improved confinement of the charge carriers in the well layer and improve the efficiency of the LED structure. However, the structures and methods of the prior art can lead to a reduction in device efficiency due to carrier overflow and piezoelectric polarization.

In the carrier overflow theory, one or more quantum well layers may be similar to a water bucket, and this ability to capture and maintain an implanted carrier weakens the high implantation of the carrier. When the injected carrier is not captured or maintained, it overflows and wastes the active area, contributing to reduced device efficiency. In a prior art structure comprising an InGaN quantum well and a GaN barrier layer, the band-off, i.e., the difference in the conduction band energy levels between the quantum well and the barrier, is substantially made up of InGaN, as described in the embodiments herein. Lt; / RTI &gt; for the active region being &lt; / RTI &gt; Decreasing the band-off-set in the structures described herein allows the injected carriers to be more efficiently distributed across the quantum well regions of the active region, thereby increasing the efficiency of the light emitting device fabricated from the semiconductor structure described herein.

In addition, due to the lattice mismatch between the InGaN well layer and the GaN barrier layer, a relatively strong piezoelectric polarization occurs in the active region of such a light emitting device structure. Piezoelectric polarization can reduce the overlap between the wave function for electrons and the wave function for holes in the active region of the light emitting device structure. For example, JH Son and JL Lee, " Numerical Analysis of Efficiency Droop Induced by Piezoelectric Polarization in InGaN / GaN Lighth- Emitting Diodes , Appl. Phys. Lett. 97, 032109 (2010), piezoelectric polarization may cause what is termed "efficiency droop" in such a light emitting device structure (e.g., LED) (Decrease) in the graph of the internal quantum efficiency (IQE) of the LED structure having the quantum efficiency.

An embodiment of the light emitting structure of the present disclosure, such as an LED structure, alleviates or overcomes problems of already known LED structures with GaN barrier layers and InGaN well layers associated with lattice mismatch, i.e., carrier overflow, piezoelectric polarization, can do. An LED structure fabricated from an embodiment of the presently disclosed LED, e.g., the semiconductor structure 100 of FIGS. 1A and 1B, can be constructed and its energy band structure is designed such that the active region 106 is reduced A piezoelectric polarization effect, and an increased overlap of the wave function of the electron and the wave function of the hole. As a result, a light emitting device, such as an LED, may exhibit reduced uniformity of charge carriers across the active region 106, and reduced efficiency degradation with increasing current density.

These advantages that can be achieved through embodiments of the present disclosure are discussed further below with reference to Figures 10a and 10b, 11a-11e, 12a and 12b, and 13a-13e. 10A and 10B illustrate an embodiment of an LED 556 similar to a previously known LED. The LED 556 includes an active region 558 comprising five (5) InGaN well layers 562 having a GaN barrier layer 564 disposed between the InGaN well layers 562. LED 556 also includes a base layer 560, a first spacer layer 566, a second spacer layer 568, an electron blocking layer 570, and an electrode layer 572. In LED 556, the InGaN well layer 562 is formed of In _{0 . 18} Ga _{0 .82} N, each of which has an average layer thickness of about 2.5 nanometers (2.5 nm). Barrier layer 564 includes a layer of GaN that may have an average layer thickness of about 10 nanometers (10 nm). Base layer 560 includes a layer of doped GaN having an average layer thickness of about 325 nanometers (325 nm), which is n-type doped by silicon at a concentration of about 5e ¹⁸ cm ^-3 . The first spacer layer 566 may comprise undoped GaN having an average layer thickness of about 25 nanometers (25 nm). The second spacer layer 568 may also include undoped GaN having an average layer thickness of about 25 nanometers (25 nm). The electron blocking layer 570 may comprise p-doped AlGaN. Electrode layer 572 may comprise a doped GaN layer, this electrode layer has an average of about 125 nanometers (125 nm) is doped with p- type by magnesium at a concentration of about 5e ¹⁷ cm ^-3 Thickness. FIG. 10B is a simplified conduction band diagram similar to that of FIG. 1B and shows the relative differences in the energy levels (in the energy band diagram) of conduction band 574 for various materials in the various layers of LED 556 in FIG. 10A. The vertical dashed line in Fig. 10B aligns with the interface between the layers in LED 556 in Fig. 10A.

As known in the art, for example, the 8x8 Kane Model disclosed in SL Chuang and CS Chang, " k.p.Method for Strained Wurtzite Semiconductors , Phys.Rev. B 54, 2491 (1996) Group III nitride materials such as GaN and InGaN. The split-off branch of the valence band at the center of the Brillouin zone and the splitting of the heavy, light, has a built-in electric field, Can be assumed to be independent. Therefore, valence subbands can be obtained from the solution of the combined Poisson and transport equations. The wave functions of electrons and holes are respectively:

, 및

, And

및

는 브릴루엥 영역(Brilluene zone)의 중심에 대응하는 전자 및 정공의 블로호 진폭(Bloch amplitudes)이고,

및

는 평면 내 유사-모멘트 벡터(quasi-moment vectors)이고,

및

는 덮개 함수(envelope functions)이고, 아래 첨자 "s"는 중(hh), 경(lh), 또는 분할(so) 정공일 수 있다. 전자 및 정공 덮개 함수에 대한 일차 슈뢰딩거 방정식은 각각:Quot; form &quot;, and at this time,

And

Is the Bloch amplitudes of electrons and holes corresponding to the center of the Brillouene zone,

And

Is the in-plane quasi-moment vectors,

And

Is the envelope functions, and the subscript "s" can be medium (hh), light (lh), or split (so). The first order Schrodinger equation for the electron and hole cover functions is:

, 및

, And

이고,

ego,

및

는 양자 우물에서 전자 및 정공에 대한 유효 퍼텐셜이고,

및

는 전자 및 정공 에너지 준위이고,

및

은 에피택셜 성장 방향에서의 전자 및 정공 유효 질량이다. 대응하는 경계 조건으로 상기 슈뢰딩거 방정식을 풀음으로써, 전자 및 정공 파동 함수 간의 중첩 적분은:At this time,

And

Is the effective potential for electrons and holes in the quantum well,

And

Is an electron and hole energy level,

And

Is the effective mass of electrons and holes in the direction of epitaxial growth. By solving the Schrödinger equation with corresponding boundary conditions, the superposition integral between the electron and hole wave functions is:

Lt; / RTI &gt;

As disclosed in SL Chuang, " Physics of Phonic Devices , 2 ^nd Ed. (Wiley, New Jersey, 2009) &quot;, the ratio of electron recombination and hole recombination is:

Where B is the emissive recombination coefficient, n is the electron concentration, p is the hole concentration, and F _n - F _p is the quasi-Fermi level separation. The electron and hole concentration and pseudo-Fermi level separation vary from location to location across the active area of the LED. The maximum radiant recombination rate can be identified in any quantum well and can be considered as the peak radiant recombination rate for each of its quantum wells.

Figure 11A illustrates the relationship between the applied current of zero across the LED 556 as a function of the position (in nanometers) of the LED 556 beginning at the surface of the base layer 560 that is opposite the active region 558 , The calculated energy of the band edges of the conduction band 574 and the valence band 576 for the LED 550 of FIGS. 10A and 10B. 11B is similar to FIG. 11A, except that at the current density applied across the LED 556 of 1205 amperes / square centimeter (125 A / cm ² ), the conduction band 574 for the LED 556 of FIGS. 10A and 10B, Lt; RTI ID = 0.0 &gt; 576 &lt; / RTI &gt; Figure 11C illustrates the calculation of the wavelength for each of the five quantum well layers 562 of the LED 556 with an applied current density across the LED 550 of 125 amperes per square centimeter (125 A / cm ² ) Fig. QW1 is the first left quantum well layer 562 and QW5 is the first right quantum well layer 562 from the perspective view of Figures 10A and 10B. 11D shows the calculated injection efficiency of the LED 556 as a function of the applied current density. 11D, the LED 550 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A / cm &lt; ² &gt;. FIG. 11E shows the calculated internal quantum efficiency (IQE) of the LED 556 as a function of the applied current density. 11E, the LED 556 may exhibit an internal quantum efficiency of about 45.2% at an applied current density of 125 A / cm &lt; ² &gt;. 11E, the internal quantum efficiency of LED 556 drops from more than 50% at an applied current density of about 20 A / cm ² to less than 40% at an applied current density of 250 A / cm ² . As discussed above, this drop in IQE is referred to in this technique as efficiency degradation.

The following Table 1 shows the calculated wave function overlap and peak emission recombination rates for each of the five quantum well layers 562 in LED 550 of FIGS. 10A and 10B.

QW1 QW2 QW3 QW4 QW5 Wave function overlap 0.328 0.326 0.325 0.341 0.362 Peak emission recombination rate 6.5e ²⁶ 3.3e ²⁶ 3.3e ²⁶ 6.8e ²⁶ 2.4e ²⁷

As can be seen from FIG. 11C and Table 1 above, the emissive recombination occurs at the last well layer 562 (closest to the p-doped side, or anode), which is quantum well number 5 (i.e., QW5) . In addition, as shown in FIG. 11E, the LED 556 may be formed at least partially due to the piezoelectric polarization caused by the use of the InGaN well layer 562 and the GaN barrier layer 564, as discussed hereinabove Indicates a decrease in efficiency

An embodiment of the LEDs of the present disclosure comprising at least one InGaN well layer and at least one active region including an InGaN barrier layer, for example an active region 106 of LED 100, Can exhibit improved uniformity, and can exhibit reduced efficiency reduction. A comparison of LED 550 and an embodiment of the LED of the present disclosure is provided below with reference to Figures 12A and 12B, and 13A through 13E.

12A and 12B illustrate another example of an embodiment of the LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five (5) InGaN well layers 114 and an InGaN barrier layer 116 disposed between the InGaN well layers 114. The InGaN well layer 114 and the InGaN barrier layer 116 may be as previously described with reference to the semiconductor structure 100 with reference to FIGS. 1A and 1B. The LED 600 also includes a base layer 112, a first spacer layer 118, a cap layer 120, and an InG electrode layer 104. In LED 600, the InGaN well layer 114 is formed of In _{0 . 18} Ga _{0 .82} N, each of these layers having an average layer thickness of about 2.5 nanometers (2.5 nm). The barrier layer 116 is formed of In _{0 . 08} comprises a layer of Ga _{0 .92} N and each of which can have an average thickness of about 10 nanometers (10 nm). The base layer 112 is doped with doped In ₀ .03 with an average layer thickness of about 300 nanometers (300 nm) doped n-type by silicon at a concentration of about 5e ¹⁸ cm ^-3 _{. 05} comprises a layer of Ga _{0 .95} N. The first spacer layer 118 is an undoped In ₀ .0 &lt; RTI ID = 0.0 &gt; GaN &lt; / RTI &gt; layer having an average layer thickness of about 25 nanometers (25 nm) _{. 08} may include a Ga _{0 .92} N. The cap layer 120 also has an undoped In _0. &Lt; RTI ID = 0.0 &gt; _{0. &} Lt; / RTI & gt _{; 08} may include a Ga _{0 .92} N. The electrode layer 104 is a doped In ₀ .0 &lt; - &gt; layer, which may have an average layer thickness of about 150 nanometers (150 nm) doped p-type by magnesium at a concentration of about 5e ¹⁷ cm ^-3 _{. Lt;} RTI ID = _0.0 &gt; _Ga0.95 &lt; / RTI &gt; N. FIG. 12B is a simplified conduction diagram illustrating the relative differences (in the energy band diagram) at the energy levels of the conduction band 602 for various materials in the various layers of the LED 600 of FIG. 12A.

13A shows the relationship between the applied current of zero across the LED 600 and the applied current of the LED 600 as a function of position (in nanometers) across the LED 600 starting at the surface of the base layer 112, Together are graphs illustrating the calculated energies of the band edges of the conduction band 602 and the valence band 604 for the LED 600 of FIGS. 12A and 12B. Figure 13b is the conduction band 602 of the LED (600) in FIG similar to that of 13a, but 125 amps / square centimeter (125 A / cm ²⁾ LED also in the applied current density across the (600) 12a of and 12b And the calculated energy of the band edge of the valence band 604. 13C illustrates the calculation of the wavelength for each of the five quantum well layers 108 of the LED 600 with an applied current density across the LED 600 of 125 amperes per square centimeter (125 A / cm ² ) Fig. QW1 is the leftmost quantum well layer 108 and QW5 is the rightmost quantum well layer 108 from the perspective view of Figures 12A and 12B. 13D shows the calculated injection efficiency of the LED 600 as a function of the applied current density. As shown in Fig. 13d, LED (600) is 125 A / in the current density applied to the cm ² may represent the injection efficiency of about 87.8%, about 20 A / cm ² to about 250 the current density A / cm ² from Lt; RTI ID = 0.0 &gt; 80%. &Lt; / RTI &gt; 13E shows the calculated internal quantum efficiency (IQE) of the LED 600 as a function of the applied current density. 13E, the LED 600 may exhibit an internal quantum efficiency of about 58.6% at an applied current density of 125 A / cm &lt; ² &gt;. 13E, the internal quantum efficiency of the LED 600 can be maintained between about 55% and about 60% at an applied current density ranging from about 20 A / cm ² to 250 A / cm ² . Thus, LED 600 exhibits very low efficiency degradation and significantly lower efficiency than LED 500 (efficiency of LED 500 is not consistent with the embodiment of the present disclosure).

Table 2 below shows the calculated wave function overlap and peak emission recombination rates for each of the five quantum well layers 108 in the LED 600 of Figures 12A and 12B.

QW1 QW2 QW3 QW4 QW5 Wave function overlap 0.478 0.493 0.494 0.494 0.471 Peak emission recombination rate 7.8e ²⁶ 7.7e ²⁶ 7.9e ²⁶ 8.1e ²⁶ 8.3e ²⁶

As can be seen from Figure 13c and Table 2 above, the emissive recombination is more uniform over the well layer 108 in the LED 600 compared to the well layer 508 in the LED 500.

LEDs 550 in FIGS. 10A and 10B and LEDs 600 in FIGS. 12A and 12B are modeled using SiLENSe software, commercially available from STR Group, Inc. SiLENSe software was also used to generate the graphs of Figures 11a-11e and 13a-13e and to obtain the data described in Tables 1 and 2. [

According to some embodiments of the present disclosure, LED is from about 20 A / at least about 45% over from cm ² in the range of current density of about 250 A / cm ^2, or even from about 20 A / cm ² of about 250 A / lt; RTI ID = 0.0 &gt; cm &lt; / ^RTI &gt; of current density. In addition, the LED may exhibit at least substantially constant carrier injection efficiency over a range of current densities from about 20 A / cm ² to about 250 A / cm ² . In some embodiments, the LED of the present disclosure may exhibit a carrier injection efficiency of at least about 80% over a range of current densities from about 20 A / cm ² to about 250 A / cm ² .

Non-limiting examples of the semiconductor structures of the embodiments of the present disclosure and methods that can be used to fabricate light emitting devices, such as LEDs, are briefly described below with reference to FIG. 6D and an example of a light emitting device manufactured by such a method Are described with reference to Figs. 7 and 8. Fig.

6D, a growth template 113 (made as previously described previously) comprising a growth substrate 658, a Group III nitride nucleation layer 660 and a GaN seed layer 656 is deposited in a deposition chamber And a layer comprising a Group III nitride material, commonly referred to as a growth stack 682, may be grown epitaxially sequentially on the seed layer 656 of the growth template 113 . Although the seed layer 656 is shown as a continuous film on the growth substrate 658 in some embodiments, i.e., the seed layer includes a plurality of "island" seed layers, RTI ID = 0.0 &gt; 658 &lt; / RTI &gt;

6D shows a semiconductor structure 680 including a growth template 113 having several layers of semiconductor structure 100 of FIGS. 1A and 1B deposited thereon. In particular, selective of the semiconductor structure _{(100) In n Ga 1 -} n N base layer 112, in this order on a growth template 112, InGaN spacer layer (118), InGaN well layer 114 is deposited epitaxially, Along with the InGaN barrier layer 116, the InGaN cap layer 120, the electron blocking layer 108, the p-type bulk layer 110 and the p-type contact layer 104, And is deposited in a tacky manner.

For example, using a metal organic chemical vapor deposition (MOCVD) process and a system in a single deposition chamber, that is, without the need for an unloading or unloading growth stack during a deposition process, The various layers of the substrate 680 may be deposited. In an embodiment of the present disclosure, wherein the growth template comprises a growth substrate, a Group III nitride nucleation layer 660 and a GaN seed layer, the entirety of the semiconductor layer 680 is grown in a single growth cycle, Can be formed on the growth substrate 658 without loading and unloading during the process.

The pressure in the deposition chamber may be reduced to between about 50 mTorr and about 500 mTorr. The pressure in the reaction chamber during the deposition process may be increased and / or decreased during deposition of the growth stack 682 and may be tailored for the particular layer being deposited. Non-limiting example, In _n Ga _{1 - n} N base layer 112, spacer layer 118, at least one well layer 114, one or more barrier layers 116, the cap layer 120 and the electron barrier layer The pressure of the reaction chamber during the deposition of the first chamber 108 can be in the range between about 50 mTorr and about 500 mTorr and in some embodiments can be equal to about 440 mTorr. The pressure in the reaction chamber for deposition of p-type bulk layer 110 and p-type contact layer 104 may be in the range of between about 50 mTorr and about 250 mTorr and in some embodiments about 100 mTorr &Lt; / RTI &gt;

The growth template 113 may be heated to a temperature between about 600 [deg.] C and about 1,000 [deg.] C in a deposition chamber. Metalorganic precursor gases and other precursor gases (and, optionally, carrier and / or purge gases) are then flowed through the deposition chamber and over one or more seed layers 656 of the growth template 113 . The metal organic precursor gas may undergo both reactive decomposition, or both reaction and decomposition, in a manner that results in epitaxial deposition of a Group II nitride layer, e.g., an InGaN layer, on the growth template 113.

As a non-limiting example, trimethylindium (TMI) can be used as a metal organic precursor for indium of InGaN, and triethylgallium (TMG) can be used as a metal organic precursor for gallium of InGaN, Triethylaluminum (TMA) can be used as a metal organic precursor for AlGaN, and ammonia can be used as a precursor for nitrogen in the Group III nitride layer. SiH ₄ can be used as a precursor for the introduction of silicon into InGaN when it is desired to be doped into Group III nitride n-type, and Cp 2 Mg (bis (cyclopentadienl) magnesium) Lt; RTI ID = 0.0 &gt; III &lt; / RTI &gt; nitride. It may be advantageous to match the ratio of the indium precursor (e.g., trimethyl indium) to a gallium precursor (e.g., triethyl gallium) that will result in indium contained in InGaN at a concentration near the saturation point for indium in the InGaN at the deposition temperature . The percentage of indium contained in InGaN can be controlled because the growth temperature is controlled to grow InGaN epitaxially. A relatively high amount of indium may be contained at a relatively low temperature and a relatively low amount of indium may be contained at a relatively high temperature. As a non-limiting example, the InGaN well layer 108 may be deposited at a temperature in the range of about 600 [deg.] C to about 950 [deg.] C.

The deposition temperatures of the various layers of the growth stack 100 may be increased and / or decreased during the deposition process, and thus may be tailored for the particular layer to be deposited. As a non-limiting example, the deposition temperature during deposition of In _n Ga _1-n N base layer 112, p-type bulk layer 110 and p-type contact layer 104 is about 600 ° and about 950 ° C And in some embodiments may be equal to about 900 &lt; 0 &gt; C. The growth rate of the In _n Ga _1-n N base layer 112, the p-type bulk layer 110 and the p-type contact layer 104 is about 1 nanometer / min (1 nm / min) nanometers / min (30 nm / min) can be in the range between and, in some embodiments, in _n Ga _1-n N base layer (112), p- type bulk layer 110 and the p- type contact The growth rate of layer 104 may be equal to about 6 nanometers / minute (6 nm / min).

In a further non-limiting exemplary embodiment, during deposition of the spacer layer 118, the at least one well layer 114, the at least one barrier layer 116, the cap layer 120, and the electron blocking layer 108, May be in a range between about 600 ° and about 950 ° C, and in some embodiments may be about 750 ° C. The growth rate of the spacer layer 118, the at least one well layer 114, the at least one barrier layer 116, the cap layer 120 and the electron blocking layer 108 is about 1 nm / min ) And about 30 nanometers / minute (30 nm / min), and in some embodiments may be in the range of a spacer layer 118, one or more well layers 114, one or more barrier layers 116, The growth rate of the layer 120 and the electron blocking layer 108 may be equal to about 1 nanometer per minute (1 nm / min).

In an embodiment involving the deposition of an InGaN layer, the flow rate ratio of the precursor gas may be selected to provide a high quality InGaN layer. For example, the method for forming the InGaN layer of the semiconductor structure 100 may include providing one or more InGaN layers having low defect density, substantially no stain relaxation, and substantially no surface pits And selecting a gas to gas ratio.

In a non-limiting example, the flow ratio (%) of trimethyl indium (TMI) to triethyl gallium (TMG)

, And such a flow rate ratio can be increased and / or reduced during the deposition process and can therefore be tailored for the particular InGaN layer to be deposited. Non-limiting example, In _n Ga _{1 -} flow rate of deposition for the _n N base layer 112 and a p- type bulk layer 110 may be in a range between about 50% and about 95 ℃, some In the embodiment, it may be equal to about 85%. In another embodiment, the flow rate ratio during deposition of the spacer layer 118, the at least one barrier layer 116 and the cap layer 120 may be in a range between about 1% and about 50% Lt; RTI ID = 0.0 &gt; 2%. &Lt; / RTI &gt; In yet another embodiment, the flow rate ratio during deposition of the one or more quantum well layers 114 can be in the range between about 1% and about 50%, and in some embodiments can be equal to about 30%.

The growth template 113 may optionally be rotated within the deposition chamber during the deposition process. As a non-limiting example, the growth template 113 may be rotated at a rotational speed between about 50 rpm (RPM) and about 1500 rpm (RPM) in a deposition chamber during the deposition process, and in some embodiments And can rotate at a rotational speed equal to the rotational speed per minute (RPM) of about 450 minutes. During the deposition process, the rotational speed can be increased and / or decreased during deposition, and thus can be tailored for the particular layer to be deposited. As a non-limiting example, the In _n Ga _{1 -n} N base layer 112, the spacer layer 118, the at least one well layer 114, the at least one barrier layer 116, the cap layer 120, 108 may be in the range between about 50 RPM and about 1500 RPM, and in some embodiments between about 440 RPM and about 440 RPM, And can be rotated at the same rotational speed. (RPM) of the growth template 113 during the deposition of the p-type bulk layer 110 and the p-type contact layer 104 to about 1500 rpm (RPM) And may, in some embodiments, be capable of rotating at a rotational speed such as about 1000 rpm (RPM).

In an embodiment of the semiconductor structure of the present disclosure, including the deposition of Group III nitride, and in particular an InGaN layer, the strain energy of one or more InGaN layers including the growth stack 682 epitaxially deposited on the growth template 113 Can affect the efficiency of a light emitting device manufactured with such a semiconductor structure. In some embodiments, the total strain energy occurring in the growth stack 682 may be related to the efficiency defined by the internal quantum efficiency (IQE) of the semiconductor structure of this disclosure.

More specifically, the strain energy stored in the n-th layer of InGaN is proportional to the average total thickness ( T _n ) of the n-th layer of InGaN and the concentration of indium ( % In _n ) of the n-th layer of InGaN. In addition, the total strain energy stored in the plurality of InGaN layers including the growth stack 682 is proportional to the sum of the average total thickness ( T _n ) of each of the InGaN layers and the concentration ( % In _n ) of indium in each of the InGaN layers , The total strain energy in the InGaN layer including the growth stack 702 can be estimated using the following equation:

,

,

In this case, the average total thickness ( T _n ) of the n-th layer is expressed in nanometers (nm) and the concentration ( % In _n ) of indium in the n-th InGaN layer is expressed in terms of atomic percentages. For example, if the n-th layer of InGaN has an average total thickness ( T _n ) of 150 nanometers (150 nm) and an indium concentration ( % In _n ) of 2.0 at%, the strain energy in the n- 300 au (300 = 150 (2)).

Figure 9 shows a graph 900 showing the relationship between IQE (au) and total strain energy (au) for the semiconductor structure of the present disclosure. The IQE of the semiconductor structure of the present disclosure can be reduced to the value of the total strain energy referred to as the "critical strain energy" of the semiconductor structure, as indicated by line 902 in graph 900. The IQE of the semiconductor structure below the critical strain energy (as shown by line 904) may be substantially greater than the IQE of the semiconductor structure above the critical strain energy (as indicated by line 906) Represent the IQE values for several semiconductor structures of the present disclosure (represented by a rectangle). In some embodiments, the IQE below the critical strain energy may be about 500% greater than the IQE above the critical strain energy. In another embodiment, the IQE below the critical strain energy may be about 250% greater than the IQE above the critical strain energy. In yet another embodiment, the IQE below the critical strain energy may be about 100% greater than the IQE above the critical strain energy.

For the semiconductor structure of this disclosure, the critical strain energy 902, defined by the sum of the product of the indium content (%) of each layer and the respective layer thickness (nm), is about 1800 Less than or equal to about 2800, or even less than or equal to about 4500.

A plurality of Group III nitride layers including the growth stack 682 of Figure 6D may be formed to substantially match the crystal lattice of the InGaN seed layer 656 of the growth template 113 As shown in FIG. In such an embodiment in which the growth stack 682 is substantially completely deformed, that is, grown substantially without strain relaxation, the growth stack inherits the lattice parameters of the InGaN seed layer. In certain embodiments of the present disclosure, the InGaN seed layer may exhibit a growth plane lattice parameter greater than 3.186 angstroms, and the growth stack may exhibit a growth plane lattice parameter of at least 3.186 angstroms. Thus, in a non-limiting example, the semiconductor structure 100, 200, 300, 400, 500 may be formed in a manner that consists of a completely deformed material, and may have such a growth plane lattice parameter.

6D may be deposited in a manner such that the growth stack 682 is partially relaxed, that is, a portion of the growth stack 682 of the growth stack 682 is partially relaxed. In other embodiments, a plurality of Group III nitride layers, including the growth stack 682 of FIG. 6D, The lattice parameters are different from the lower InGaN seed layer. In this embodiment, the percent strain relaxation ( R )

Where a is the average growth plane lattice parameter for the growth stack 682, a _s is the average growth plane lattice parameter of the InGaN seed, and a _l is the equilibrium (or natural state ) Average growth plane lattice parameter. For example, in some embodiments, the growth stack 682 may exhibit a percent strain relief ( R ) of less than about 0.5%, and in a further embodiment the growth stack 682 may exhibit a percent strain relief of less than about 10% ( R ), and in yet another embodiment the growth stack 682 may represent a percent strain relaxation ( R ) of less than about 50%.

After epitaxial deposition of several layers of a semiconductor structure comprising a Group III nitride material, further processing may be applied to complete the fabrication of the semiconductor structure with a light emitting device, such as an LED. For example, electrode contacts may be formed on a layer of Group III nitride material using processes known in the art and briefly described below with reference to FIGS. 7 and 8. FIG.

An example of a light emitting device 700, e.g., an LED, fabricated from semiconductor structure 100 is shown in FIG. It should be noted that although the following description describes an embodiment for fabricating a light emitting device from semiconductor structure 100, such fabrication processes may also be applied to semiconductor structures 200, 300, 400, 500.

In more detail, In _n Ga _{1 -} In some embodiments in which _n N base layer 112 can be removed to expose the GaN seed layer 656, a portion of the semiconductor structure 100 may be removed by, then in _n Ga _{1 -} to expose a portion of the _n n base layer 112. Removal of selected portions of the semiconductor structure 100 may be realized by applying a photosensitive chemical to the exposed surface of the p-contact layer 104 of the semiconductor structure 104 (not shown). Upon exposure of electromagnetic radiation through a patterned transparent plate and subsequent development (subsequent development), the photosensitive layer is In _n Ga _{1 -} "mask layer to allow the selective removal of Group III nitride layer on the _n N base layer 112 quot; mask layer &quot;. In _n Ga _{1 - n} N base layer 112 to remove the selected portion of the Group III nitride layer on the etching process, for example, wet chemical etch, and / or dry plasma-based etch (e.g., reactive ion etching, inductively coupled plasma Etch).

The first electrode contact 702 may be formed on a portion of the exposed In _n G _{1 -n} aN base layer 112. The first electrode contact 702 may be comprised of one or more metals, which may include titanium, aluminum, nickel, gold, and one or more of these metals. The second electrode contact 704 may be formed on a portion of the p-contact layer 104 and the second electrode contact 704 may be formed of one of nickel, gold, platinum, silver, Or more of the metal layer. In forming the first electrode contact 702 and the second electrode contact 704, the current may pass through the light emitting device 700 to generate electromagnetic radiation, for example, in the form of visible light. The light emitting device 700 is configured such that at least a portion of the current path between the first electrode contact 702 and the second electrode contact 704 includes a lateral pathway and thus is generally referred to in the art as "lateral device "). &lt; / RTI &gt;

Also, although the following description describes an embodiment of manufacturing a light emitting device from a semiconductor structure 100, a further example of a light emitting device 800, e.g., an LED, made of a semiconductor structure 100 is shown in FIG. It should be noted that such a manufacturing process may also be applied to the semiconductor structure 200, 300, 400, 500.

More specifically, all or a portion of the growth template 113 may be used to enable the exposure of the In _s Ga _{1 -s} N layer 656, or in some embodiments, to the In _n Ga _1-n N base layer 112 may be removed from the semiconductor structure 100 to enable exposure. Removal of all or part of the growth template 113 may include one or more removal methods including wet etching, dry etching, chemical mechanical polishing, grinding, and laser lift-off. Upon removal of all or part of the growth template 113, the first electrode contact 802 may be applied to the In _n Ga _1-n N base layer 112 as described above. The second electrode contact 804 may then be applied to a portion of the p-contact layer 104, thereby forming the light emitting device 800. In forming the first electrode contact 802 and the second electrode contact 804, the current may pass through the light emitting device 800 to generate electromagnetic radiation, for example, in the form of visible light. The light emitting device 800 is generally referred to in the art as a "vertical device" since the current path between the first electrode layer 802 and the second electrode layer 804 includes a substantially vertical pathway .

In addition to the fabrication methods and processes described above for the fabrication of non-limiting example light emitting devices 700 and 800, there may be used, for example, surface roughening, thermal dissipation, dicing flip-chip bonding "of bonding and other well-known manufacturing methods for dicing and metallurgical carriers to improve singulation, isolation, interconnection, and the like, It should be noted that additional methods and processes known in the art, such as processes known in the art, may also be used.

A light emitting device, such as an LED, according to an embodiment of the present disclosure may be fabricated and used with any type of light emitting device incorporating one or more LEDs therein. Embodiments of the presently disclosed LEDs may be particularly suitable for use in applications that operate at relatively high power and benefit from LEDs that require a relatively high luminous intensity. For example, the LEDs of this disclosure may be particularly suitable for use in LED lamps and LED-based bulbs that can be used for building lighting, street lighting, automotive lighting, and the like.

A further embodiment of the present disclosure includes a light emitting device that emits light comprising one or more of the LEDs described herein, such as the light emitting device 700 of FIG. 7 and the light emitting device 800 of FIG. As a non-limiting example, the light emitting device may be as described in U.S. Patent No. 6,600,175, issued July 29, 2003 to Baretz et al., The disclosure of which is incorporated herein by reference in its entirety But may include one or more LEDs as described herein.

FIG. 14 illustrates an exemplary embodiment of a light emitting device 900 of the present disclosure including a light emitting device such as devices 700, 800 described with reference to FIGS. 14, the light emitting device 900 may include a container 902, at least a portion of which is at least substantially transparent to electromagnetic radiation in the visible region of the electromagnetic radiation spectrum. The container 902 may comprise, for example, an amorphous or crystalline ceramic material (e.g., glass) or a polymeric material. The LED 800 is disposed within the container 902 and may be mounted on the support structure 904 (e.g., a printed circuit board or other substrate) within the container 902. The light emitting device 900 further includes a first electrical contact structure 906 and a second electrical contact structure 908. The first electrical contact structure 906 may be in electrical communication with one of the LED electrode contacts, e.g., the first electrode contact 802 (FIG. 8), and the second electrical contact structure 908 may be in electrical communication with another For example, a second electrode contact 804 (Figure 8). As a non-limiting example, the first electrical contact structure 906 may be in electrical communication with the first electrode contact 804 via the support structure 904 and the wire 910 may be in electrical contact with the second electrical contact structure 908 And may be used to electrically couple with the second electrode contact 804. The voltage thus provides a voltage and corresponding current between the first and second electrode contacts 802 and 804 of the LED so that the first electrical contact structure 906 of the light emitting device 900, And the second electrical contact structure 908.

The light emitting device 900 may optionally include one or more LEDs 800 in the container 902 for emitting fluorescence that emits electromagnetic radiation (e.g., visible light) when stimulated or excited by absorption of electromagnetic radiation emitted by the one or more LEDs 800 in the container 902 Or a fluorescent or phosphorescent material. For example, the inner surface 912 of the container 902 may be at least partially coated with such a fluorescent or phosphorescent material. The one or more LEDs 800 may emit electromagnetic radiation at one or more specific wavelengths and the fluorescent or phosphorescent material may comprise a mixture of various materials to emit radiation of various visible wavelengths, Emits white light out of the container 902. Various forms of phosphorescent and fluorescent materials are known in the art and may be employed in embodiments of the light emitting device of the present disclosure. For example, some such materials are disclosed in the aforementioned U.S. Patent No. 6,600,175.

Additional non-limiting examples of embodiments of the present disclosure are provided below.

Example 1: Base layer; A plurality of InGaN layers disposed on the base layer and including at least one well layer comprising In _w Ga _{1 - w} N and at least one barrier layer comprising In _b Ga _{1 - b} N, Wherein w is 0.10? W? 0.40 and b is 0.01? B? 0.10; An electron blocking layer disposed on the active region opposite to the base layer and comprising In _e Ga _{1 - e} N, wherein e is 0.00? E? 0.02; P- type disposed on the electron blocking layer In _p Ga _{1 - p} N bulk layer _{(p-type In p Ga 1} - p N bulk layer); And a p-type In _c Ga _{1 - c} N contact layer (p-type In _c Ga ₁ -C n N contact layer) disposed on the p-type In _p Ga _{1 - p} N bulk layer, p is 0.00? p? 0.08, and c is 0.00? c? 0.10.

Example 2: The base layer further comprises a growth template, the growth template comprising: a growth substrate; And a GaN seed layer disposed on the growth substrate, wherein the growth plane of the GaN seed layer comprises a pole plane.

Example 3: The base layer, n- type In _n Ga _{1 - n N} further includes a base layer, and at this time, n is the 0.01≤n≤0.10 embodiment the semiconductor structure of the first embodiment or the second example.

Example 4: In the active region and _sp Ga ₁ is disposed between the base layer _- N _sp spacer layer, and further comprising, at this time, sp is any one of a semiconductor structure of 0.01≤sp≤0.10 of Examples 1 to 3 .

Example 5: A semiconductor structure according to any one of Examples 1 to 4, further comprising: an In _cp Ga _{1 - cp} N cap layer disposed between the active region and the electron blocking layer, wherein 0.01? Cp?

Example 6: The semiconductor structure of Example 2 wherein the GaN seed layer has an average thickness of between about 1.0 占 퐉 and about 5 占 퐉.

Example 7: The semiconductor structure of Example 2 or Example 6 further comprising a Group III nitride nucleation layer disposed between the growth substrate and the GaN seed layer.

Embodiment 8: The semiconductor structure of any one of embodiments 1 to 7, wherein the active region has an average thickness between about 40 nm and about 750 nm.

Example 9: A semiconductor structure according to any one of Examples 1 to 8, wherein the electron blocking layer is composed of at least substantially GaN.

Example 10: A semiconductor structure according to any one of Examples 1 to 9, wherein the _p -type In _p Ga _{1 - p} N bulk layer has an average thickness of between about 50 nm and about 600 nm.

Example 11: The semiconductor structure of Example 10 wherein the _p -type In _p Ga _{1 - p} N bulk layer has an average thickness of about 175 nm.

Embodiment 12: A semiconductor structure according to any one of Embodiments 1 to 11, wherein the p-type In _c Ga _{1 - c} N contact layer is composed of at least substantially GaN.

Example 13: The semiconductor structure of any one of embodiments 1-12, wherein the critical strain energy of the semiconductor structure is about 1800 or less.

Example 14: Preparation of the base layer, the active area, an electron blocking layer, a p- type In _p Ga _{1 - p} N bulk layer, and the p- type In _c Ga _{1 - c} N contact layer, a lower percentage than the strain relief 10% Lt; RTI ID = 0.0 &gt; 1, &lt; / RTI &gt;

Example 15: A first electrode contact on at least a portion of a base layer; And a second electrode contact on at least a portion of the p-type contact layer.

Example 16: Base layer; An active region disposed over the base layer, the active region comprising a layer of a plurality of InGaNs comprising at least one well layer and at least one barrier layer disposed directly on the at least one well layer; An electron blocking layer disposed over the active region; A p-type In _p Ga _{1 - p} N bulk layer disposed on the electron blocking layer; And a p-type In _c Ga _{1 - c} N contact layer disposed on the p-type In _p Ga _{1 - p} N bulk layer, wherein the light emitting device has a critical strain energy of about 1800 or less,

Example 17: The base layer further comprises a growth template, wherein the growth template comprises a growth substrate, and a GaN seed layer disposed on the growth substrate, wherein the growth plane of the GaN seed layer comprises a planar (16).

Example 18: The light emitting device of Example 16 or Example 17 wherein at least one well layer comprises In _w Ga _{1 - w} N, wherein w is 0.10? W? 0.40.

Example 19: A light emitting device according to any one of Examples 16 to 18, wherein at least one barrier layer comprises In _b Ga _{1 - b} N, wherein b is 0.01 b 0.10.

Example 20: A light emitting device according to any one of Examples 16 to 19, wherein the electron blocking layer is made of at least substantially GaN.

Example 21: A light emitting device according to any one of Examples 16 to 20, wherein p in the p-type In _p Ga _{1 - p} N bulk layer is 0.01? P?

Embodiment 22: A light emitting device according to any one of Examples 16 to 21, wherein c in the p-type In _c Ga _{1 - c} N contact layer is 0.01? C?

Example 23: A light emitting device according to any one of Examples 16 to 22, wherein the p-type In _c Ga _{1 - c} N contact layer is substantially composed of GaN.

Example 24: A first electrode contact on at least a portion of a base layer; And a second electrode contact on at least a portion of the p-type In _c Ga _1-c N contact layer.

Growth represents the _p N bulk layer, and the p- type In _c Ga _1-c N contact layer, a small percentage strain relief than 1% with _- an active region, an electron blocking layer, a p- type In _p Ga _1: Example 25 Lt; RTI ID = 0.0 &gt; 16 &lt; / RTI &gt;

Example 26: Providing a base layer; Growing a layer of a plurality of InGaN to form an active region on the base layer; Growing an electron blocking layer on the active region opposite to the base layer; Growing a _p -type In _p Ga _{1 - p} N bulk layer on the electron blocking layer; And growing a p-type In _c Ga _{1 - c} N contact layer on the _p -type In _p Ga _{1 - p} N bulk layer, wherein p is 0.00? P? 0.08 and c is 0.00? wherein the step of growing a plurality of InGaN layers comprises growing at least one In _w Ga _{1 - w} N well layer and growing at least one In _b Ga _{1 - b} N barrier layer Wherein w is 0.10? W? 0.40 and b is 0.01? B? 0.10,

Example 27: Providing a base layer further comprises forming a growth template, said forming a growth template comprising: providing a growth substrate; and growing a GaN seed layer on the growth substrate , The growth plane of the GaN seed layer is the polar plane method of Example 26,

Example 28, comprising: providing a base layer, n- _n-type In Ga _{1 - n} N is carried further comprising the step of growing the base layer, and at this time, n is 0.01≤n≤0.10 Example 26 or Example 27.

Example 29: In _sp Ga ₁ disposed between the active region and the base _layer-step of growing a spacer layer _sp N; further comprising a, and this time, sp is any of the Examples 26 to 28 0.01≤sp≤0.10 One way.

Example 30: Growing an In _cp Ga _{1 - cp} N cap layer disposed between the active region and the electron blocking layer, wherein cp is greater than that of Examples 26 to 29 where 0.01? Cp? Either way.

Example 31: The method of embodiment 27 further comprising growing a GaN seed layer with an average thickness ranging from about 1.0 占 퐉 to about 7 占 퐉.

Example 32: The method of embodiment 27 or 31, wherein forming a growth template further comprises depositing a Group III nitride nucleation layer disposed between the growth substrate and the GaN seed layer.

Example 33: The method of any one of Examples 26 to 32 further comprising growing the active region to have an average thickness between about 40 nm and about 750 nm.

Embodiment 34: A method as in any of the embodiments 26-33, further comprising growing an electron blocking layer so as to be at least substantially composed of GaN.

Example 35: Growing a _p -type In _p Ga _1-p N bulk layer to have an average layer thickness between about 50 nm and about 600 nm. .

Example 36: at least substantially consists of a p- type to GaN In _c Ga _{1 - c} N step of growing a contact layer, Examples 26 to 35 The method as in any of further comprising: a.

Example 37: to define the growing stack showing a small percentage of the strain relief than 1% of the base layer, the active area, an electron blocking layer, a p- type In _p Ga _{1 - p} N bulk layer, and the p- type In _c Ga _{1 -} examples 26 to 36 the method as in any of further comprising a; _c N forming a contact layer.

Example 38: The method of embodiment 37 further comprising forming a growth stack to have a critical strain energy of about 1800 or less.

Example 39: An active region, an electron blocking layer, a p-type In _p Ga _{1 - p} N bulk in a single chemical vapor deposition system at pressures or pressures of between about 50 mTorr and about 500 mTorr examples 26 to 38 the method as in any of the further include; _- layer, and a p- type in _c Ga _{1 c} N contact layer growth step of each.

Example 40: Growing a _p -type In _p Ga _{1 - p} N bulk layer in a chamber while flowing trimethyl indium (TMI) and triethyl gallium (TMG) through a chamber, , The flow rate of trimethyl indium (TMI) versus the flow rate of triethyl gallium (TMG) (%) is between about 50% and about 95% Way.

The exemplary embodiment of the present disclosure set forth above does not limit the scope of the present invention because it is merely an example of an embodiment of the present invention which is defined by the scope of the appended claims and their legal equivalents to be. Any equivalent embodiment is intended to be within the scope of this invention. Indeed, various modifications of the present disclosure, other than those shown and described herein, such as alternative combinations of the described elements, will become apparent to those skilled in the art from the foregoing description. Such variations and embodiments are also intended to fall within the scope of the appended claims.

Claims (14)

As a semiconductor electroluminescent structure,
a base layer comprising an n-type doped layer;
Wherein disposed on the base layer, at least one of In _w Ga _1-w N well layer (well layer), and at least one of In _b Ga _{1 -} comprises a _b N plurality of InGaN layers including a barrier layer, wherein w is an active region in which 0.10? w? 0.40 and b is 0.01? b? 0.10;
An electron blocking layer disposed on the active region opposite to the base layer, the electron blocking layer including In _e Ga _{1 - e} N and e being 0.00? E? 0.02;
The electron blocking layer p- type In _p Ga ₁ disposed on _{- p} N bulk layer _{(p-type In p Ga 1} - p N bulk layer); And
It includes,; _c N contact layer _{(p-type In c Ga 1} -c N contact layer) the p- type In _p Ga _{1 - - p} N bulk layer p- type In _c Ga ₁ that is placed on top of
P is 0.00? P? 0.08, and c is 0.00? C? 0.10. The method according to claim 1,
The base layer may further comprise a growth template,
The growth template may comprise:
Growth substrate; And
And a GaN seed layer disposed on the growth substrate, wherein a growth plane of the GaN seed layer includes a polar plane. 3. The method of claim 2,
Wherein the growth template further comprises a Group III nitride nucleation layer disposed between the growth substrate and the GaN seed layer. The method according to claim 1,
The n- type doped layer, n- _n-type In Ga _{1 - n} and the N base layer, and the n is a semiconductor light emitting structure 0.01≤n≤0.10. The method according to claim 1,
Wherein the electron blocking layer is made of GaN. The method according to claim 1,
The p-type In _c Ga _{1 - c} N contact layer is made of GaN. The method according to claim 1,
The critical strain energy of the semiconductor structure is defined by the sum of the product of the respective layer thicknesses (nm) and the indium content (%) of each layer, and the critical strain energy of the semiconductor field Light emitting structure. A method of forming a semiconductor electroluminescent structure,
providing a base layer comprising an n-type doped layer,
Growing a layer of a plurality of InGaN to form an active region on the base layer;
Growing an electron blocking layer on the active region opposite the base layer;
Growing a _p -type In _p Ga _{1 - p} N bulk layer on the electron blocking layer; And
Growing a p-type In _c Ga _{1 - c} N contact layer on the p-type In _p Ga _{1 - p} N bulk layer,
P is 0.00? P? 0.08, c is 0.00? C? 0.10,
Wherein growing the plurality of InGaN layers comprises:
At least one of Ga _w In _{1 -} a step of growing the well layer _w N, and at least one, and comprising the step of growing a In _b Ga _1-b N barrier layer, wherein w is 0.10≤w≤0.40, the b Lt; = b &lt; / = 0.10. 9. The method of claim 8,
Wherein providing the base layer further comprises forming a growth template,
Wherein forming the growth template comprises:
Providing a growth substrate, and
And growing a GaN seed layer on the growth substrate, wherein the growth plane of the GaN seed layer is polar planar. 10. The method of claim 9,
Wherein the forming the growth template further comprises depositing a Group III nitride nucleation layer disposed between the growth substrate and the GaN seed layer. 9. The method of claim 8,
The step of providing the base layer comprising an n-type doped layer further comprises growing an _n -type In _n Ga _{1 -n} N base layer,
Wherein n is 0.01? N? 0.10. 9. The method of claim 8,
And forming a GaN electron blocking layer on the GaN barrier layer. 9. The method of claim 8,
On the p- type GaN In _c Ga _{1 - c} N contact layer growth step of; further comprising: a semiconductor light emitting structure, The method of forming a. 9. The method of claim 8,
Further comprising forming the semiconductor structure to have a critical strain energy that is defined by a sum of products of respective layer thicknesses (nm) and indium contents (%) of each layer, and having a critical strain energy of 1800 or less. / RTI &gt;

Images