KR102120682B1 - SEMICONDUCTOR LIGHT EMITTING STRUCTURE HAVING ACTIVE REGION COMPRISING InGaN AND METHOD OF ITS FABRICATION - Google Patents

Abstract

The semiconductor structure includes an active region between a plurality of InGaN layers. The active region may be composed of at least substantially InGaN. Layer of a plurality of InGaN is In _w Ga _{1 -} comprises at least one barrier layer containing an N _{b -} at least one well layer and at least one of In _b Ga ₁ in the vicinity of the well layer including a _w N. In some embodiments, the value of w in In _w Ga _1-w N of the well layer may be greater than or equal to about 0.10, or in some embodiments less than or equal to about 0.40, and In _b Ga of at least one barrier layer The value of b in _{1 - b} N is greater than about 0.01 and less than about 0.10. The method of forming a semiconductor structure involves growing such a layer of InGaN to form an active region of a light emitting device, such as an LED. The luminary device includes such an LED.

Description

A semiconductor structure having an active region containing InGaN, a method for forming such a semiconductor structure, and a light emitting device formed from such a semiconductor structure TECHNICAL FIELD

The present disclosure relates to a light emitting device manufactured from such a semiconductor structure having a semiconductor structure and an active region containing InGaN, a method for manufacturing such a light emitting device, and a device including such a light emitting device.

Light emitting devices, such as light emitting diodes (LEDs), are electronic devices that emit electromagnetic radiation in the form of visible light when a voltage is applied across the active area of the LED between the anode and cathode. LEDs typically include one or more layers of semiconductor material, in which electrons supplied from the anode and holes supplied from the cathode recombine. Because electrons and holes recombine within the active region of the LED, energy is released in the form of photons emitted from the active region of the LED.

LEDs can be manufactured to include a wide range of various types of semiconductor materials, including, for example, III-V semiconductor materials, and II-V semiconductor materials. The wavelength of light emitted from any particular LED is a function of the amount of energy emitted when electrons and holes recombine. Therefore, the wavelength of light emitted from the LED is a function of the relative difference in energy between the energy level of the electron and the energy level of the hole. The energy level of the electron and the energy level of the hole are at least partially a function of the composition of the semiconductor material, the doping form and concentration of the semiconductor material, reconstitution (ie crystal structure and orientation), and the quality of the semiconductor material where recombination of electrons and holes occurs to be. Accordingly, the wavelength of light emitted from the LED can be selectively adjusted by selectively adjusting the composition and composition of the semiconductor material in the LED.

It is known in the art to manufacture LEDs comprising III-V semiconductor materials, such as Group III nitride materials. Such group III nitride LEDs are known to emit radiation in the blue and green visible regions of the electromagnetic radiation spectrum, and are known to operate with relatively high power and luminosity.

This summary is provided to introduce a selection of concepts in a simplified form. This concept is described in more detail in the detailed description of the exemplary embodiment of the following disclosure. This summary is not intended to identify key features or basic features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In some embodiments, the present disclosure is In _n Ga ₁ having a polarity growth plane having a large growth in-plane lattice parameter greater than about 3.2 Angstroms (angstroms) _- comprises a semiconductor structure including the _n N base layer. The active region is disposed over the base layer, and the active region includes a plurality of InGaN layers. The plurality of InGaN layers includes at least one In _w Ga _{1 - w} N well layer, and at least one In _b Ga _{1 - b} N barrier layer, wherein b is 0.01≤b≤0.10, and at this time, w is 0.10≤w≤0.40. In the semiconductor structure is _n Ga _{1 -} p- type contact layer disposed on the p- type bulk layer, and the p- type bulk layer disposed on the electron blocking layer, an electron blocking layer disposed on the active region _n N base layer and the opposite side It further includes. When p- type bulk layer, comprising a In _p Ga N _p a, p is 0.00≤p≤0.08, p- type contact layer is In _c Ga _{1 - c} includes N, at this time, c is 0.00 ≤c≤0.10.

In a further embodiment, the present disclosure includes light emitting devices manufactured from such a semiconductor structure.

For example, in a further embodiment, the present disclosure is In _n Ga ₁ having a polarity growth plane having a large growth in-plane lattice parameter greater than about 3.2 Angstroms _- and a light emitting device including the _n N base layer. The active region is disposed over the base layer, and the active region includes a plurality of InGaN layers. The plurality of layers of InGaN includes at least one well layer and at least one barrier layer. Apparatus p- type In _p Ga ₁ disposed on the electron blocking layer, an electron blocking layer disposed on the active region _{- p} N bulk layer; And p- type In _p Ga _{1 - c} N further includes a contact layer _{- p} N bulk layer p- type In _c Ga ₁ that is placed on top. Moreover, the critical strain energy of the light emitting device may be about 4500 or less.

In another embodiment, the present disclosure includes a method of forming such a semiconductor structure and a light emitting device. For example, in some embodiments, the present disclosure includes a method of forming a semiconductor structure in which an In _n Ga _1-n N base layer having a polar growth plane having a growth plane lattice parameter greater than about 3.2 mm ₂ is provided. do. A plurality of InGaN layers are grown to form active regions over the base layer. The step of growing a plurality of InGaN layers comprises: growing at least one In _w Ga _{1 - w} N well layer, and growing at least one In _b Ga _{1 - b} N barrier layer on the at least one well layer. In this case, w is 0.10≤w≤0.40, and b is 0.01≤b≤0.10. The method comprises growing an electron blocking layer over the active region, growing a p-type In _p Ga _{1 - p} N bulk layer over the electron blocking layer, and p- over a p-type In _p Ga _{1 - p} N bulk layer. Further comprising the step of growing the type In _c Ga _{1 - c} N contact layer, wherein p is 0.00≤p≤0.08, c is 0.00≤c≤0.10.

1A is a simplified side view of a semiconductor structure including one or more InGaN well layers and one or more InGaN barrier layers in an active region of a semiconductor structure in accordance with embodiments of the present disclosure.
1B is a simplified diagram showing the relative difference in energy level of a conduction band in an energy band diagram for various materials of various layers of the semiconductor structure of FIG. 1A.
2A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A, but further comprising an electron stop layer between the base layer and the active region of the semiconductor structure.
2B is a simplified conduction band diagram for the semiconductor structure of FIG. 2A.
3A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A, but further including a strain relief layer between the base layer and the active region of the semiconductor structure.
3B is a simplified conduction band diagram for the semiconductor structure of FIG. 3A.
4A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A but further including an additional thin GaN barrier layer within the active region of the semiconductor structure.
4B is a simplified conduction band diagram for the semiconductor structure of FIG. 4A.
5A is a simplified side view of another semiconductor structure similar to the semiconductor structure of FIG. 1A, but further including a well overflow structure in the active region of the semiconductor structure.
5B is a simplified conduction band diagram for the semiconductor structure of FIG. 5A.
6A is a simplified top view of an intermediate semiconductor structure that can be employed to manufacture a growth template used in the manufacture of a semiconductor structure in accordance with an embodiment of the method of the present disclosure.
6B is a partial side cross-sectional view of the intermediate semiconductor structure of FIG. 6A.
6C is a partial side cross-sectional view of a growth template that can be employed to fabricate a semiconductor structure in accordance with an embodiment of the method of the present disclosure.
6D shows a layer of a growth stack epitaxially deposited on a growth template such as that of FIG. 6C.
7 is a partial side cross-sectional view of a light emitting device manufactured with a semiconductor structure according to an embodiment of the method of the present disclosure.
8 is a partial side cross-sectional view of a further light emitting device manufactured from a semiconductor structure according to an embodiment of the method of the present disclosure.
9 is a graph showing a relationship between total strain energy and internal quantum efficiency of a semiconductor structure formed according to an embodiment of the method of the present disclosure.
10A is a simplified side view of a known LED comprising an InGaN well layer and a GaN barrier layer in the active area of the LED.
10B is a simplified conduction band diagram for the LED of FIG. 10A.
FIG. 11A is a graph showing calculated band edges for valence bands and conduction bands by zero applied voltage across the active area of the LED of FIG. 10A, and calculations are obtained using a calculation model of the LED.
11B is a graph similar to that of FIG. 11A, but showing the calculated band edges for valence and conduction bands with a current density of 125 A/cm ² flowing across the active area of the LED due to the applied voltage of the active area. .
FIG. 11C is a graph showing the calculated intensity of emitted radiation as a function of wavelength for each InGaN quantum well layer in the LED of FIG. 11A.
11D is a graph showing carrier injection efficiency calculated as a function of current density applied across the active area of the LED of FIG. 11A.
12A is a simplified side view of the LED of the present disclosure similar to that of FIG. 1A and including an InGaN well layer and an InGaN barrier layer in the active area of the LED.
12B is a simplified conduction band diagram of the LED of FIG. 12A.
13A is a graph showing calculated band edges for valence and conduction bands with zero applied voltage across the active area of the LED of FIG. 12A, and calculations are obtained using the calculation model of the LED.
13B is a graph similar to FIG. 13A, but showing the calculated band edges for valence and conduction bands with a current density of 125 A/cm ² flowing across the active area of the LED due to the applied voltage across the active area. .
13C is a graph showing the calculated intensity of emitted radiation as a function of wavelength for each InGaN quantum well layer in the LED of FIG. 13A.
13D is a graph showing carrier injection efficiency calculated as a function of applied current density across the active area of the LED of FIG. 13A.
13E is a graph showing the calculated internal quantum efficiency as a function of the calculated current density across the active area of the LED of FIG. 13A.
14 shows an example of a light emitting device comprising an LED of the present disclosure.

The examples presented herein are not meant to represent the actual appearance of any particular semiconductor material, structure, or device, but are merely an ideal expression used to describe embodiments of the disclosure.

1A shows an embodiment of a semiconductor structure 100. The semiconductor structure 100 includes a plurality of Group III nitride layers (eg, indium nitride, gallium nitride, aluminum nitride, and alloys thereof) and a base layer 102 ), p-type contact layer 104 and active region 106 disposed between base layer 102 and p-type contact layer 104, active region 106 including a plurality of layers of InGaN ). In addition, the active region 106 includes at least one InGaN well layer and at least one InGaN barrier layer. In some embodiments, the active region 106 (if there is no dopant present) may be composed of at least substantially InGaN. The semiconductor structure 100 includes an electron blocking layer 108 disposed over the active region 106, a p-type bulk layer 110 disposed over the electron blocking layer 108, and p The p-type contact layer (104) disposed on the -type bulk layer 110 is further included.

Base layer 102 In _n Ga _{1 -} growth plane of the _n N base layer may comprise 112 At this time, In _n Ga _1-n N base layer 112 is about 3.2 angstroms (angstroms) It is a polar plane with a larger growth plane lattice parameter. A light emitting device, such as a light emitting diode, can be fabricated from the semiconductor structure 100, as described in detail later herein. However, in simple terms, the first electrode contact (electrode contact) is In Ga _{n 1 - n} can be formed on a part of the N base layer 112 and the second electrode contact is formed on a part of the p- type contact layer 104 Can be, and as a result, an electrical voltage can be supplied across the active region 106 between the electrode contacts, whereby electromagnetic radiation (eg, visible light) is emitted from the semiconductor structure 100. To be released from the device.

Embodiments of semiconductor structures of the present disclosure, comprising an active region comprising at least one InGaN well layer and at least one InGaN barrier layer, are various types of methods for growing or forming a Group III nitride layer, such as InGaN. It can be prepared using. By way of non-limiting example, several Group III nitride layers may include chemical vapor deposition (CVD) processes, metalorganic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE). Process, atomic layer deposition (ALD) process, hybrid vapor phase epitaxy (HVPE) process, molecular beam epitaxy (MBE) process, atomic layer deposition (ALD) ) Process, chemical beam epitaxy (CBE) process, or the like.

In some embodiments, in the name of Letertre, U.S. Patent Application Publication No. US 2010/0176490 A1, published on July 15, 2010, U.S. Patent Application published on May 6, 2010 in the name of Arena Publication No. US 2010/0109126, US patent application published on August 23, 2012 in the name of Figuet Publication No. US 2012/0211870, and US patent published on September 6, 2012 in the name of Figuet The method disclosed in one or both of US Publication No. US 2012/0225539 can be used to grow or otherwise deposit several layers of Group III nitride. Such a method may enable the production of a Group III nitride layer, such as an InGaN layer (and other optional Group III nitride layers) having the composition and thickness described below. This method can then be used to form a growth template (113) in which a group III nitride layer can be formed.

An example of such a method that can be used to prepare a growth template 113 according to embodiments of the present disclosure is briefly described below with reference to FIGS. 6A-6C.

6A is a top view of intermediate semiconductor structures 650 used in the formation of the growth template 113 (of FIG. 1A) in which one or more semiconductor structures of the present disclosure and subsequent light emitting devices can be fabricated, 6B is a simplified cross-sectional view of a portion of the intermediate semiconductor structure 650 used to form the growth template 113. The growth template 113 can be made as disclosed in US Patent Application Publication No. US 2010/0176490 A1 and/or US Patent Application Publication No. US 2010/0109126 mentioned above. As disclosed therein, the intermediate semiconductor structure 650 is disposed on a sacrificial substrate 652, a layer of compliant material 654 disposed on the sacrificial substrate 652, and over the flexible material 654 It may include one or more In _s Ga _{1 - s} N seed layer (seed layer) 656 each comprising a layer of a group III nitride material. One or more In _s Ga _{1 - s} N seed layer 656 may be used as that can be formed and then the various layers of the semiconductor structure 100 "seed (seed)" described herein.

An initial In _s Ga _{1 - s} N seed layer may be formed on the initial growth substrate, after which ion implantation, bonding, and subsequent separation (subsequent) of a portion of the initial In _s Ga _1-s N seed layer (not shown) separation) may be transferred to the sacrificial substrate 652. It characterized by having a _s N seed layer and the growth plane lattice mismatch (growth plane lattice mismatch) _- initial growth substrate, In _s Ga _{1 - s} N seed layer is stained method (stained manner) to the factory In _s Ga ₁ to form It may include a growth substrate. For example, the initial growth substrate may include a sapphire substrate including a gallium polar GaN seed layer, and the resulting In _s Ga _{1 - s} N seed layer is tensile strained gallium polarity In _s Ga _{1 - s} N And a seed layer.

The initial In _s Ga _{1 - s} N seed layer can be formed or grown such that the In _s Ga _{1 - s} N seed layer includes a growth plane comprising a polar plane of group III-nitride. have. For example, the growth plane can be formed such that the In _s Ga _{1 - s} N seed layer comprises a gallium-polar plane. In addition, the initial In _s Ga _{1 - s} N seed layer may be grown or formed such that the composition of the In _s Ga _{1 - s} N seed layer is 0.05 ≤ _s ≤ 0.10. The In _s Ga _{1 - s} N seed layer can also be grown or formed to a thickness greater than about 200 nanometers (200 nm). However, the In _s Ga _{1 - s} N seed layer has an In _s Ga _{1 - s} N seed layer critical thickness, which is the thickness at which strain in the In _s Ga _{1 - s} N seed layer is mitigated by the formation of additional defects. _{The s} Ga _{1 - s} N seed layer is formed in a manner that does not exceed. This phenomenon is commonly referred to in the art as phase separation. Therefore, the In _s Ga _{1 - s} N seed layer can include a modified high quality seed material.

By way of example and not limitation, a process known in the industry as a SMART-CUT process uses an In _s Ga _{1 - s} N seed layer 656 on the sacrificial substrate 652 using a layer of flexible material 654 as a bonding layer. ). Such processes include, for example, US Patent No. RE39,484 by Bruel, US Patent No. 6,303,468 by Aspar, etc., US Patent No. 6,335,258 by Aspar, etc. , Aspar et al., 6,946,365.

The sacrificial substrate 652 may include a homogenous material or a heterogeneous (ie, composite) material. As a non-limiting example, the support substrate 652 may include sapphire, silicon, group III-arsenides, quartz (SiO ₂ ), fused silica (SiO ₂ ) glass, glass-ceramic composite material ( Fused silica glass composites (e.g. SiO ₂ -TiO ₂ or Cu ₂ ), e.g. of PA, for example under the trademark ZERODUR®, sold by Schott North America, Inc. of Dureya -Al ₂ O ₃ -SiO ₂ ), aluminum nitride (AlN), or silicon carbide (silicon carbine, SiC).

The layer of flexible material 654 may include, for example, a material having a glass transition temperature (T _g ) lower than or equal to about 800°C. The layer of flexible material 654 can have a thickness ranging from about 0.1 μm to about 10 μm, particularly about 1 μm to about 5 μm. As a non-limiting example, the layer of the flexible material 100 may be oxide, phosphosilicate glass (PSG), borosilicate (BSG), borophosphosilicate glass (BPSG), polyimide ( polyimide, doped or undoped quasi-inorganic siloxane spin-on-glass (SOG), inorganic spin-on-glass (ie methyl-, ethyl-, phenyl -, or butyl), and at least one of doped or undoped silicate.

To _s N seed layer 656 reflow (reflow) a layer of flexible material (654) to relieve crystal lattice strain, at least in part _- flexible layer, for example one or more of In _s Ga ₁ of the material (654) In order to be able to reduce the viscosity of the layer of flexible material 654 to a temperature sufficient to, for example, it can be heated using an oven, furnace, or deposition reactor. By reducing the viscosity of the layer of flexible material 654, the tensile strain in the In _s Ga _1-s N seed layer 656 can be at least partially relaxed or even eliminated, whereby about An In _s Ga _{1 - s} N seed layer 656 comprising a growth plane lattice parameter greater than 3.2 Angstroms is formed.

For at least partial relaxation of one or more In _s Ga _{1 - s} N seed layers 656, In _s Ga _{1 -s} N seed layer 656 can be transferred to a support substrate, after which the flexible material 654 And the sacrificial substrate 652 can be removed to form a growth template 113 as shown in FIGS. 1A and 6C. In more detail and with reference to FIGS. 6B and 6C, at least partially relaxed In _s Ga _{1 - s} N seed layer 656 can be attached to the support substrate 658, sacrificial substrate 652 and flexible material ( 654) can be removed using one or more of methods such as laser lift-off, wet etching, dry etching, and chemical mechanical polishing.

The support substrate 658 can include a homogeneous material or a heterogeneous (ie, composite) material. As a non-limiting example, the support substrate 658 may be sapphire, silicon, group III-arsenide, quartz (SiO ₂ ), fused silica (SiO ₂ ) glass, glass-ceramic composite materials (eg, trademark ZERODUR ® of PA, sold by Schott North America, Inc. of Dureya, fused silica glass composites (e.g. SiO ₂ -TiO ₂ or Cu ₂ -Al ₂ O ₃ -SiO ₂ ), aluminum nitride (AlN), or silicon carbide (SiC).

6C, in some embodiments, growth template 113 may optionally include a layer of dielectric material 660 overlying support substrate 100. Layer of dielectric material 660 is selectively major surface of the supporting substrate 658 or one or more of In _s Ga _{1 -} may be formed on _s N seed layer 656, at this time, the dielectric material 660, a support substrate ( It is used as a bonding layer for promoting the bonding of the In _s Ga _{1 - s} N seed layer 656 to 658). The layer of dielectric material 660 may include, for example, silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ), or silicon dioxide (SiO ₂ ) , For example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Therefore, the growth template 113 includes a support substrate 658 and an In _s Ga _{1 - s} N seed layer 656 disposed on the support substrate 658 and as shown in FIGS. 1A and 6C.

In addition, the In _s Ga _{1 - s} N seed layer 656 can be formed over the support substrate 658, so that the composition of the In _s Ga _{1 - s} N seed layer 656 is in the range of 0.05 ≤ s ≤ 0.10. It can be. Moreover, the In _s Ga _1-s N seed layer 656 can have a polar growth plane 662 that includes growth plane lattice parameters greater than about 3.2 Angstroms. The In _s Ga _{1 - s} N seed layer can also be formed with a total layer thickness ( T _s ) greater than about 100 nanometers (100 nm).

The growth template 113 forms part of the base layer 102 of FIG. 1A. The base layer may, in some embodiments, also include an In _n Ga _{1 - n} N base layer 112, where the In _n Ga _{1 - n} N base layer is adjacent to an In _s Ga _{1 - s} N seed It inherits the crystal properties of the layer 656. Therefore, In _n Ga _{1 -} may be _n N base layer 112 also includes a polarity growth plane as the growth plane having a larger lattice parameter than about 3.2 Angstroms, and gallium polarity growth plane.

In _n Ga _{1 - n} N base layer 112 is In Ga _{n 1 -} may comprise a layer of N _n, At this time, n is in the 0.00≤n≤0.10 and, or some embodiments, 0.02≤n ≤0.08. In one specific non-limiting example, n can be equal to about 0.05. The In _n Ga _1n N base layer 112 is between about 10 nanometers (10 nm) and about 3000 nanometers (3,000 nm), or, in some embodiments, about 10 nanometers (10 nm) and about 1000 nanometers. It can have an average layer thickness ( T _n ) between meters (1,000 nm). Alternatively, In _n Ga _{1 - n N} base layer 112 may be doped. For example, In _n Ga _{1 - n} N base layer 112 may be doped with n- type by the element electron donors, such as silicon or germanium doped. In _n Ga _{1 -} concentration of the dopant (dopants) in the _n N base layer 112 is about ¹⁷ 3e cm ^-3 to about 1e ²⁰ cm ^-3 , or, in some embodiments, the concentration of dopants in the In _n Ga _{1 - n} N base layer 112 is about 5e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 .

In order to manufacture a light emitting device from the semiconductor structure 100, the first electrode contact forms one or more of several other layers of the semiconductor structure 100 including InGaN, and then the In _n Ga _1-n N base layer 112 ).

The completed base layer 102, as shown in Fig. 1a, growth template 113 and the In _n Ga ₁ as described herein above _- include _n N base layer 112. Various Group III nitride layers of semiconductor structure 100 may be grown or formed in a layer-by-layer process, which is described in more detail later herein. In some embodiments, the base layer 102 may include a base on which other layers of the semiconductor structure 100 can be grown or formed. Thus, the various Group III nitride layers of the semiconductor structure 100 sequentially start with the base layer 102, although the base layer 102 may be oriented to be actually placed on the bottom during manufacturing. Thus, it can be grown or formed, and can be moved from left to right from the perspective view of FIG. 1A. In other words, the structure can be oriented 90 degrees counterclockwise in the direction of FIG. 1A during manufacture.

As discussed in more detail below, the active region 106 is disposed between the base layer 102 and the p-type contact layer 104. Active region 106 includes at least one InGaN well layer 114 and at least one InGaN barrier layer 116. In some embodiments, the active region 106 (if no dopant is present) may be composed of at least substantially InGaN, and the indium content of the InGaN well layer 114 is strictly greater than that of the InGaN barrier layer 116. more. In particular, the active region 106 is In _w Ga _{1 -} may comprise at least one well layer 114 containing N _w, at this time, and w is 0.10≤w≤0.40, or in some embodiments , 0.12≤w≤0.25, or in another embodiment, w is equal to about 0.14. Active region 106 also includes at least one barrier layer 116 comprising In _b Ga _{1 - b} N, where b <w, 0.01 ≤ b ≤ 0.10, or in some embodiments , 0.03≤b≤0.08, or in other embodiments b is equal to about 0.05. In some embodiments, InGaN barrier layer 116 may be near (eg, immediately adjacent to) at least one InGaN well layer 114.

The active region 106 of the semiconductor structure is a region of the semiconductor structure that, when fabricated in a light emitting device such as a light emitting diode (LED), electrons and holes recombine with each other to produce photons, emitted from the LED. In some embodiments, photons are emitted in the form of visible light. At least a portion of the visible light may have wavelengths or wavelengths within the electromagnetic radiation spectrum range from about 380 nanometers (380 nm) to about 560 nanometers (560 nm).

As previously mentioned, the active region 106 of the semiconductor structure 100 includes one or more InGaN well layers 114 and one or more InGaN barrier layers 116, and in some embodiments (if no dopant is present ) Can be at least substantially made of InGaN. Thus, the active region 106 may consist essentially of InGaN in some embodiments. Active region 106 is one of the well layer 114, and one comprising a pair of layers of one or more adjacent including a barrier layer 116, and this time, each of the well layer 114 is In _w Ga _{1 - w} n, wherein w is 0.10 ≤ w ≤ 0.40, and each barrier layer 116 includes In _b Ga _1-b N, where b is 0.01 ≤ b ≤ 0.10, b <w.

1A and 1B, although in a further embodiment, the active region 106 of the semiconductor structure 100 may include one or more pairs of active layers, but the activity of the semiconductor structure 100 Region 106 includes one (1) pair of active layers (well layer 114 and barrier layer 116). For example, in the active region 106 of the semiconductor structure 100, one to twenty-five (25) active layers can include adjacent pairs, each pair comprising a well layer 114 and a barrier layer ( 116), and as a result, the active region 106 includes a stack of alternating well layers 114 and barrier layers 116 (in embodiments that include one or more pairs). However, it is understood that the number of barrier layers 116 may not be the same as the number of well layers 114. The well layer 114 can be separated from each other by the barrier layer 116. Accordingly, the number of barrier layers 116 may be the same as the number of well layers 114, one more, or one less in some embodiments.

1A, each well layer 114 is between about 1 nanometer (1 nm) and about 1000 nanometers (1,000 nm), about 1 nanometer (1 nm) and about 100 nanometers (100 nm) ) you may have between, or even from about 1 nanometer (1 nm) and the average thickness (T _W) of between about 10 nanometers (10 nm). The well layer 114 may include quantum wells in some embodiments. In such an embodiment, each well layer 114 may have an average layer thickness ( T _W ) of about 10 nanometers (10 nm) or less. In other embodiments, well layer 114 may not include quantum wells, and each well layer 114 may have an average layer thickness ( T _W ) greater than about 10 nanometers (10 nm). . In such an embodiment, the active region 106 may include what is referred to in the art as a “double heterostructure”. Each barrier layer 116 is between about 1 nanometer (1 nm) and about 50 nanometers (50 nm), or even about 1 nanometer, although the barrier layer 116 in other embodiments may be thicker. It can have an average layer thickness ( T _B ) between (1 nm) and about 10 nanometers (10 nm).

One or both of well layer 114 and barrier layer 116 may be doped. For example, one or both of well layer 114 and barrier layer 116 may be doped n-type by doping with elements such as silicon or germanium, which are electron donors. The concentration of dopant in the well layer 114 is about ¹⁷ cm ^-3 to 3e may be in the range of about 1e ¹⁹ cm ^-3, or in some embodiments about 3e ¹⁷ cm ^-3 to about ¹⁷ cm 5e ^{- It} can be in the range of ³ . Similarly, the concentration of dopant in the barrier layer 116 can range from about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 , or in some embodiments from about 1e ¹⁸ cm ^-3 to about 3e ^It can be in the range of ¹⁸ cm ^-3 .

One or both of the well layer 114 and the barrier layer 116 may have a wurtzite crystal structure. Additionally, in some embodiments, one or both of the well layer 114 and the barrier layer 116 are parallel to the interface or interface between the well layer 114 and the barrier layer 116 greater than about 3.2 Angstroms. It may include a polar growth surface, such as a gallium polar growth surface, which may have an average lattice constant in one growth plane. More specifically, in some embodiments, the average growth plane lattice constant c may be between about 3.2 Angstroms and about 3.3 Angstroms.

The active region 106 comprising at least one well layer and at least one barrier layer is between about 40 nanometers (40 nm) and about 1000 nanometers (1,000 nm), about 40 nanometers (40 nm) and about It can have an average overall thickness between 750 nanometers (750 nm), or even between about 40 nanometers (40 nm) and about 200 nanometers (200 nm).

With continued reference to FIG. 1A, the semiconductor structure 100 has an additional layer between the active region 106 and the p-type contact layer 104 and/or between the active region 106 and the base layer 102. Can optionally include. For example, in some embodiments, the semiconductor structure 100 may include a spacer layer 118 between the active region 106 and the base layer 102.

The optional spacer layer 118 can include a layer of In _sp Ga _{1 - sp} N, where sp is 0.01 ≤ sp ≤ 0.10, or 0.03 ≤ sp ≤ 0.06, or sp is equal to about 0.05 . Between _n N base layer 112 different-composition layer and the base layer 102, the active region 106, which may have (and thus, different lattice parameters) for _the-spacer layer 118 is I _n Ga ₁ It can be used to provide a more gradual transition. Thus, the In _sp Ga _{1 - sp} N spacer layer 118 may be disposed directly between the base layer 102 and the active region 106 in some embodiments. By providing a more gradual transition between the base layer 102 and the active region 106, stress in the crystal lattice of the various layers of InGaN, and thus defects that can be attributed to such stress, can be reduced. The In _sp Ga _{1 -sp} N spacer layer 118 is between about 1 nanometer (1 nm) and about 100 nanometers (100 nm), or even about 1 nanometer (1 nm) and about 100 nanometers (25 nm). It may have an average layer thickness ( T _sp ) between. As one specific non-limiting example, the average layer thickness T _sp may be equal to about 10 nanometers (10 nm).

Optionally, the In _sp Ga _{1 - sp} N spacer layer 118 can be doped. For example, the In _sp Ga _1-sp N spacer layer 118 may be doped by elemental doping such as silicon or germanium, which is an n-type electron donor. The concentration of dopant in the spacer layer 118 is about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 . As one particular non-limiting example, the spacer layer 118 may have a concentration of dopant therein, such as about 2e ¹⁸ cm ^-3 .

1A, the semiconductor structure 100 further includes an optional In _cp Ga _{1 - cp} N cap layer 120 disposed between the active region 106 and the p-type contact layer 104. can do. Optional In _cp Ga _{1 - cp} N cap layer 120 may include a layer of In _cp Ga _{1 - cp} N, where cp is 0.01 ≤ cp ≤ 0.10, or 0.03 ≤ cp ≤ 0.07. As one specific non-limiting example, the value of cp may be equal to about 0.05. The In _cp Ga _{1 - cp} N cap layer 120 can be used to avoid dissolution and/or evaporation of indium in the underlying layers of the active region 106 upon subsequent treatment at elevated temperatures. And/or function the same as the spacer layer.

In _cp Ga _{1 - cp} N cap layer 120 is between about 1 nanometer (1 nm) and about 100 nanometers (100 nm), or about 1 nanometer (1 nm) and about 25 nanometers (25 nm) It may have an average layer thickness ( T _cp ) between. As one specific non-limiting example, T _cp may be equal to about 10 nanometers (10 nm). Optionally, the cap layer 120 can be doped. For example, the cap layer 120 may be doped p-type by doping elements such as magnesium, zinc, and carbon, which are electron acceptors. However, in other embodiments, the cap layer 120 may be doped n-type. The concentration of dopant in the cap layer 120 may be in the range of about 3e ¹⁷ cm ^-3 to about 1e ¹⁹ cm ^-3 , or in the range of about 1e ¹⁸ cm ^-3 to about 5e ^{18 ,} cm ^-3 . have. As one particular non-limiting example, the concentration of dopant in the cap layer 120 may be equal to about 2e ¹⁸ cm ^-3 .

The semiconductor structure 100 of the present disclosure may further include one or more electron blocking layers (EBLs) disposed between the active region 106 and the p-type contact layer 104. Such an electron blocking layer has an active energy level of a band edge of a conduction band, which can act to confine electrons in the active region 106 and prevent carrier overflow from the active region 106 It may include a relatively high material compared to the band edge of the conduction band in region 106.

As a non-limiting example, FIG. 1A shows the electron blocking layer 108 over the cap layer 120 opposite the active region 106. In an embodiment that includes a p-type bulk layer 110, the electron blocking layer 108 can be disposed directly between the cap layer 120 and the p-type bulk layer 110, as shown in FIG. 1A. .

The electron blocking layer 108 includes Group III nitride. As a non-limiting example, the electron blocking layer 108 (if no dopant is present) may be at least substantially comprised of In _e Ga _{1 - e} N, where 0.00≤e≤0.02, and some embodiments In, at least (if no dopant is present) can be substantially comprised of GaN. In another embodiment, the electron blocking layer 108 may be composed of at least substantially Al _e Ga _{1 - e} N, wherein 0.00≤e≤0.20. In some embodiments, the electron blocking layer 108 (if no dopant is present) can be at least substantially comprised of Al _e Ga _1-e N.

The electron blocking layer 108 may be doped p-type with one or more dopants selected from the group consisting of magnesium, zinc, and carbon. The concentration of the one or more dopants in the electron blocking layer 108 may range from about 1e ¹⁷ cm ^-3 to about 1e ²¹ cm ^-3 _, or in some embodiments equal to about 3e ¹⁹ cm ^{- 3} . . In some embodiments, the electron blocking layer 108 can have an average layer thickness ( T _e ) in a range from about 5 nanometers (5 nm) to about 50 nanometers (50 nm), or in some embodiments For, it may have an average layer thickness ( T _e ), such as about 20 nanometers (20 nm).

In a further embodiment of the semiconductor structure 100 of the present disclosure, the semiconductor structure 100 may have an electron blocking layer similar to the electron blocking layer 108, wherein the electron blocking layer is an inset ( 122, it has a superlattice structure comprising alternating layers of various materials. For example, the electron blocking layer 108 may have a superlattice structure including alternating layers of GaN 124 and In _e Ga _{1 - e} N 124, where e is 0.01 ≤ e ≤ 0.02 to be. In another embodiment, the electron blocking layer may have a superlattice structure including alternating layers of GaN 124 and Al _e Ga _{1 -e} N 126, where e is 0.01≤e≤0.20 . In such a superlattice structure, each layer may have an average layer thickness of about 1 nanometer (1 nm) to about 20 nanometers (20 nm).

As previously mentioned, the semiconductor structure 100 of the present disclosure may further include a p-type bulk layer 110 disposed between the electron blocking layer 108 and the p-type contact layer 104. Such a p-type bulk layer may include a p-doped group III nitride material, such as p-doped In _p Ga _1-p N. Such a p-type bulk layer can be used, for example, as a source of hole carriers and to improve electrical conductivity and light extraction to and from the active region 106. Inclusion of indium in the p-type bulk layer 110 can aid in carrier flow synchronization, and confinement of carriers in the active region.

The p-type bulk layer 110 (if no dopant is present) may be at least substantially composed of In _p Ga _{1 -p} N, where 0.00≤p≤0.08, preferably 0.01≤p≤ 0.08. As one specific non-limiting example, p-type bulk layer 110 may be at least substantially composed of In _p Ga _1-p N, where p is equal to about 0.02. The p-type bulk layer 110 may be doped p-type by one or more dopants selected from the group consisting of magnesium, zinc, and carbon. The concentration of one or more dopants in the p-type bulk layer 110 can range from about 1e ¹⁷ cm ^-3 to about 1e ²¹ cm ^-3 . As one specific non-limiting example, the concentration of dopant in p-type bulk layer 110 may be equal to about 3e ¹⁹ cm ^-3 . In some embodiments, the p-type bulk layer 110 may have an average layer thickness ( T _bk ) ranging from about 50 nanometers (50 nm) to 600 nanometers (600 nm). As one specific non-limiting example, the average layer thickness ( T _bk ) may be equal to about 175 nanometers (175 nm).

The semiconductor structure 100 may further include a p-type contact layer 104 disposed on the p-type bulk layer 110 opposite to the electron blocking layer 108. The p-type contact layer 104 may include Group III nitride. Such a p-type contact layer can be used, for example, to improve the conductivity of holes to the active region 106. The p-type contact layer 104 is a high concentration of one or more dopants, such as p-type dopants, to limit the electrical resistance of the electrode contacts formed over a portion of the p-type contact layer during manufacture of the light emitting device from the semiconductor structure 100 It may include.

As a non-limiting example, p- type contact layer 104 is an In _c Ga ₁ doped with p- type _may include the N _c. For example, the p-type contact layer 104 (if no dopant is present) may be at least substantially comprised of In _c Ga _{1 - c} N, where 0.01≤c≤0.10, and some embodiments In, the p-type contact layer 104 (if no dopant is present) can be at least substantially comprised of GaN. The inclusion of indium in the p-type contact layer 104 is helpful in that it creates a low operating voltage for the device and can reduce the energy barrier by the metal electrode formed on the device. do. The p-type contact layer 104 may be p-type doped by one or more dopants selected from the group consisting of magnesium, zinc, and carbon. The concentration of one or more dopants in the p-type contact layer 104 can range from about 1e ¹⁷ cm ^-3 to about 1e ²¹ cm ^-3 . As one specific non-limiting example, the concentration of one or more dopants in the p-type contact layer 104 may be equal to about 1e ²⁰ cm ^-3 . The p-type contact layer 104 may have an average layer thickness T _c ranging from about 2 nanometers (2 nm) to about fifty nanometers (50 nm). As one specific non-limiting example, the average layer thickness T _c may be equal to about 15 nanometers (15 nm). As shown in FIG. 1A, the p-type contact layer 104 may be formed directly over the p-type bulk layer 110.

As described in more detail below, the completed semiconductor structure 100 can be used in the manufacture of one or more semiconductor light emitting devices, such as LEDs. In short, the electrode contact is over a part of the semiconductor layer of the base layer 102, for example, In _n Ga _{1 - c N} can be formed over part of the base layer 112, the addition of electrode contacts are p- type contact layer ( 104 may be formed over a portion of the charge carrier, allowing charge carriers to be injected into the active region 106 with a resultant emission resulting from electromagnet radiation, which may be in the form of visible light.

1B is a simplified diagram showing the energy levels (in the energy band diagram) of the conduction band 128 for various semiconductor materials in the various layers of the semiconductor structure 100 of FIG. 1A (support substrate 658 and bonding layer). (Note that 660) is omitted). 1B is vertically aligned with the semiconductor structure 100 of FIG. 1A. The vertical dashed line in FIG. 1B is aligned with the interface between the various layers of the semiconductor structure 100 of FIG. 1A. The vertical axis in FIG. 1B is energy, and the high energy level is positioned vertically above the low energy level. It should be noted that FIG. 1B shows a non-limiting example of the conduction band energy level for the exemplary semiconductor structure 100. As a result, the relative horizontal conduction band energy level can change at a relative position as a function of the composition and doping of at least the individual semiconductor layers, and the composition range of the various semiconductor layers is in the range as described above. Thus, FIG. 1B can be used to see the relative difference in energy levels of the conduction band 128 in various layers of the semiconductor structure 100. 1B, the energy level of the conduction band 128 in the well layer 114 may be lower than the energy level of the conduction band 128 in the other layer of the semiconductor structure 100.

As is known in the art, for group III nitride layers, such as InGaN, the energy level of the conduction band 128 is a function of a number of variables, including but not limited to indium content and dopant levels. The well layer 114 and the barrier layer 116 can be formed to have a composition, otherwise the energy level of the conduction band 128 in the well layer 114 is the energy level of the conduction band 128 in the barrier layer 116. It is configured to be lower. As a result, charge carriers (eg, electrons) can accumulate in the well layer 114 during operation of the light emitting device fabricated from the semiconductor structure 100, and the barrier layer 116 charges across the active region 106. It may function to prevent movement of the carrier (eg, electron). Thus, in some embodiments, the indium content in each well layer 114 may be higher than the indium content in each barrier layer 116. For example, the difference between the indium content in each well layer 114 and the indium content in each barrier layer 116 may be greater than about 0.05 (i.e., w-b ≥ 0.05), or some implementations In an example, it may be greater than about 0.20 (ie, w-b ≥ 0.20). In some embodiments, the dopant concentration in the barrier layer 116 may be different from the dopant concentration in the well layer 114. High doping concentrations can cause defects in the crystal structure of InGaN, and such defects can cause non-radiative combinations of electron-hole pairs. In some embodiments, the dopant concentration in well layer 114 is the non-radiative combination of electron-hole pairs in well layer 114 to the ratio of the non-radiative combination of electron-hole pairs in barrier layer 116. In order to reduce the ratio of, it may be lower than the dopant concentration in the barrier layer 116. In other embodiments, the dopant concentration in the barrier layer 116 may be higher than the dopant concentration in the well layer 114.

As shown in FIG. 1B, the energy barrier provided by the electron blocking layer 108 includes the electron blocking layer 108 and the cap layer 120 (or the electron blocking layer on the side closest to the active region 106) 108) may be due to the difference in the energy level of the conduction band 128 in another layer). The height of the energy barrier can be changed by changing the composition of the electron blocking layer 108. For example, as shown in FIG. 1B, the conduction energy level 130 (if no dopant is present) (indicated by the solid line) may indicate the conduction band energy level for an electron blocking layer consisting at least substantially of GaN. . The conduction band energy level in the electron blocking layer is at least substantially relative to the GaN electron blocking layer as shown by the conduction band energy level 132 (indicated by the broken line) by forming an electron blocking layer composed of In _e Ga _{1 - e} N. Can be reduced, where e is 0.01≦e≦0.02. In another embodiment, the conduction band energy level is at least substantially the Al _e Ga _{1 -} by forming the electron blocking layer composed of the _e N (indicated by a broken line) the conduction band energy level 134, a GaN electron blocking, as shown by the Can be increased for a layer, where e is 0.01 ≤ e ≤ 0.20. Therefore, the energy level of the conduction band in the electron blocking layer can be altered to provide the desired conduction band off-set between the electron blocking layer 108 and the other group III nitride layer of the semiconductor structure 100. have.

In an embodiment of a semiconductor structure 100 in which the electron blocking layer 108 has a superlattice structure comprising alternating layers of various materials, the conduction band energy level is the same as the period shown in inset 136 of FIG. 1B. It can be increased and decreased in a periodic like manner. For example, an electron blocking layer 108 is GaN (138) and Al _e Ga _{1 -} may have a superlattice structure comprising alternating layers of _e N (140), the time, e is 0.01≤e≤0.20 , Or alternatively, the superlattice structure may include alternating layers of GaN and In _e Ga _{1 - e} N, where e is 0.01≤e≤0.02. The magnitude of the conduction band energy off-set between alternating layers of various materials can be selected by the difference in composition between the GaN layer and the Al _e Ga _{1 - e} N or In _e Ga _{1 - e} N layer.

The semiconductor structure of the present disclosure may further include an electron stopping layer disposed between the active region of the semiconductor structure and the In _n Ga _1-n N base layer of the semiconductor structure. Such an electron stop layer can function to further confine electrons in the active region at the band edge of the conduction band, and prevent overflow of carriers from the active region, thereby improving carrier uniformity in the active region It may include a relatively high n-doped group III nitride material compared to the band edge of the conduction band in the In _n Ga _{1 - n} N base layer and/or In _sp Ga _{1 - spN} base layer, providing (uniformity).

As a non-limiting example, FIGS. 2A and 2B show an embodiment of a semiconductor structure 200 including such an electron stop layer 202. The semiconductor structure 200 is similar to the semiconductor structure 100 and the active region 106 comprising one or more InGaN well layers 114 and one or more InGaN barrier layers 116 as described above with respect to the semiconductor structure 100 ). The semiconductor structure 200 also includes a base layer 102, a spacer layer 118, a cap layer 120, an electron blocking layer 108, a p-type bulk layer (as described above in connection with the semiconductor structure 100) 110) and p-type contact layer 104. E-stop layer 202 of the semiconductor structure 200 is In Ga _{n 1 - n} N are disposed between the base layer 112 and spacer layer 118.

The electron stop layer 202 includes group III nitride. As a non-limiting example, the electron stop layer 202 may include AlGaN doped with n-type. For example, in some embodiments, the electron stop layer 202 (if no dopant is present) may be composed of at least substantially Al _st Ga _1-st N, where 0.01≦ _st ≦0.20. In another embodiment, the electron stop layer 202 is a superlattice comprising alternating layers of layers of Al _st Ga _{1 -st} N 206 and GaN 208 as shown in inset 204. It may have a structure, where 0.01≤st≤0.20. The semiconductor structure 200 may include any number of alternating layers of layers of Al _st Ga _{1 -st} N 206 and GaN 208 (eg, from about one (1) to about twenty (20)). have. The layers 206 and 208 in such a superlattice structure may have an average layer thickness of about 1 nanometer (1 nm) to about 100 nanometers (100 nm).

The electron stop layer 202 may be doped n-type by one or more dopants selected from the group consisting of silicon and germanium. The concentration of one or more dopants in the electron stop layer 202 can range from about 0.1e ¹⁸ cm ^-3 to 20e ¹⁸ cm ^-3 . In some embodiments, the electron stop layer 202 may have an average layer thickness T _st ranging from about 1 nanometer (1 nm) to about 50 nanometers (50 nm).

2B is a simplified conduction band diagram and shows the relative energy levels of the conduction band 228 for various materials of the semiconductor structure 200. As shown in FIG. 2B, in the embodiment of the semiconductor structure 200 of FIG. 2A, the energy level of the conduction band 228 in at least a portion of the electron stop layer 202 of the semiconductor structure 200 (FIG. 2B) is In _n Ga _{1 - n} N is relatively higher than the energy level of the conduction band 228 in a base layer layer energy level and / or the spacer of the conduction band 200 in the 112 (118). The electron stop layer 202 includes alternating layers of layers of Al _st Ga _{1 -st} N 206 and GaN 208, shown in inset 210 in FIG. 2B, where 0.01≤st≤0.20. In an embodiment that includes a superlattice structure as shown, the energy level of the conduction band may change periodically.

In a further embodiment, the semiconductor structure of the present disclosure, the active region and the In _n Ga ₁ is employed to facilitate manufacture of the semiconductor structure may _comprise at least one material layer between the _n N base layer. For example, in some embodiments, the semiconductor structure of the present disclosure, and its structure one or more light emitting devices produced from the same active region and the In _n Ga _{1 -} at least one strain relief disposed between the _n N base layer layer (strain relief layer), wherein the strain relief layer accommodates the deformation of the crystal lattice of the crystal structure of several layers of the semiconductor structure between the In _n Ga _{1 - n} N base layer and the p-type contact layer. Can be made and constructed, and the layers can be epitaxially grown in a layer-by-layer process.

As a non-limiting example, FIGS. 3A and 3B show an embodiment of a semiconductor structure 300 including such a strain relief layer 302. The semiconductor structure 300 is similar to the semiconductor structure 100 and includes an active region comprising one or more InGaN well layers 114 and one or more InGaN barrier layers 116, as described above with respect to the semiconductor structure 100 ( 106). The semiconductor structure 300 also includes a base layer 102, a spacer layer 118, a cap layer 120, an electron blocking layer 108, a p-type bulk layer (as previously described with respect to the semiconductor structure 100) 110) and p-type contact layer 104. Strain reducing layer 302 of the semiconductor structure 300 is In Ga _{n 1 - n} N are disposed between the base layer 112 and the spacer layer 118. In the embodiment of Figures 3a and 3b, the strain relief layer 302 In _n Ga _{1 -} is disposed directly between the _n N base layer 112 and the In _{sp sp} Ga1- N spacer layer 118.

The strain relief layer 302 can include a group III nitride. As a non-limiting example, the strain relief layer 302 includes alternating layers of layers of In _sra Ga _{1 - sra} N 306, and In _srb Ga _{1 - srb} N 308, where 0.01≦sra ≤0.10, 0.01≤srb≤0.10, as shown in the inset 304 may have a superlattice structure. Also, sra may be larger than srb. Semiconductor structure 300 can be any number of alternating layers of In _sra Ga _{1 - sra} N layer 306 and In _srb Ga _{1 - srb} N 308 (eg, from about one (1) to about twenty (20)) ). The layers 306 and 308 in such a superlattice structure may have an average layer thickness of about 1 nanometer (1 nm) to about 20 nanometers (20 nm).

The strain relief layer 302 may be doped n-type with one or more dopants selected from the group consisting of silicon and germanium. The concentration of one or more dopants in the strain relief layer 302 can range from about 0.1e ¹⁸ cm ^-3 to 20e ¹⁸ cm ^-3 . In some embodiments, the strain relief layer 302 can have an average layer thickness ranging from about 1 nanometer (1 nm) to about 50 nanometers (50 nm).

3B is a simplified conduction band diagram and shows the relative energy levels of the conduction band 328 for various materials in the semiconductor structure 300. As shown in FIG. 3B, in the embodiment of the semiconductor structure 300 of FIG. 3A, the energy level of the conduction band 328 in at least a portion of the strain relief layer 302 (FIG. 3A) of the semiconductor structure 300 is: The energy level of the conduction band 328 in the InGaN base layer 112 and/or the energy level of the conduction band 328 in the spacer layer 118 may be relatively lower. In another embodiment, the energy level of the conduction band 328 in at least a portion of the strain relief layer 302 (FIG. 3A) of the semiconductor structure 300 is the energy level of the conduction band 328 in the InGaN base layer 112 and /Or the energy level of the conduction band 328 in the spacer layer 118 may be relatively higher. As shown in inset 310 of FIG. 3B, the strain relief layer comprises a superlattice structure comprising alternating layers In _sra Ga _{1 - sra} N layer 306 and In _srb Ga _{1 - srb} N 308. In an embodiment, the conduction band energy level may vary periodically.

4A and 4B show another embodiment of the semiconductor structure 400 of the present disclosure. The semiconductor structure 400 is similar to the semiconductor structure 100 and includes an active region comprising one or more InGaN well layers 114 and one or more InGaN barrier layers 116 as described above with respect to the semiconductor structure 100 ( 406). The semiconductor structure 400 also includes a base layer 102, a spacer layer 118, a cap layer 120, an electron blocking layer 108, a p-type bulk layer (as previously described in connection with the semiconductor structure 100) 110) and p-type contact layer 104. The active region 406 of the semiconductor structure 400 further includes an additional GaN barrier layer 402. Each of the additional GaN barrier layers 402 can be disposed between the InGaN well layer 114 and the InGaN barrier layer 116. The additional GaN barrier layer 402 may also function to confine electrons in the well layer 114, where the electrons may tend to recombine more with the hole and result in an increased probability of radiation emission. .

In some embodiments, each GaN barrier layer 402 may be doped n-type with one or more dopants selected from the group consisting of silicon and germanium. For example, the concentration of one or more dopants in the GaN barrier layer 402 can range from about 1.0e ¹⁷ cm ^-3 to 50e ¹⁷ cm ^-3 . In some embodiments, each GaN barrier layer 402 can have an average layer thickness T _b2 ranging from about 0.5 nanometers (0.5 nm) to about 20 nanometers (20 nm).

4B is a simplified conduction band diagram and shows the relative energy levels of the conduction band 428 for various materials in the semiconductor structure 400. 4B, in the embodiment of the semiconductor structure 400 of FIG. 4A, the energy level of the conduction band 428 in the GaN barrier layer 402 (FIG. 4A) is the conduction band 428 in the InGaN barrier layer 116. ) And may be relatively higher than the energy level of the conduction band 428 in the InGaN well layer 114.

5A and 5B show another embodiment of the present disclosure that includes a semiconductor structure 500. In this embodiment, the method disclosed in U.S. Patent Application No. 13/362,866, filed January 31, 2012 under the name Arena, can be used to form active region 506. The semiconductor structure 500 is similar to the semiconductor structure 100 and includes an active region 506 comprising one or more InGaN well layers 514 and one or more InGaN barrier layers 516 as described above with respect to the semiconductor structure 100. ). The semiconductor structure 500 also includes a base layer, a spacer layer, a cap layer, an electron blocking layer, a p-type bulk layer 100 and a p-type contact layer as described above in connection with the semiconductor structure 100. For clarity, surrounds the active region 506 is only the layer is shown, these layers are optional spacer layer 118 and cap layer 120 and the In _n Ga _{1 - n} N base layer 112 and an electron blocking layer ( 108). If the selected layer is omitted from the semiconductor structure 500, active region 506 is _n In Ga _{1 -} it can be directly disposed between the _n N base layer 112 and electron blocking layer 108.

The active region 506 of the semiconductor structure 500 is similar to the active region 100 of the semiconductor structure, but further includes two or more InGaN barrier layers, wherein the band-gap energy between subsequent barrier layers is shown in FIGS. 5A and 5A. As seen in 5b, it increases stepwise from right to left, ie from the cap layer 120 to the spacer layer 118. Such a configuration of the active region 506 in the semiconductor structure 500 can prevent the overflow of carriers out of the active region 506 to help confine the charge carriers in the active region 500, thereby doing so The efficiency of the light emitting device manufactured from 500 is increased.

Barrier region (516 _AC) is each band may have a selected material composition and structural configuration to provide a respective barrier region (516 _AC) having the gap energy (550 _AC), this time, the band-gap energy of the semiconductor It is given by the energy difference between valence band energy 552 and conduction band energy 528 of each semiconductor material including structure 500. In be smaller than the gap energy (550 _B) and the second barrier regions (516 _B)-gap energy (550 _A) of the second barrier regions (516 _B) band at - the first barrier region (516 _A) bands at The band-gap energy 550 _B of may be smaller than the band-gap energy 550 _C in the third barrier region 516 _C , as shown in the energy band diagram of FIG. 5B. In addition, each of the band-gap energies of the quantum well region 552 _AC may be substantially the same, and may be less than each of the band-gap energies 516 _AC of the barrier region 550 _AC .

In this configuration, the hole energy barrier 554 _A between the first quantum well 514 _A and the second quantum well 514 _B is a hole between the second quantum well 516 _B and the third quantum well 516 _C. May be smaller than the energy barrier 554 _B. In other words, the hole energy barrier 554 _AC across the barrier region 516 _AC may increase stepwise across the active region 506 from the cap layer 120 in the direction of the spacer layer 118. The electron hole energy barrier 554 _AC is the difference in energy of the valence band 552 across the interface between the quantum well region 514 _AC and the adjacent barrier region 516 _AC . As a result of increasing the electron hole energy barrier 554 _AC across the barrier region 516 _AC moving from the cap layer 120 toward the spacer layer 108, an increase in uniformity of holes within the active region 506 Can be achieved, thereby improving efficiency during the operation of manufacturing a light emitting device from semiconductor structure 500.

As previously mentioned, barrier region 516 _AC can have a material composition and structural configuration selected to provide their respective, respective band-gap energy 550 _AC to barrier region 516 _AC . _. By way of example and not limitation, each barrier region 516 _AC may include a tertiary III-nitride material, such as In _b3 Ga _{1 - b3} N, where b3 is at least about 0.01. Reducing the indium content in In _b3 Ga _{1 - b3} N of the barrier region 516 _AC (ie, reducing the value of b3) can increase the band-gap energy of the barrier region 516 _AC . Accordingly, the second barrier region 516 _B may have a low indium content in the first barrier region 516 _A , and the third barrier region 516 _C may have a low indium content relative to the second barrier region 516 _B. Can have In addition, barrier region 516 _AC and well region 514 _AC can be doped and have an average layer thickness as described above for semiconductor structure 100.

As previously mentioned, according to embodiments of the present disclosure, active region 106 (FIG. 1A) may include at least one InGaN well layer and at least one InGaN barrier layer, and in some embodiments , At least substantially InGaN (eg, may consist essentially of InGaN if no dopant is present). A number of already known light emitting device structures including an InGaN well layer include a GaN (at least substantially indium free) barrier layer. The difference in the energy level of the conduction band between the InGaN well layer and the GaN barrier layer is relatively high, and according to the idea in this technology, it is possible to provide improved confinement of charge carriers in the well layer and improve the efficiency of the LED structure. However, prior art structures and methods can result in reduced device efficiency due to carrier overflow and piezoelectric polarization.

In the theory of carrier overflow, one or more layers of quantum wells can be similar to a water bucket, and this ability to capture and maintain the injected carriers weakens the high injection of carriers. When the injected carrier is not captured or maintained, it overflows and wastes the active area, contributing to poor device efficiency. In prior art structures comprising an InGaN quantum well and GaN barrier layer, the band off-set, i.e., the difference in conduction band energy level between the quantum well and the barrier, is substantially composed of InGaN, as described in the Examples herein. It is considerably greater than the band off-set for the active region. The reduction in band off-set in the structures described herein allows the injected carriers to be distributed more efficiently across the quantum well regions of the active region, increasing the efficiency of light emitting devices made from the semiconductor structures described herein.

Moreover, due to the lattice mismatch between the InGaN well layer and the GaN barrier layer, relatively strong piezoelectric polarization occurs within the active region of this light emitting device structure. Piezoelectric polarization can reduce the overlap between the wave function for electrons and the wave function for holes within the active region of the light emitting device structure. For example, JH Son and JL Lee's " Numerical Analysis of Efficiency Droop Induced by Piezoelectric Polarization in InGaN / GaN Lighth - Emitting Diodes , Appl. Phys. Lett. 97, 032109 (2010), piezoelectric polarization can cause what is called "efficiency droop" in such light emitting device structures (eg, LEDs). It is the decrease (decrease) in the graph of the internal quantum efficiency (IQE) of the LED structure having.

Embodiments of the light emitting structures of the present disclosure, such as LED structures, alleviate or overcome the problems of known LED structures having GaN barrier layers and InGaN well layers associated with lattice mismatch, ie carrier overflow, piezoelectric polarization, and efficiency degradation can do. An LED structure fabricated from an embodiment of the LED of the present disclosure, such as the semiconductor structures 100 of FIGS. 1A and 1B, can be constructed, its energy band structure is designed, and as a result, the active region 106 is reduced It shows the piezoelectric polarization effect, and an increased superposition of the wave function of the electron and the wave function of the hole. As a result, light emitting devices, such as LEDs, may exhibit improved uniformity of charge carriers across the active region 106 and reduced efficiency degradation with increasing current density.

These advantages that can be obtained through embodiments of the present disclosure are further discussed below with reference to FIGS. 10A and 10B, 11A-11E, 12A and 12B, and 13A-13E. 10A and 10B show an embodiment of an LED 556 similar to a known LED. LED 556 includes an active region 558 that includes five (5) InGaN well layers 562 with a GaN barrier layer 564 disposed between InGaN well layers 562. The LED 556 also includes a base layer 560, a first spacer layer 566, a second spacer layer 568, an electron blocking layer 570, and an electrode layer 572. In the LED (556), InGaN well layer 562, respectively, and those of a layer of In _{0 .18} Ga _{0 .82} N has an average thickness of about 2.5 nanometer (2.5 nm). The barrier layer 564 includes a layer of GaN that can have an average layer thickness of about 10 nanometers (10 nm). The base layer 560 includes a layer of doped GaN having an average layer thickness of about 325 nanometers (325 nm), which is n-type doped with silicon at a concentration of about 5e ¹⁸ cm ^-3 . The first spacer layer 566 may include undoped GaN having an average layer thickness of about 25 nanometers (25 nm). The second spacer layer 568 may also include undoped GaN having an average layer thickness of about 25 nanometers (25 nm). The electron blocking layer 570 may include p-doped AlGaN. The electrode layer 572 can include a layer of doped GaN, which is an average layer of about 125 nanometers (125 nm) doped p-type by magnesium at a concentration of about 5e ¹⁷ cm ^-3 . It can have a thickness. 10B is a simplified conduction band diagram similar to that of FIG. 1B and shows the relative difference in energy level (in the energy band diagram) of the conduction band 574 for various materials in the various layers of the LED 556 of FIG. 10A. The vertical dashed line in FIG. 10B is aligned with the interface between the various layers in LED 556 of FIG. 10A.

As is known in the art, for example, the SL khuang and CS Chang's “ k·p Method for Strained Wurtzite Semiconductors , Phys. Rev. B 54, 2491 (1996)" can be used to characterize the structure of valence bands for group-III nitride materials such as GaN and InGaN. The splitting of The heavy, light, and split-off branch of the valence band at the center of the Brillouin zone can be assumed to be independent of the built-in electric field. , Valence subbands can be obtained from the solution of the coupled Poisson and transport equations The wave functions of electrons and holes are respectively:

, 및

, And

및

는 브릴루엥 영역(Brilluene zone)의 중심에 대응하는 전자 및 정공의 블로호 진폭(Bloch amplitudes)이고,

및

는 평면 내 유사-모멘트 벡터(quasi-moment vectors)이고,

및

는 덮개 함수(envelope functions)이고, 아래 첨자 "s"는 중(hh), 경(lh), 또는 분할(so) 정공일 수 있다. 전자 및 정공 덮개 함수에 대한 일차 슈뢰딩거 방정식은 각각:It can be assumed to be a form, at this time,

And

Is the blown amplitudes of electrons and holes corresponding to the center of the Brilluene zone,

And

Is in-plane quasi-moment vectors,

And

Is an envelope function, and the subscript "s" can be a medium (hh), light (lh), or split (so) hole. The linear Schrodinger equation for the electron and hole cover functions is:

, 및

, And

이고,

ego,

및

는 양자 우물에서 전자 및 정공에 대한 유효 퍼텐셜이고,

및

는 전자 및 정공 에너지 준위이고,

및

은 에피택셜 성장 방향에서의 전자 및 정공 유효 질량이다. 대응하는 경계 조건으로 상기 슈뢰딩거 방정식을 풀음으로써, 전자 및 정공 파동 함수 간의 중첩 적분은:At this time,

And

Is the effective potential for electrons and holes in quantum wells,

And

Is the electron and hole energy level,

And

Is the electron and hole effective mass in the epitaxial growth direction. By solving the Schrödinger equation with the corresponding boundary conditions, the overlapping integration between the electron and hole wave functions is:

Is obtained from

SL Chuang's " Physics of Phonic Devices , 2 ^nd Ed. (Wiley, New Jersey, 2009)", the ratio of radiation recombination of electrons and holes is:

It can be given by, where B is the radiation recombination coefficient, n is the electron concentration, p is the hole concentration, F _n - F _p is the quasi-Fermi level separation. Electron and hole concentrations and pseudo-Fermi level separation vary with position across the active area of the LED. The maximum emission recombination rate can be identified in any quantum well and can be considered as the peak emission recombination rate for each of its quantum wells.

FIG. 11A is a function of the position (in nanometers) across the LED 556 starting at the surface of the base layer 560 opposite the active area 558, with a zero applied current across the LED 556. , Is a graph showing the calculated energy of the band edges of the conduction band 574 and valence band 576 for the LED 550 of FIGS. 10A and 10B. 11B is similar to FIG. 11A but with conduction band 574 and home appliance for LED 556 of FIGS. 10A and 10B at a current density applied across LED 556 of 1205 amperes/square centimeter (125 A/cm ² ). It is a graph showing the calculated energy of the band edge of the magnetic band 576. 11C is calculated as a function of wavelength for each of the five quantum well layers 562 of the LED 556 with the applied current density across the LED 550 of 125 amperes/square centimeter (125 A/cm ² ). It is a graph showing the intensity. QW1 is the leftmost quantum well layer 562, and QW5 is the rightmost quantum well layer 562 from the perspective views of FIGS. 10A and 10B. 11D shows the calculated injection efficiency of LED 556 as a function of applied current density. 11D, the LED 550 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm ² . 11E shows the calculated internal quantum efficiency (IQE) of the LED 556 as a function of the applied current density. 11E, the LED 556 can exhibit an internal quantum efficiency of about 45.2% at an applied current density of 125 A/cm ² . 11E, the internal quantum efficiency of the LED 556 drops from greater than 50% at an applied current density of about 20 A/cm ² to less than 40% at an applied current density of 250 A/cm ² . Can be. As discussed earlier, this drop in IQE is called the technique as a drop in efficiency.

Table 1 below shows the calculated wave function overlap and peak emission recombination rate for each of the five quantum well layers 562 in the LED 550 of FIGS. 10A and 10B.

QW1 QW2 QW3 QW4 QW5 Wave function overlap 0.328 0.326 0.325 0.341 0.362 Peak radiation recombination rate 6.5e ²⁶ 3.3e ²⁶ 3.3e ²⁶ 6.8e ²⁶ 2.4e ²⁷

As can be seen from Figure 11c and Table 1 above, the radiation recombination is the last well layer 562 (p-doped side, or closest to the anode), which is the quantum well number 5 (ie QW5) in the LED 556. Comes mainly from In addition, as shown in FIG. 11E, the LED 556 may occur at least partially due to piezoelectric polarization caused by the use of the InGaN well layer 562 and GaN barrier layer 564 as previously discussed herein. It shows a decrease in efficiency.

Embodiments of the LEDs of the present disclosure comprising at least one InGaN well layer and at least one InGaN barrier layer, such as an active region comprising the active region 106 of the LED 100, are used in radiation recombination occurring in the well layer. It may exhibit improved uniformity and reduced efficiency degradation. A comparison of the LED 550 and an embodiment of the LED of the present disclosure is provided below with reference to FIGS. 12A and 12B, and 13A-13E.

12A and 12B show another example of an embodiment of the LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five (5) InGaN well layers 114 and an InGaN barrier layer 116 is disposed between the InGaN well layers 114. InGaN well layer 114 and InGaN barrier layer 116 may be as previously described with respect to semiconductor structure 100 with reference to FIGS. 1A and 1B. The LED 600 also includes a base layer 112, a first spacer layer 118, a cap layer 120, and an InG electrode layer 104. In the LED (600), InGaN well layer 114 comprises a layer of In _{0 .18} Ga _{0 .82} N, each of which layer has an average thickness of about 2.5 nanometer (2.5 nm). Barrier layer 116 each may have an average thickness of about 10 nanometers (10 nm) and a layer of In _{0 .08} Ga _{0 .92} N. Base layer 112 is doped with n- type by silicon at a concentration of about 5e ¹⁸ cm ^-3, from about 300 nanometers (300 nm) having an average thickness of In _{0 .05} Ga _{0 .95} doped N of It includes a layer of. The first spacer layer 118 can comprise a non-In _{0 .08} Ga _{0 .92} N-doped layer having an average thickness of about 25 nanometers (25 nm). Cap layer 120 may also comprise from about 25 nanometers with an average layer thickness of _{0 .08} In non-doped Ga _{0 .92} N of (25 nm). The electrode layer 104 is doped In _{0 .05} Ga ₀ , which can have an average layer thickness of about 150 nanometers (150 nm) doped p-type with magnesium at a concentration of about 5e ¹⁷ cm ^-3 _{. 95} N layers. 12B is a simplified conduction band diagram showing the relative difference in energy level (in the energy band diagram) of the conduction band 602 for various materials in the various layers of the LED 600 of FIG. 12A.

13A is a function of the position (in nanometers) across the LED 600 starting at the surface of the base layer 112 opposite the active region 106, with the applied current of zero across the LED 600 Together, it is a graph showing the calculated energy of the band edges of the conduction band 602 and valence band 604 for the LED 600 of FIGS. 12A and 12B. 13B is similar to that of FIG. 13A, but conduction band 602 for LED 600 of FIGS. 12A and 12B at an applied current density across LED 600 of 125 amperes/square centimeter (125 A/cm ² ). And a graph showing the calculated energy of the band edge of the valence band 604. 13C is calculated as a function of wavelength for each of the five quantum well layers 108 of the LED 600 with applied current density across the LED 600 of 125 amperes/square centimeter (125 A/cm ² ). It is a graph showing the intensity. QW1 is the leftmost quantum well layer 108, and QW5 is the rightmost quantum well layer 108 from the perspective views of FIGS. 12A and 12B. 13D shows the calculated injection efficiency of LED 600 as a function of applied current density. As shown in FIG. 13D, the LED 600 can exhibit an injection efficiency of about 87.8% at an applied current density of 125 A/cm ² , and a current density of about 250 A/cm ² from about 20 A/cm ² A carrier injection efficiency of at least about 80% over the range can be achieved. 13E shows the calculated internal quantum efficiency (IQE) of the LED 600 as a function of the applied current density. 13E, the LED 600 may exhibit an internal quantum efficiency of about 58.6% at an applied current density of 125 A/cm ² . 13E, the internal quantum efficiency of the LED 600 can be maintained between about 55% and about 60% at an applied current density ranging from about 20 A/cm ² to 250 A/cm ² . Thus, the LED 600 exhibits a very low efficiency drop and a significantly lower efficiency drop than the efficiency drop indicated by the LED 500 (the LED 500 is not consistent with embodiments of the present disclosure).

Table 2 below shows the calculated wave function overlap and peak emission recombination rate for each of the five quantum well layers 108 in the LED 600 of FIGS. 12A and 12B.

QW1 QW2 QW3 QW4 QW5 Wave function overlap 0.478 0.493 0.494 0.494 0.471 Peak radiation recombination rate 7.8e ²⁶ 7.7e ²⁶ 7.9e ²⁶ 8.1e ²⁶ 8.3e ²⁶

13C and Table 2 above, radiation recombination is more uniform across the well layer 108 in the LED 600 compared to the well layer 508 in the LED 500.

The LEDs 550 of FIGS. 10A and 10B and the LEDs 600 of FIGS. 12A and 12B are modeled using SiLENSe software commercially available from STR Group, Inc. SiLENSe software was also used to generate the graphs of FIGS. 11A-11E and 13A-13E, and to obtain the data shown in Tables 1 and 2.

According to some embodiments of the present disclosure, the LED is at least about 45% over a range of current densities from about 20 A/cm ² to about 250 A/cm ² , or even from about 20 A/cm ² to about 250 A/ an internal quantum efficiency of at least about 55% over a range of current densities of cm ² . Further, the LED may exhibit at least substantially constant carrier injection efficiency over a range of current densities from about 20 A/cm ² to about 250 A/cm ² . In some embodiments, LEDs of the present disclosure can exhibit a carrier injection efficiency of at least about 80% over a range of current densities from about 20 A/cm ² to about 250 A/cm ² .

Non-limiting examples of a semiconductor structure and a light emitting device of an embodiment of the present disclosure that can be used to manufacture an LED, for example, are briefly described below with reference to FIGS. 6C to 6D and light emission produced by such a method Examples of devices are described with reference to FIGS. 7 and 8.

Referring to FIG. 6C, growth template 113 (prepared as previously described above) can be placed in a deposition chamber, group III, commonly referred to as growth stack 682 (see FIG. 6D). The layer comprising nitride material may be grown epitaxially, sequentially, on one or more seed layers 656 of the growth template 113. It should be noted that although the seed layer is shown as an island of one or more Group III nitride materials, in some embodiments, the seed layer can include a continuous film over the support substrate 658.

6D shows a semiconductor structure 680 that includes a growth template 113 that includes two seed layers 656, each of which is deposited on top of several of the semiconductor structures 100 of FIGS. 1A and 1B deposited thereon. Have a layer In particular, the In _n Ga _{1 - n} N base layer 112 of the semiconductor structure 100 is sequentially epitaxially deposited on the growth template 112, an InGaN spacer layer 118, an InGaN well layer 114, and InGaN. On each of the seed layer structures 656, along with the barrier layer 116, InGaN cap layer 120, electron blocking layer 108, p-type bulk layer 110 and p-type contact layer 104. Direct epitaxial deposition.

For example, a semiconductor structure comprising a growth stack 682 using a metal organic chemical vapor deposition (MOCVD) process and a system in a single deposition chamber, that is, without the need for an unloading or unloading growth stack during the deposition process. Several layers of 680 can be deposited. The pressure in the deposition chamber can be reduced between about 50 mTorr and about 500 mTorr. The pressure in the reaction chamber during the deposition process can be increased and/or decreased during deposition of the growth stack 682, so that it can be tailored for the particular layer being deposited. As a non-limiting example, In _n Ga _{1 - n} N base layer 112, spacer layer 118, one or more wells 114/barrier layer 116, cap layer 120 and electron barrier layer 108 The pressure of the reaction chamber during deposition of may be in a range between about 50 mTorr and about 500 mTorr, and in some embodiments may be equal to about 440 mTorr. The pressure in the reaction chamber for the deposition of the p-type bulk layer 110 and the p-type contact layer 104 may range between about 50 mTorr and about 250 mTorr, and in some embodiments, about 100 mTorr and It can be the same.

The growth template 113 can be heated to a temperature between about 600°C and about 1,000°C in the deposition chamber. Metal organic precursor gases and other precursor gases (and, optionally, carrier and/or purge gases) then flow through the deposition chamber and over one or more seed layers 656 of the growth template 113. I can do it. The metal-organic precursor gas can be subjected to reactive decomposition, or both reaction and decomposition, in a manner that results in epitaxial deposition of a group II nitride layer, such as an InGaN layer, over the growth template 113.

As a non-limiting example, trimethylindium (TMI) can be used as a metal organic precursor for indium of InGaN, triethylgallium (TMG) can be used as a metal organic precursor for gallium of InGaN, and tri Ethyl aluminum (triethylaluminum, TMA) can be used as a metal organic precursor for AlGaN, and ammonia can be used as a precursor for nitrogen in the group III nitride layer. SiH ₄ can be used as a precursor for the introduction of silicon into InGaN when a group III nitride n-type doping is desired, and Cp2Mg (bis(cyclopentadienl) magnesium) is a group III p-type doping. It can be used as a precursor for introducing magnesium into III nitride. It may be advantageous to match the ratio of the indium precursor (e.g. trimethylindium) to a gallium precursor (e.g. triethylgallium) that will cause indium to be included in InGaN at a concentration near the saturation point for indium in InGaN at deposition temperature . The percentage of indium contained in InGaN can be controlled because InGaN is epitaxially grown by controlling the growth temperature. A relatively high amount of indium can be included at a relatively low temperature, and a relatively low amount of indium can be included at a relatively high temperature. As a non-limiting example, InGaN well layer 108 may be deposited at a temperature ranging from about 600°C to about 950°C.

The deposition temperature of the various layers of the growth stack 100 can be increased and/or decreased during the deposition process and thus tailored for the particular layer to be deposited. As a non-limiting example, In _n Ga _{1 - n} N base layer 112, the deposition temperature during the deposition of the p- type bulk layer 110 and the p- type contact layer 104 is about 600 ° and about 950 ℃ It may be in the range between, and in some embodiments may be equal to about 900 ℃. In _n Ga _{1 - n} N base layer 112, the growth rate of the p- type bulk layer 110 and the p- type contact layer 104 is about 1 nm / min (1 nm / min) and about 30 It may be in the range of nanometers / min (30 nm / min), in some embodiments, in _n Ga _{1 - n n} base layer (112), p- type bulk layer 110 and the p- type contact The growth rate of layer 104 may be equal to about 6 nanometers/minute (6 nm/min).

In further non-limiting exemplary embodiments, the deposition temperature during deposition of the spacer layer 118, one or more well layers 114, one or more barrier layers 116, cap layers 120 and electron blocking layers 108. Can be in a range between about 600° and about 950° C., and in some embodiments, can be about 750° C. The growth rates of the spacer layer 118, one or more well layers 114, one or more barrier layers 116, cap layers 120, and electron blocking layers 108 are about 1 nanometer/minute (1 nm/min) ) And about 30 nanometers/minute (30 nm/min), in some embodiments a spacer layer 118, one or more well layers 114, one or more barrier layers 116, caps The growth rate of layer 120 and electron blocking layer 108 may be equal to about 1 nanometer/minute (1 nm/min).

In embodiments involving the deposition of an InGaN layer, the flow rate ratio of the precursor gas can be selected to provide a high quality InGaN layer. For example, a method for forming an InGaN layer of semiconductor structure 100 provides one or more InGaN layers with low defect density, substantially no stain relaxation, and substantially no surface pits. This may include selecting a gas ratio.

In a non-limiting example, the flow rate ratio (%) of trimethylindium (TMI) to triethylgallium (TMG ) is:

It can be defined as, and such a flow rate ratio can be increased and/or decreased during the deposition process and thus can be tailored for the particular InGaN layer to be deposited. Non-limiting example, In _n Ga _{1 -} flow rate of deposition for the _n N base layer 112 and a p- type bulk layer 110 may be in a range between about 50% and about 95 ℃, some In an embodiment, it may be equal to about 85%. In other embodiments, the flow rate ratio during deposition of the spacer layer 118, the one or more barrier layers 116 and the cap layer 120 may be in a range between about 1% and about 50%, some embodiments It can be equal to about 2%. In yet another embodiment, the flow rate ratio during deposition of the one or more quantum well layers 114 may be in a range between about 1% and about 50%, and in some embodiments may be equal to about 30%.

The growth template 113 can optionally be rotated within the deposition chamber during the deposition process. As a non-limiting example, the growth template 113 may be rotated at a rotational speed between about 50 revolutions per minute (RPM) and about 1500 revolutions per minute (RPM) in the deposition chamber during the deposition process, and in some embodiments It can rotate at a rotational speed equal to about 450 revolutions per minute (RPM). The rotational speed during the deposition process can be increased and/or decreased during deposition, so that it can be tailored for the particular layer to be deposited. Non-limiting examples as the In _n Ga _{1 - n} N base layer 112, spacer layer 118, at least one well layer 114, at least one barrier layer 116, cap layer 120 and the electron barrier layer ( The rotational speed of the growth template during deposition of 108 may be in a range between about 50 revolutions per minute (RPM) and about 1500 revolutions per minute (RPM), and in some embodiments, about 440 revolutions per minute (RPM). It can be rotated at the same rotation speed. The rotation speed of the growth template 113 during deposition of the p-type bulk layer 110 and the p-type contact layer 104 may be in a range between about 50 revolutions per minute (RPM) and about 1500 revolutions per minute (RPM). In some embodiments, it may rotate at a rotational speed such as about 1000 revolutions per minute (RPM).

Deformation energy of one or more InGaN layers comprising a growth stack 682 epitaxially deposited over growth template 113, in an embodiment of the semiconductor structure of the present disclosure including deposition of Group III nitride, and in particular InGaN layer Can affect the efficiency of a light emitting device manufactured with such a semiconductor structure. In some embodiments, the total strain energy generated within the growth stack 682 may be related to the efficiency defined by the internal quantum efficiency (IQE) of the semiconductor structure of the present disclosure.

More specifically, the strain energy stored in the nth layer of InGaN is proportional to the average total thickness ( T _n ) of the nth layer of InGaN and the concentration of indium ( % In _n ) of the nth layer of InGaN. In addition, the total strain energy stored in the plurality of InGaN layers including the growth stack 682 is proportional to the sum of the average total thickness ( T _n ) of each InGaN layer and the concentration of indium ( % In _n ) in each InGaN layer. , The total strain energy in the InGaN layer including the growth stack 702 can be estimated using the following equation:

,

,

At this time, the average total thickness ( T _n ) of the n-th layer is expressed in nanometers (nm), and the concentration of indium ( %In _n ) in the n-th InGaN layer is expressed in atomic percentages. For example, if the nth layer of InGaN has an average overall thickness ( T _n ) of 150 nanometers (150 nm) and an indium concentration ( % In _n ) of 2.0 at%, the strain energy in the nth layer of InGaN is It may be 300 au (300 = 150(2)).

9 shows a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for a semiconductor structure of the present disclosure. The IQE of the semiconductor structure of the present disclosure can be reduced to the value of the total strain energy referred to as “critical strain energy” of the semiconductor structure, as indicated by line 902 of graph 900. The IQE of the semiconductor structure below the critical strain energy (as indicated by line 904) may be substantially greater than the IQE of the semiconductor structure above the critical strain energy (as indicated by line 906), eg, graph 900 Denotes IQE values (represented by rectangular marks) for several semiconductor structures of the present disclosure. In some embodiments, the IQE below the critical strain energy may be about 500% greater than the IQE above the critical strain energy. In other embodiments, the IQE below the critical strain energy may be about 250% greater than the IQE above the critical strain energy. In another embodiment, the IQE below the critical strain energy may be about 100% greater than the IQE above the critical strain energy.

For the semiconductor structure of the present disclosure, the critical strain energy 902 defined by the sum of the product of the indium content (%) of each layer and the thickness (nm) of each layer is about 1800 or less. , About 2800 or less, or even about 4500 or less.

In the present disclosure, a plurality of group III nitride layer including a growing stack (682) of Figure 6d is a growing stack 682 is grown the template 113 of the In _s Ga _{1 -} a _s N seed layer 656 It can be deposited in a manner that is substantially completely deformed to match the crystal lattice. In such an embodiment in which the growth stack 682 is substantially completely deformed, ie, grown substantially without strain relief, the growth stack inherits the lattice parameters of the In _s Ga _{1 - s} N seed layer. In certain embodiments of the present disclosure, the In _s Ga _{1 - s} N seed layer may exhibit a growth plane lattice parameter greater than 3.2 Angstroms, and the growth stack may exhibit a growth plane lattice parameter greater than 3.2 Angstroms. Therefore, in a non-limiting example, the semiconductor structures 100, 200, 300, 400, 500 may be formed in a manner composed of fully deformed materials, and may have such growth plane lattice parameters.

In another embodiment, a plurality of Group III nitride layers comprising the growth stack 682 of FIG. 6D can be deposited in such a way that the growth stack 682 is partially relaxed, ie, of the growth stack 682. The lattice parameter is different from the lower In _s Ga _{1 - s} N seed layer. In this embodiment, the percentage strain relief ( R ) is.

It can be defined as, where a is the average growth plane lattice parameter for the growth stack 682, a _s is the average growth plane lattice parameter of the In _s Ga _{1 - s} N seed, and a _l is the growth stack. The equilibrium (or natural) mean growth plane lattice parameter for. For example, in some embodiments growth stack 682 may exhibit a percentage strain relief ( R ) less than about 0.5%, and in further embodiments growth stack 682 may exhibit a percentage strain relief less than about 10%. ( R ), and in another embodiment, the growth stack 682 may exhibit a percentage strain relief ( R ) less than about 50%.

After epitaxial deposition of several layers of a semiconductor structure comprising a group III nitride material, further processing can be applied to complete the fabrication of the semiconductor structure with a light emitting device, such as an LED. For example, electrode contacts are known in the art and can be formed on a layer of group III nitride material using the process briefly described below with reference to FIGS. 7 and 8.

An example of a light emitting device 700, such as an LED, made from semiconductor structure 100, is shown in FIG. 7. Although the following description describes an embodiment for manufacturing a light emitting device from the semiconductor structure 100, it should be noted that such a manufacturing process can also be applied to the semiconductor structures 200, 300, 400, 500.

More specifically, a portion of the semiconductor structure 100 can be removed, thereby exposing a portion of the In _n G _{1 -n} aN base layer 112. Removal of the selected portion of the semiconductor structure 100 can be realized by applying a photosensitive chemical to the exposed surface of the p-contact layer 100 of the semiconductor structure 100 (not shown). Upon exposure of the electromagnetic radiation through the patterned transparent plate and subsequent development, the photosensitive layer allows the "mask layer to allow selective removal of the group III nitride layer over the In _n Ga _{1 -n} N base layer 112. (mask layer)". Removal of the selected portion of the group III nitride layer over the In _n G _{1 - n} aN base layer 112 may be performed by an etching process, such as wet chemical etch and/or dry plasma based etch (eg, reactive ion etching, inductively coupled plasma) Etching).

A first electrode contact 702 is exposed In G _{n 1 -} may be formed on part of the _n aN base layer 112. The first electrode contact 702 may be composed of one or more metals, which may include titanium, aluminum, nickel, gold, and one or more alloys thereof. The second electrode contact 704 can be formed over a portion of the p-contact layer 104, and the second electrode contact 704 can include nickel, gold, platinum, silver and one or more alloys thereof. It may be composed of the above metal layer. Upon formation of the first electrode contact 702 and the second electrode contact 704, current may pass through the light emitting device 700 to generate electromagnetic radiation, for example in the form of visible light. The light-emitting device 700 is generally referred to in this technology as “at least a portion of the current path between the first electrode contact 702 and the second electrode contact 704 includes a lateral pathway. device)”.

Also, although the following description describes an embodiment of manufacturing a light emitting device from the semiconductor structure 100, a further example of a light emitting device 800 made of the semiconductor structure 100, such as an LED, is shown in FIG. 8. It should be noted that such a manufacturing process can also be applied to semiconductor structures 200, 300, 400, 500.

More specifically, all or part of the growth template 113 is to enable exposure of the In _s Ga _{1 - s} N layer 656 or in some embodiments, the In _n Ga _{1 - n} N base layer ( 112) can be removed from the semiconductor structure 100 to enable exposure. Removal of all or part of growth template 113 may include one or more removal methods including wet etching, dry etching, chemical mechanical polishing, grinding and laser lift-off. When all or part of the removal of the growth template 113, a first electrode contact 802 In _n Ga ₁ as described previously _can be applied to _n N base layer 112. Thereafter, the second electrode contact 804 can be applied to a portion of the p-contact layer 104, thereby forming a light emitting device 800. Upon formation of the first electrode contact 802 and the second electrode contact 804, current may pass through the light emitting device 800 to generate electromagnetic radiation, for example in the form of visible light. Since the current path between the first electrode layer 802 and the second electrode layer 804 includes a substantially vertical path, the light emitting device 800 is generally referred to as a "vertical device" in this technique. It should be noted that.

In addition to the previously described manufacturing methods and processes for the production of non-limiting example light-emitting devices 700, 800, for example, for improving surface roughening and thermal dissipation to improve light extraction. It is noted that additional methods and processes known in the art may also be used, such as processes known in the art as "flip-chip bonding" among bonding to metallic carriers, and other well-known manufacturing methods. It should be noted.

A light emitting device according to an embodiment of the present disclosure, for example, an LED, may be manufactured and used as any type of light emitting device that integrates one or more LEDs therein. Embodiments of the LEDs of the present disclosure may be particularly suitable for use in applications that benefit from LEDs that operate under relatively high power and require relatively high luminosity. For example, the LEDs of the present disclosure may be particularly suitable for use in LED lamps and LED-based bulbs that can be used in building lighting, street lighting, automotive lighting, and the like.

Further embodiments of the present disclosure include a light emitting device that emits light comprising one or more LEDs described herein, such as the light emitting device 700 of FIG. 7 and the light emitting device 800 of FIG. 8. As a non-limiting example, the light emitting device may be as described, for example, in US Pat. No. 6,600,175 issued July 29, 2003 to Baretz et al., the disclosure of which is incorporated herein by reference in its entirety. Although included, it may include one or more LEDs as described herein.

14 illustrates an exemplary embodiment of a light emitting device 900 of the present disclosure that includes light emitting devices such as devices 700 and 800 described with reference to FIGS. 7 and 8. As shown in FIG. 14, the light emitting device 900 can include a container 902, at least a portion of which is at least substantially transparent to electromagnetic radiation in the visible region of the electromagnetic radiation spectrum. The container 902 can include, for example, an amorphous or crystalline ceramic material (eg, glass) or a polymer material. The LED 800 is disposed within the container 902 and can be mounted on a support structure 904 (eg, a printed circuit board or other substrate) within the container 902. The light emitting device 900 further includes a first electrical contact structure 906 and a second electrical contact structure 908. The first electrical contact structure 906 can be in electrical communication with one of the electrode contacts of the LED, such as the first electrode contact 802 (FIG. 8), and the second electrical contact structure 908 is the other of the electrode contacts of the LED. One, for example, may be in electrical communication with a second electrode contact 804 (FIG. 8). As a non-limiting example, the first electrical contact structure 906 can be in electrical communication with the first electrode contact 804 through the support structure 904, and the wire 910 can connect the second electrical contact structure 908. It can be used to electrically couple with the second electrode contact 804. Thus, the voltage provides a voltage and a corresponding current between the first and second electrode contacts 802 and 804 of the LED, such that the first electrical contact structure 906 of the light emitting device 900 to cause the LED to emit radiation. And the second electrical contact structure 908.

The light emitting device 900 is capable of self-emission of electromagnetic radiation (eg, visible light) when stimulated or excited by absorption of electromagnetic radiation emitted by one or more LEDs 800 within the container 902. Or it may further include a phosphorescent material (fluorescent or phosphorescent material). For example, the inner surface 912 of the container 902 may be at least partially coated with such a fluorescent or phosphorescent material. The one or more LEDs 800 can emit electromagnetic radiation of one or more specific wavelengths, and the fluorescent or phosphorescent material can include a mixture of various materials that emit radiation of various visible wavelengths, resulting in the light emitting device 900 Emits white light out of the container 902. Various types of phosphorescent and fluorescent materials are known in the art and can be employed in embodiments of the light emitting device of the present disclosure. For example, some such materials are disclosed in U.S. Patent No. 6,600,175 mentioned above.

Additional non-limiting examples of embodiments of the present disclosure are presented below.

Example _1: In _n Ga 1 having a polarity growth plane having a large growth in-plane lattice parameter greater than about 3.2 Angstroms _{- n} N base layer; It is disposed on the base layer, and includes a plurality of InGaN layers, wherein the plurality of InGaN layers comprises at least one In _w Ga _{1 - w} N well layer, and at least one In _b Ga _{1 - b} N barrier layer. In this case, w is 0.10≤w≤0.40, b is 0.01≤b≤0.10, the active region; The In _n Ga _{1 - n N} electron blocking layer disposed over the base layer and the opposite side of the active region; Is disposed on the electron blocking layer, In _p Ga _{1 -} N _p and including, the time, p is the 0.00≤p≤0.08, p- type bulk layer; And disposed on the p-type bulk layer, including In _c Ga _{1 - c} N, where c is 0.00≤c≤0.10, and a semiconductor structure including a p-type contact layer.

Example 2: The base layer further includes a growth template, the growth template includes a support substrate; And an In _s Ga _{1 - s} N seed layer disposed on the support substrate, wherein the growth plane of the In _s Ga _1-s N seed layer is a polar plane having a growth plane lattice parameter greater than about 3.2 Angstroms, At this time, s is 0.05≤s≤0.10, the bonding interface (bonding interface) is the semiconductor structure of Example 1 disposed between the support substrate and the In _s Ga _{1 - s} N seed layer.

Example 3: In the active region _cp Ga ₁ disposed between the electron blocking _layer, and further comprising a cap layer _cp N, at this time, cp The semiconductor structure of 0.01≤cp≤0.10 in Example 3.

Example 4: In _cp Ga _{1 - cp} N cap layer further disposed between the active region and the electron blocking layer, wherein cp is 0.01≤cp≤0.10, the semiconductor of any one of Examples 1 to 3 rescue.

Example 5: The electron blocking layer includes In _e Ga _{1 - e} N, where e is 0.01≤e≤0.02, the semiconductor structure of any one of Examples 1 to 4.

Example 6: The semiconductor structure of any one of Examples 1 to 5, wherein the electron blocking layer is at least substantially composed of GaN.

Example 7: The electron blocking layer is at least substantially composed of Al _e Ga _{1 - e} N, where e is 0.1≤e≤0.2, the semiconductor structure of any one of Examples 1-6.

Example 8: electron blocking layer is GaN and Al _e Ga _{1 -} has a superlattice structure comprising alternating layers of N _e, the time, e is the semiconductor structure of 0.1≤e≤0.2 of Example 7.

Example 9: the In _n Ga _{1 - n N} further includes an e-stop layer disposed between the base layer and the active region, and the electron stop layer comprises Al a Ga _{1 st -st} N At this time, st Is 0.01≤st≤0.20, the semiconductor structure of any one of Examples 1 to 8.

Example 10: The electron stop layer has a superlattice structure including alternating layers of GaN and Al _st Ga _{1 -st} N, where st is 0.01≤st≤0.2, the semiconductor structure of Example 9.

Example 11: the In _n Ga _{1 - n} N further comprises a strain relief layer disposed between the base layer and the active region, and wherein the strain relief layer are alternately In _sra Ga _sra N and In _srb Ga-1 _srb N It has a superlattice structure including a layer, where sra is 0.01≤sra≤0.10, srb is 0.01≤srb≤0.10, and sra is greater than srb, the semiconductor structure of any one of Examples 1 to 10.

Example 12: The semiconductor structure of any one of Examples 1-11, wherein the active region further comprises an additional barrier layer comprising GaN disposed between the at least one well layer and the at least one barrier layer.

Example 13: The semiconductor structure of any one of Examples 1 to 12, wherein the critical strain energy of the semiconductor structure is about 4500 or less.

Example 14: In _n Ga _{1 - n} N base layer, active region, electron blocking layer, p-type bulk layer and p-type contact layer Example 1 defining a growth stack exhibiting a percentage strain relaxation of 10% or less The semiconductor structure of any one of 13 to 13.

Example 15: The semiconductor structure of any one of Examples 1 to 14, wherein the p-type contact layer is at least substantially composed of GaN.

Example _{16: In n Ga 1 - n} N base layer of one embodiment of the examples 1 to 15 further comprising at least a second electrode contact portion of the top of the first electrode contact and p- type contact layer of at least a portion above a Semiconductor structure.

_N N base layer _- In _n Ga ₁ having a polarity growth plane having a large growth in-plane lattice parameter greater than about 3.2 angstroms;: Example 17 An active region disposed over the base layer, the active region comprising a plurality of InGaN layers, the plurality of InGaN layers comprising at least one well layer, and at least one barrier layer; An electron blocking layer disposed over the active region; P- type In _p Ga ₁ disposed on the electron blocking layer _{- p} N bulk layer; And p- type In _p Ga _{1 - p} N p- type that is placed on top of the bulk layer In _c Ga _{1 - c} N comprises the contact layer, and at this time, the critical strain energy of the light emitting device is less than or equal to about 4500 (au), a light emitting Device.

Example _{18: In n Ga 1 - n} N n The light emitting device of 0.01≤n≤0.10 of Example 17 in the base layer.

Example 19: at least one well layer is a In _w Ga _{1 -} comprises a _w N, at this time, w is the light-emitting device of 0.10≤w≤0.40 in Example 17 or Example 18.

Example 20: at least one barrier layer is In _b Ga _{1 -} a _b include N, at this time, b is any one of a light emitting device of 0.01≤b≤0.10 of Examples 17 to 19.

Example 21: The light emitting device of any one of Examples 17-20, wherein the electron blocking layer is at least substantially comprised of GaN.

Example 22: p- type In _p Ga _{1 -} N _p in the bulk layer is p 0.00≤p≤0.08 of Examples 17 to 21 The light emitting device of any one of.

Example 23: The light emitting device according to any one of Examples 17 to 22, wherein c in the p-type In _c Ga _{1 - c} N contact layer is 0.01≤c≤0.10.

Example 24: p- type In _c Ga _{1 - c} N contact layer is substantially one of a light emitting device of Examples 17 to 23, consisting of GaN.

Example 25: In _n Ga _{1 -} embodiment further includes a second electrode contact of N _c above at least a portion of the contact layer _{- n} N first electrode over at least a portion of the base layer and p- type contact In _c Ga ₁ The light emitting device of any one of 17 to 24.

Example 26: In _n Ga _{1 - n} N base layer, active region, electron blocking layer, p-type In _p Ga _{1 - p} N bulk layer and p-type In _c Ga _{1 - c} N contact layer than 1% The light emitting device of any one of Examples 17-25 forming a growth stack exhibiting low percentage strain relaxation.

Example 27: A method of forming a semiconductor structure, In _n Ga ₁ having a polarity growth plane having a large growth in-plane lattice parameter greater than about 3.2 Å _- providing a _n N base layer; Growing at least one In _w Ga _{1 - w} N well layer, and growing at least one In _b Ga _{1 - b} N barrier layer on the at least one well layer, and electron blocking over the active region Growing a layer, wherein w is 0.10≦w≦0.40, b is 0.01≦b≦0.10, and growing a plurality of InGaN layers to form an active region on the base layer; Step of growing a bulk layer _p N _- p- type In _p Ga ₁ on the electron blocking layer; And growing a p-type In _c Ga _{1 - c} N contact layer on the p-type In _p Ga _{1 - p} N bulk layer, wherein p is 0.00≤p≤0.08, c is 0.00 A method for forming a semiconductor structure of ≤c≤0.10.

Example 28: The step of providing the In _n Ga _{1 - n} N base layer further comprises forming a growth template; and forming the growth template comprises: providing a support substrate; And bonding an In _s Ga _{1 - s} N seed layer to the support substrate, wherein the growth plane of the In _s Ga _{1 - s} N seed layer has a growth plane lattice parameter greater than about 3.2 Angstroms. polar plane, and wherein the in _s Ga _{1 -} N _s method of embodiment s of the seed layer is 0.05≤s≤0.10 of example 27.

Example 29: growing an In _sp Ga _{1 -sp} N spacer layer on the In _s Ga _{1 - s} N seed layer opposite to the In _n Ga _{1 - n} N base layer; further comprising, In _sp The method of Example 28, wherein sp in the Ga _{1 - sp} N spacer layer is 0.01≤sp≤0.10.

Example 31: The step of growing the electron blocking layer includes growing the electron blocking layer to be composed of at least substantially In _e Ga _{1 -e} N, wherein e is 0.00≤e≤0.02 The method of any one of 27 to 30.

Example 32: The method of Example 31, wherein growing the electron blocking layer comprises growing an electron blocking layer to be at least substantially comprised of GaN.

Example 33: The step of growing the electron blocking layer includes the step of growing the electron blocking layer to include Al _e Ga _{1 - e} N, wherein e is 0.1≤e≤0.2, Examples 27 to 32 Either way.

Example 34: Growing the electron blocking layer further comprises growing the electron blocking layer to have a superlattice structure comprising alternating layers of GaN and Al _e Ga _{1 - e} N, where e is The method of Example 33 wherein 0.1≤e≤0.2.

Example 35: In _n Ga _{1 -} further comprising the step of growing the electron stopper layer disposed between the _n N base layer and the active region and, at this time, E-stop layer is Al _st Ga _{1 -} further comprising: _st N , At this time, 0.01≤st≤0.20, the method of any one of Examples 27 to 34.

Example 36: In _n Ga _{1 -} a step of growing a strain relief layer disposed between the _n N layer and the active areas more, and the strain relief layer are alternately In _sra Ga _sra N and In _srb Ga-1 _srb N It has a superlattice structure including a layer, wherein sra is 0.01≤sra≤0.10, srb is 0.01≤srb≤0.10, and sra is greater than srb in any one of Examples 27 to 35.

Example 37: forming an active region comprises at least one of In _w Ga _{1 -} growing a barrier layer of one or more further includes GaN between _b N barrier layer _{- w} N well layer and at least one of In _b Ga ₁ Method of any one of Examples 27 to 36 further comprising a.

Example 38: In _n Ga _{1 -} Example of defining the _n N base layer, the active area, an electron blocking layer, a p- type bulk layer and p- type contact layer is grown a stack showing a low percentage strain relief than 1% with The method of any one of 27 to 37.

Example 39: The method of Example 38 further comprising forming a growth stack to have a critical strain energy of about 4500 or less.

Example 40: The step of growing a p-type In _c Ga _{1 - c} N contact layer includes Examples 27 to comprising growing a p-type In _c Ga _{1 - c} N contact to consist at least substantially of GaN. Method of any one of 39.

Example 41: The method of Example 38 or Example 39 further comprising growing the growth stack in a single chemical vapor deposition system at a pressure between about 50 and about 500 mTorr.

Example 42: Growing an In _n Ga _{1 - n} N base and a p-type In _p Ga _{1 - p} N bulk layer in the chamber while flowing trimethylindium (TMI) and triethylgallium (TMG) through the chamber And wherein the flow rate ratio (%) of the flow rate of trimethylindium (TMI) to the flow rate of triethylgallium (TMG) is between about 50% and 95%.

The exemplary embodiments of the present disclosure described above do not limit the scope of the present invention, because these embodiments are only examples of embodiments of the present invention, which are only defined by the scope of the appended claims and their legal equivalents. to be. Any equivalent embodiment is intended to be within the scope of this invention. Indeed, various modifications of the present disclosure, other than those shown and described herein, such as useful combinations of alternatives to the elements described, will become apparent to those skilled in the art from the above description. Such variations and embodiments are also intended to fall within the scope of the appended claims.

Claims (14)

In the semiconductor structure,
3.2 In _n Ga _1-n N base layer having a polar growth plane having a growth plane lattice parameter greater than Angstroms;
A plurality of InGaN layers disposed on the base layer and including at least one In _w Ga _1-w N well layer, and at least one In _b Ga _1-b N barrier layer, wherein w is 0.10 ≤ w ≤ 0.40, and b is 0.01 ≤ b ≤ 0.10, an active region;
An electron blocking layer disposed on the active region opposite to the In _n Ga _1-n N base layer;
A p-type bulk layer disposed on the electron blocking layer, including In _p Ga _1-p N, wherein p is 0.00≤p≤0.08; And
It is disposed on the p-type bulk layer, includes In _c Ga _1-c N, and c includes a p-type contact layer of 0.00≤c≤0.10,
The base layer further includes a growth template, wherein the growth template is:
Support substrate; And
Disposed on the support substrate, the growth plane comprises an In _s Ga _1-s N seed layer, a polar plane having a growth plane lattice parameter greater than 3.2 Angstroms, wherein s is 0.05 ≤s≤0.10, a bonding interface is a semiconductor structure disposed between the support substrate and the In _s Ga _1-s N seed layer. According to claim 1,
In _sp Ga _1-sp N spacer layer disposed on the In _s Ga _1-s N seed layer opposite to the In _n Ga _1-n N base layer; and further comprising, the sp is 0.01≤ A semiconductor structure with sp≤0.10. According to claim 1,
And an In _cp Ga _1-cp N cap layer disposed between the active region and the electron blocking layer, wherein cp is 0.01≤cp≤0.10. According to claim 1,
The electron blocking layer is a semiconductor structure composed of GaN. According to claim 1,
And an electron stopping layer disposed between the In _n Ga _1-n N base layer and the active region, wherein the electron stopping layer includes Al _st Ga _1-st N, and the st Is 0.01≤st≤0.20 semiconductor structure. According to claim 1,
Further comprising a strain relief layer (strain relief layer) disposed between the In _n Ga _1-n N base layer and the active region,
The strain relief layer has a superlattice structure including alternating layers of In _sra Ga _sra N and In _srb Ga-1 _srb N, and the sra is 0.01≤sra≤0.10, and the srb Is 0.01≤srb≤0.10, and sra is a semiconductor structure larger than srb. According to claim 1,
The critical strain energy of the semiconductor structure is defined by the sum of the product of each layer thickness (nm) and the indium content (%) of each layer, 4500 The following semiconductor structure. A method of forming a semiconductor structure,
Providing an In _n Ga _1-n N base layer having a polar growth plane having a growth plane lattice parameter greater than 3.2 kPa;
Growing a plurality of InGaN layers over the base layer to form active regions;
Growing an electron blocking layer over the active region;
Growing a _p -type In _p Ga _1-p N bulk layer on the electron blocking layer; And
And growing a p-type In _c Ga _1-c N contact layer on the p-type In _p Ga _1-p N bulk layer.
The p is 0.00≤p≤0.08, the c is 0.00≤c≤0.10,
The step of growing the plurality of InGaN layers,
Growing at least one In _w Ga _1-w N well layer, and
And growing at least one In _b Ga _1-b N barrier layer on the at least one well layer, wherein w is 0.10 ≤ w ≤ 0.40, and b is 0.01 ≤ b ≤ 0.10,
The step of providing the In _n Ga _1-n N base layer may further include forming a growth template.
The step of forming the growth template,
Providing a support substrate, and
Bonding an In _s Ga _1-s N seed layer to the support substrate, wherein the growth plane of the In _s Ga _1-s N seed layer is a polar plane with a growth plane lattice parameter greater than 3.2 Angstroms, In the In _s Ga _1-s N seed layer, the s is 0.05≤s≤0.10 semiconductor structure forming method. The method of claim 8,
The step of growing the electron blocking layer includes growing the electron blocking layer made of GaN. The method of claim 8,
Further comprising the step of growing an electron stop layer disposed between the In _n Ga _1-n N base layer and the active region;
The electron stop layer includes Al _st Ga _1-st N, and st is 0.01≤st≤0.20. The method of claim 8,
Further comprising the step of growing a strain relief layer disposed between the In _n Ga _1-n N base layer and the active region;
The strain relief layer has a superlattice structure including alternating layers of In _sra Ga _sra N and In _srb Ga-1 _srb N, wherein sra is 0.01≤sra≤0.10, and srb is 0.01≤srb≤0.10, The sra is a method of forming a semiconductor structure larger than srb. The method of claim 8,
The step of growing the p-type In _c Ga _1-c N contact layer includes growing the p-type IncGa1-cN contact layer composed of GaN.

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