KR20150121410A - Semiconductor thin film transistor, method for manufacturing the same, array substrate and display device - Google Patents

Semiconductor thin film transistor, method for manufacturing the same, array substrate and display device Download PDF

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Publication number
KR20150121410A
KR20150121410A KR1020140047202A KR20140047202A KR20150121410A KR 20150121410 A KR20150121410 A KR 20150121410A KR 1020140047202 A KR1020140047202 A KR 1020140047202A KR 20140047202 A KR20140047202 A KR 20140047202A KR 20150121410 A KR20150121410 A KR 20150121410A
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South Korea
Prior art keywords
metal layer
electrode
insulating film
substrate
gate
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KR1020140047202A
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Korean (ko)
Inventor
전성곤
최규하
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네오뷰코오롱 주식회사
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Priority to KR1020140047202A priority Critical patent/KR20150121410A/en
Publication of KR20150121410A publication Critical patent/KR20150121410A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate

Abstract

The present invention provides a semiconductor device comprising a substrate 10, first and second auxiliary electrodes 21a and 22a formed on the substrate with the oxide insulating film 32 sandwiched therebetween, source and drain electrodes 22a and 22b formed on the first and second auxiliary electrodes, A gate insulating film formed on the active layer, and a gate electrode formed on a region corresponding to the active layer above the gate insulating layer, wherein the active layer is formed over the source and drain electrodes, And the oxide insulating film 32 is formed by oxidizing the metal layer formed on the substrate.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor thin film transistor, a method of manufacturing a semiconductor thin film transistor, an array substrate, and a display device.

The present invention relates to a semiconductor thin film transistor, a method of manufacturing the same, an array substrate provided with the semiconductor thin film transistor, and a display device including the array substrate, and more particularly to a semiconductor thin film transistor for a flat panel display using an auxiliary electrode, An array substrate, and a display device including the array substrate.

2. Description of the Related Art Flat panel display devices such as a liquid crystal display (LCD) and an organic light emitting display (OLED) have recently become common gate electrodes for reducing the resistance of these display devices, A separate auxiliary electrode is used in addition to the data electrode.

However, according to the addition of the auxiliary electrode, an additional etching process is required to etch the auxiliary electrode, thereby complicating the process and increasing the cost. In addition, the source and the drain of the thin film transistor (TFT) When auxiliary electrodes are stacked together in the drain region, there is a problem that the thickness of these layers is increased and a problem of step coverage with a semiconductor layer having a relatively thin thickness occurs, resulting in disconnection of the semiconductor layer or increase of resistance.

As a countermeasure against this, there is a technique described in Patent Document 1. FIG. 1 is a process sectional view showing a conventional array substrate manufacturing process described in Patent Document 1. FIG.

In the conventional array substrate manufacturing process of Patent Document 1, a first metal layer is formed on a transparent insulating substrate 101 and a gate wiring (not shown) and a gate electrode 108 are formed by patterning through a photo process and an etching process And a gate insulating film 112, an oxide semiconductor layer 119, an auxiliary metal layer 122, and a second metal layer 128 are sequentially formed thereon.

Thereafter, a photoresist is applied on the second metal layer 128, and subjected to a halftone exposure and development process to form the data line 132 in the region where the source and drain electrodes of the switching region TrA are to be formed, 1 photo pattern 191a is formed on the first metal pattern 128, the second photopattern 191b is formed in the spacing region between the source and drain electrodes, and the second metal layer 128 is exposed in the other regions.

Subsequently, the second metal layer 128, the auxiliary metal layer 122, and the oxide semiconductor layer 119 are sequentially etched by using different etchants using the first and second photolithography patterns 191a and 191b as masks, The data line 132 including the first and second dummy patterns 124 and 120 is formed together with the gate wiring of the window and the switching region TrA is partitioned and then the second phototransistor 132 is formed by ashing, The second metal layer 128 of the spacing region is removed by etching using the first phot pattern 191a as a mask to remove the source electrode 191b by exposing the spacing region between the source and drain electrodes, A portion of the auxiliary metal layer 122 between the source electrode 135 and the drain electrode 138 is exposed (see FIG. 1 (a)).

Subsequently, after removing the remaining first phot pattern 191a by a strip process, the array substrate 101 is subjected to a plasma treatment in a vacuum chamber of an oxygen atmosphere or a heat treatment at a temperature of 300 ° C to 400 ° C And an exposed portion of the auxiliary metal layer 122 in the spacing region is oxidized to form an oxide film 126 having an insulating characteristic (see FIG. 1 (b)).

There is also a technique described in Patent Document 2 as a technique for manufacturing a substrate array by a method similar to Patent Document 1.

However, in the prior arts of Patent Documents 1 and 2, a halftone mask for halftone exposure is required. Since a total of four etching processes, ashing, oxidation and photoresist stripping processes are required in the TFT manufacturing process, There is a problem that the manufacturing cost increases.

Patent Document 1: Published Patent Application No. 2010-0130490 (published on December 13, 2010) Patent Document 2: Published Patent Application No. 2010-0130523 (Dec. 13, 2010)

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems of the prior art described above, and it is an object of the present invention to provide a semiconductor thin film transistor capable of improving step coverage by auxiliary electrodes while reducing the number of process steps, And to provide the above-mentioned objects.

According to an aspect of the present invention, there is provided a semiconductor thin film transistor including a substrate, first and second auxiliary electrodes formed on the substrate with an oxide insulating film interposed therebetween, and source and drain electrodes formed on the first and second auxiliary electrodes, And an active layer formed over the source electrode and the drain electrode, a gate insulating film formed on the active layer, and a gate electrode formed in a region corresponding to the active layer on the gate insulating layer And the oxide insulating film is a film formed by oxidizing the metal layer formed on the substrate.

The array substrate of the present invention includes the semiconductor thin film transistor, a data line and a gate line formed so as to cross each other on the substrate, and a pixel formed in a crossing region where the data line and the gate line cross each other.

The display device of the present invention includes the array substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor thin film transistor, comprising: forming a metal layer on a substrate; forming a source electrode and a drain electrode on the metal layer; Forming an active layer on the source electrode and the drain electrode; forming a gate insulating film on the active layer; forming a gate insulating film on the gate insulating film; And forming a gate electrode in a region corresponding to the active layer.

According to the present invention, it is possible to omit the etching process for forming the auxiliary electrode contacting the source electrode and the drain electrode under the source electrode and the drain electrode, thereby simplifying the manufacturing process and reducing the manufacturing cost.

In addition, since the height of the oxide insulating film can be made approximately equal to the height of the source and drain electrodes by the expansion due to the oxidation of the metal layer in the oxidation process of the metal layer formed on the substrate, in the step of forming the active layer, It is possible to minimize disconnection of the active layer due to step coverage and increase in contact resistance.

1 is a process sectional view showing a conventional array substrate manufacturing process described in Patent Document 1,
2 is a cross-sectional view of an array substrate according to a preferred embodiment of the present invention,
3 is a process sectional view showing an array substrate manufacturing process according to a preferred embodiment of the present invention,
4 is a process sectional view showing an array substrate manufacturing process according to a preferred embodiment of the present invention,
5 is an electron micrograph of an oxide film formed by the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of an array substrate 100 according to a preferred embodiment of the present invention. In FIG. 2, only one data line and one pixel are shown for convenience of explanation.

The array substrate 100 of the preferred embodiment of the present invention is arranged such that a plurality of data wirings 31 and a plurality of gate wirings (not shown) cross each other on a substrate 10 made of a transparent material such as glass or plastic A plurality of pixels P are arranged in the intersecting region, and each of the plurality of pixels P includes a light emitting region composed of a light emitting element such as an LCD or an organic EL, and a semiconductor as a driving element for driving the light emitting element, And a thin film transistor (TFT).

The semiconductor thin film transistor (TFT) of the present embodiment includes a source electrode 21 and a drain electrode 22 formed on a substrate 10 made of a transparent material such as glass or plastic with an oxide insulating film 32 interposed therebetween, An active layer 23 formed on the insulating film 32, the source electrode 21, and the drain electrode 22; a gate insulating film 24 formed over the entire region of the substrate 10 including the upper portion of the active layer 23; And a gate electrode 26 formed in a predetermined region of the gate insulating film 24.

A portion of the gate insulating film 24 above the gate drain electrode 22 is exposed and a dummy electrode 27 formed of the same material as the gate electrode 26 in the step of forming the gate electrode 26 is formed in this exposed portion have.

A planarizing film 28 is formed on the entire region of the substrate 10 including the gate electrode 26 and the upper portion of the dummy electrode 27. The planarization film 28 is formed on the dummy electrode 27, At least a portion of the upper portion of the dummy electrode 27 is exposed and a pixel electrode 29 is formed in a predetermined region including the exposed upper portion of the dummy electrode 27. One of the pixel electrode 29 is electrically connected to the dummy electrode 27 And is connected to the drain electrode 22 of the semiconductor thin film transistor (TFT).

The characteristic of the semiconductor thin film transistor (TFT) of the present embodiment is that the oxide insulating film 32 is a layer formed by oxidizing the first metal layer 11 (see FIG. 3) formed on the substrate 10 in a manufacturing process described later, The lower portion of the source electrode 21 and the lower portion of the drain electrode 22 remain unoxidized in the oxidation process of the first metal layer 11 and the remaining layers are respectively connected to the source electrode 21 and the drain electrode 22, The auxiliary electrodes 21a,

2, the height of the oxide insulating film 32 is higher than the height of the source electrode 21 and the drain electrode 22 due to the expansion due to the oxidation of the first metal layer 11 in the oxidation process of the first metal layer 11 The step between the source electrode 21 and the drain electrode 22 and the active layer 23 is minimized in the step of forming the active layer 23 to thereby reduce the step coverage of the active layer 23 And the contact resistance can be prevented from increasing.

The etching process for forming the auxiliary electrodes 21a and 22a of the source electrode 21 and the drain electrode 22 can be omitted.

The data line 31 of the array substrate 100 is spaced apart from the semiconductor thin film transistor TFT by the oxide insulating film 32 and is formed at the end of the pixel P region and the source and drain electrodes 21 22 and the auxiliary electrode 31a formed of the same process and material as those of the auxiliary electrodes 21a, 22a.

Next, a method of manufacturing the substrate array 100 according to the preferred embodiment of the present invention will be described.

Figs. 3 and 4 are process sectional views showing an array substrate manufacturing process according to a preferred embodiment of the present invention.

First, as shown in Fig. 3 (a), a first metal layer 11 is formed on a transparent substrate 10 made of glass or plastic. Here, the first metal layer 11 is a layer to be used later as an auxiliary electrode and the oxide insulating film 32. In the present embodiment, the material for forming the first metal layer 11 is formed using molybdenum (Mo) The first metal layer 11 may be formed of a metal such as molybdenum alloy (MoW, MoNb), aluminum (Al), aluminum alloy (AlNd etc.), titanium (Ti), titanium alloy A material selected from a metal or an alloy which can be changed into an oxide film by oxygen plasma treatment, heat treatment or oxygen plasma treatment and heat treatment can be used.

Then, as shown in Fig. 3A, a data electrode layer 12 is formed on the first metal layer 11. The data electrode layer 12 is a layer that becomes a data wiring, a source electrode, and a drain electrode in a subsequent step. In this embodiment, ITO (Indium Tin Oxide) is formed by, for example, sputtering.

A resist pattern corresponding to the source electrode 21, the drain electrode 22, and the data line 31 is formed by applying a photoresist on the data electrode layer 12, exposing and developing it, The source electrode 21, the drain electrode 22 and the data line 31 are formed by a photolithography process and then a strip process is performed to remove the photoresist. As a result, as shown in FIG. 3 (b) 21, the drain electrode 22 and the data wiring 31, the first metal layer 11 is exposed.

Subsequently, the substrate 10 is introduced into a vacuum chamber (not shown) in an oxygen atmosphere, and subjected to a plasma treatment using the source electrode 21, the drain electrode 22 and the data wiring 31 as a mask to form a first metal layer Oxidizes the exposed portion of the substrate 11. In the present embodiment, the first metal layer 11 is oxidized at a temperature of 200 ° C to 500 ° C for several seconds to several tens of seconds by using PECVD (Plasma Enhanced Chemical Vapor Deposition).

As a result, the first metal layer 11 made of molybdenum is changed to molybdenum oxide to form an oxide insulating film 32 having an insulating property, and the source electrode 21, the drain electrode 22 and the lower portion of the data wiring 31 The first metal layer 11 of the region remains as the auxiliary electrode 21a, 22a, 31a of the source electrode 21 and the drain electrode 22 and the data wire 31, respectively.

As a method of oxidizing the first metal layer 11 with the oxide insulating film 32, a plasma treatment method other than the PECVD method, for example, a method of oxidizing the first metal layer 11 in an oven or a heating furnace in a temperature atmosphere of 300 ° C. to 400 ° C. A heat treatment method, or a combination of a PECVD method and a heat treatment method.

5, which shows an electron micrograph of the oxide film formed according to the present invention, compared with the thickness of the first metal layer 11 (see FIG. 5 (a)) before the oxidation process, (See Fig. 5 (b)) of the oxidized insulating film 32 oxidized by the oxidized film was increased by about 2.5 to 3.0 times.

The first metal layer 11 used as the auxiliary electrode is formed to have a thickness of 10 to 300 nm, preferably 20 to 150 nm. The first metal layer 11 is oxidized to form the oxide insulating film 32, The thickness of the first metal layer 11 is appropriately adjusted by making use of the fact that the thickness of the oxide insulating film 32 is thicker than the thickness of the first metal layer 11 before the oxidation to form the active layer 23 It is possible to minimize the step between the source electrode 21 and the drain electrode 22 and the active layer 23 to prevent disconnection of the active layer 23 due to step coverage and increase in contact resistance.

A semiconductor layer is formed on the substrate 10 on which the source electrode 21 and the drain electrode 22 and the oxide insulating film 32 are formed and is patterned into a predetermined shape to form the source electrode 21 and the drain electrode 22 An active layer 23 is formed over the oxide insulating film 32 between the source electrode 21 and the drain electrode 22 (FIG. 3 (d)).

A gate insulating film 24 is formed over the entire region of the substrate 10 including the upper portion of the active layer 23 by using an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiN x ) And a part of the drain electrode 22 is exposed by patterning by a mask process to form a first contact hole 25a (Fig. 4 (a)).

A metal layer is formed on the substrate 10 on which the gate insulating layer 24 is formed and patterned through a predetermined mask process to form the gate electrode 26. At this time, The first contact hole 25a is filled at the time of forming the metal layer so that the height of the first contact hole 25a is made equal to the height of the gate insulating film 24 so that the drain electrode 22, A dummy electrode 27 connecting between the anode electrodes 29 is formed (Fig. 4 (b)).

Of course, the dummy electrode 27 is not essential and may be removed in the patterning process for forming the gate electrode 26. However, the dummy electrode 27 may be removed in the patterning process for forming the gate electrode 26, It is preferable to form the dummy electrode 27 to facilitate the connection.

Subsequently, an inorganic insulating material or organic insulating material is applied to the upper surface of the substrate 10 on which the gate electrode 26 and the dummy electrode 27 are formed to form a planarization film 28, and patterned by a predetermined mask process to form dummy electrodes 27 The second contact hole 25b is formed (FIG. 4 (c)).

Then, a transparent conductive material such as ITO or IZO (Indium Zinc Oxide) is deposited on the planarizing film 28 formed with the second contact hole 25b and patterned by a mask process to form a second contact hole 25b The pixel electrode 29 connected to the drain electrode 22 is formed through the dummy electrode 27 of the pixel electrode 29 to complete the array substrate 100.

As described above, in the present invention, since the auxiliary electrode is formed by the oxidation process instead of etching the first metal layer, the number of etching processes in the semiconductor thin film transistor manufacturing process can be reduced, It is possible to manufacture a semiconductor thin film transistor having an electrode, so that the manufacturing cost can be reduced.

While the present invention has been described with reference to the preferred embodiments, it is not limited thereto, and various modifications and variations are possible within the scope of the present invention.

10 substrate
11 First metal layer
12 data electrode layer
21 source electrode
22 drain electrode
21a, 22a, 31a auxiliary electrode
23 active layer
24 gate insulating film
26 gate electrode
28 Planarizing film
29 pixel electrode
32 oxide insulating film

Claims (11)

A substrate;
First and second auxiliary electrodes formed on the substrate with an oxide insulating film therebetween,
A source electrode and a drain electrode formed on the first and second auxiliary electrodes,
An active layer formed over the source electrode and the drain electrode,
A gate insulating film formed on the active layer,
And a gate electrode formed in a region corresponding to the active layer above the gate insulating layer,
Wherein the oxide insulating film is a film formed by oxidizing a metal layer formed on the substrate. The method according to claim 1,
Wherein the metal layer is formed of any one of molybdenum, molybdenum alloy, aluminum, aluminum alloy, titanium, titanium alloy, and copper. A semiconductor thin film transistor according to any one of claims 1 to 2,
A data wiring and a gate wiring formed to cross each other on the substrate,
And a pixel formed in a crossing region where the data line and the gate line cross each other. A display device comprising the array substrate of claim 3. Forming a metal layer on the substrate;
Forming a source electrode and a drain electrode on the metal layer;
Forming an oxide insulating film by oxidizing the metal layer using the source electrode and the drain electrode as masks;
Forming an active layer on the source electrode and the drain electrode;
Forming a gate insulating film on the active layer,
And forming a gate electrode in a region corresponding to the active layer above the gate insulating film. The method of claim 5,
Wherein the metal layer is formed of any one of molybdenum, molybdenum alloy, aluminum, aluminum alloy, titanium, titanium alloy, or copper. The method of claim 5,
Wherein the oxidation is performed using PECVD (Plasma Enhanced Chemical Vapor Deposition). The method of claim 5,
Wherein the oxidation is performed using a heat treatment. The method of claim 5,
Wherein the oxidation is performed using both PECVD and heat treatment. The method of claim 5,
Wherein the metal layer has a thickness of 10 to 300 nm. The method of claim 10,
Wherein the metal layer has a thickness of 20 to 150 nm.
KR1020140047202A 2014-04-21 2014-04-21 Semiconductor thin film transistor, method for manufacturing the same, array substrate and display device KR20150121410A (en)

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