KR102259278B1 - Display device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a display device and a method for manufacturing the same, wherein a thin film transistor (TFT) of the display device includes: a gate connected to a gate line; a first hole passing through the insulating film; a second hole passing through the insulating layer and a first contact metal pattern in contact with the oxide semiconductor pattern and connected to the data line in the first hole; and a second contact metal pattern in contact with the oxide semiconductor pattern in the second hole and connected to the pixel electrode. The first and second contact metal patterns and the pixel electrode are formed of the same transparent electrode. The data line is formed of a metal different from that of the transparent electrode.

Description

Display device and manufacturing method thereof

The present invention relates to a display device including an oxide semiconductor thin film transistor (TFT) and a method for manufacturing the same.

In the display device, a TFT is formed in each pixel to switch a data voltage applied to the pixel or to drive the pixel. As for TFT, amorphous silicon TFT, polysilicon TFT, oxide semiconductor TFT, etc. are known.

Oxide semiconductor TFTs have higher mobility than amorphous silicon TFTs, can be manufactured in a low-temperature process, and are transparent through visible light. Therefore, an oxide semiconductor TFT is suitable for a high-resolution display device or a transparent display.

Oxide semiconductors are soluble in acidic solutions. Accordingly, the oxide semiconductor may be lost by the etchant when wet etching the metal stacked on the oxide semiconductor. Although the metal stacked on the oxide semiconductor may be dry etched, the surface of the oxide semiconductor may be damaged by plasma generated for the dry etching. An etch stopper is formed on the oxide semiconductor to prevent back etching of the oxide semiconductor.

The TFT array substrate of the display device uses a photo-mask process to pattern thin films such as TFTs, wirings, and pixel electrodes in a desired shape. The photomask process is a photolithography process technology in which a thin film is patterned into a desired shape by sequentially performing a series of processes such as thin film deposition, photoresist application process, photomask alignment, exposure, development, etching, and strip processes. . If the number of photomask processes is reduced, the manufacturing cost can be reduced and the yield can be increased.

In order to reduce the number of manufacturing processes for the TFT array substrate, a photoresist having a thickness difference may be formed by using a half-tone mask in the photomask process. A method of simultaneously forming a source-drain metal and a transparent electrode in one photomask process using such a halftone mask has been attempted. The source-drain metal may be selected from copper (Cu), and the transparent electrode may be generally selected from ITO (Indium-Tin Oxide). In this method, the same copper (Cu) is etched faster than ITO due to the difference in the etch ratio of copper (Cu) and ITO to the etchant, so that the ITO wiring width is copper (Cu) as shown in FIG. wider than the wiring width. When this method is applied to the data line, the data line is widened due to the ITO protruding out of both sides of the copper (Cu). In order to ensure reliability at high temperatures, a gap between the data line and the pixel electrode must be secured, and the gap is covered by a black matrix (BM). Since the gap between the data line and the pixel electrode must be secured, the aperture area of the pixel is narrowed by the ITO tail of the data line, so that the aperture ratio of the pixel is lowered.

The present invention provides a display device capable of increasing an aperture ratio of a pixel and a method of manufacturing the same.

The TFT of the display device of the present invention includes a gate connected to a gate line; a first hole passing through the insulating film; a second hole passing through the insulating layer and a first contact metal pattern in contact with the oxide semiconductor pattern and connected to the data line in the first hole; and a second contact metal pattern in contact with the oxide semiconductor pattern in the second hole and connected to the pixel electrode.

The first and second contact metal patterns and the pixel electrode are formed of the same transparent electrode. The data line is formed of a metal different from that of the transparent electrode.

The second contact metal pattern and the pixel electrode are integrated.

The drain is integrated with the data line. A separate source metal pattern connects the second contact metal pattern and the pixel electrode.

A gap between the first and second contact metal patterns is smaller than a gap between the drain of the TFT and the source metal pattern.

The method of manufacturing the display device may include forming an oxide semiconductor pattern on the gate insulating layer; and forming an insulating layer to cover the oxide semiconductor, forming a first photoresist pattern on the insulating layer, and then forming first and second holes having an undercut structure in the insulating layer under the first photoresist pattern and exposing the oxide semiconductor. A first contact metal pattern in contact with the oxide semiconductor pattern in the first hole by performing a contact hole filling process in the formed state, a second contact metal pattern in contact with the oxide semiconductor pattern in the second hole, and and simultaneously forming the pixel electrodes.

In the present invention, contact metal patterns and a pixel electrode are simultaneously formed as the same transparent electrode by performing a contact hole filling process in a state in which ESL holes having an undercut structure are formed, and a source-drain metal is formed by a separate photomask process. As a result, according to the present invention, it is possible to realize a short channel of the oxide semiconductor TFT and increase the stability of the contact hole filling process, as well as significantly increase the aperture ratio of the pixel.

1 is a diagram illustrating an example in which a transparent electrode protrudes out of a source-drain metal in a photomask process using a halftone mask.
2 is a plan view illustrating a pixel of a display device according to an exemplary embodiment of the present invention.
3A to 9B are diagrams illustrating a method of manufacturing the pixel illustrated in FIG. 2 .
10A to 10E are cross-sectional views illustrating defects in a contact hole filling process.
11A to 11B are diagrams illustrating another example of a pixel electrode pattern.
12 is a view showing a scanning electron microscope (SEM) image showing an undercut structure of an ESL hole.
13 is a view showing an effect of improving the aperture ratio in the display device of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

Referring to FIG. 2 , pixels of a display device according to an exemplary embodiment of the present invention have data lines DL, gate lines GL orthogonal to the data lines DL, data lines DL and a gate line. a TFT formed at the intersection of the GLs, a pixel electrode PIX connected to the TFT, a common electrode COM, a Vcom bus line CBUS for supplying a common voltage Vcom to the common electrode COM, etc. do.

The TFT is an oxide semiconductor TFT. When the oxide semiconductor TFT is implemented as a short channel having a short channel length (L) at a channel ratio (W/L), the filling rate of the pixel may be increased. In the photomask process, it is difficult to implement a short channel due to a short circuit between the drain and the source of the TFT. The present invention applies a contact hole filling process (CHF) to implement a short channel of an oxide semiconductor TFT without a short circuit between the drain and the source.

The present invention prevents protrusion of the transparent electrode caused by using the halftone mask by separately patterning the transparent electrode and the source-drain metal using a general photomask without using the halftone mask. Since the halftone mask is more expensive than a general photomask, the manufacturing cost can be lowered by replacing the halftone mask with a general photomask. The present invention can fabricate a TFT array with the same number of manufacturing steps as in the prior art without using a halftone mask.

3A to 9B are diagrams illustrating a method of manufacturing the pixel illustrated in FIG. 2 . 2A to 9B show the TFT and the pixel opening area of the pixel taken along the line "I-I" in Fig. 1;

The first photomask process will be described with reference to FIGS. 3A and 3B . 3A is a cross-sectional view, and FIG. 3B is a plan view.

3A and 3B , a gate metal is deposited on a substrate SUBS and the gate metal is partially etched by a first photomask process. As a result of the first photomask process, a gate metal pattern is formed on the substrate SUBS. The gate metal may be selected from copper (Cu), but is not limited thereto. The gate metal pattern includes a gate line GL, a Vcom bus line CBUS, and the like. The gate line GL is integrated with the gate of the TFT. The TFT is formed on the gate line GL. Next, a gate insulating layer GI is formed to cover the gate metal pattern. The gate insulating layer GI may be formed of silicon oxide (SiOx) capable of preventing a change in characteristics of the oxide semiconductor TFT.

The Vcom bus line CBUS is the same gate metal as the gate line GL and is formed on the same layer as the gate line GL. The Vcom bus line CBUS is in contact with the common electrode COM through a contact hole CNT penetrating the inorganic insulating layer and the protective layer.

The second photomask process will be described with reference to FIGS. 4A and 4B . 4A is a cross-sectional view, and FIG. 4B is a plan view.

4A and 4B , in the present invention, an oxide semiconductor pattern ACT is formed by depositing an oxide semiconductor on the gate insulating layer GI and performing a second photomask process to partially etch the oxide semiconductor. The oxide semiconductor may be selected from Indium-Galium-Zinc Oxide (IGZO), but is not limited thereto. The oxide semiconductor pattern ACT is formed on the TFT. The oxide semiconductor pattern ACT includes a short channel region of the TFT, a drain contact region and a source contact region separated with the short channel region interposed therebetween. The drain contact region is a portion in which the drain of the TFT is in contact with the oxide semiconductor pattern ACT. The source contact region is a portion where the source of the TFT is in contact with the oxide semiconductor pattern.

The third photomask process will be described with reference to FIGS. 5A and 5B . 5A is a cross-sectional view, and FIG. 5B is a plan view.

5A and 5B, in the present invention, an inorganic insulating film used as an etch stopper is deposited, and a first photoresist is applied thereon. Next, the present invention performs a third photomask process. In the third photomask process, the first photoresist is partially removed to form the first photoresist pattern PR1 , and the inorganic insulating layer exposed in the hole of the photoresist pattern PR1 is etched to form the oxide semiconductor pattern ACT. ) to form ESL holes EHOLE. The ESL holes EHOLE pass through the inorganic insulating layer and are divided into a first ESL hole exposing a drain contact region and a second ESL hole exposing a source contact region in the oxide semiconductor pattern ACT of the TFT. The inorganic insulating layer may be formed of SiOx. In order to prevent the oxide semiconductor pattern ACT from being etched and lost during wet etching of the contact metal pattern to be described later, the side surface of the etch stopper pattern ESL under the first photoresist pattern PR1 is undercut. , UC) structure should be overetched.

The gate insulating layer GI may be partially etched by performing a photomask process prior to the third photomask process in order to expose a portion of the gate metal pattern at the periphery of the display panel.

The undercut structure UC of the ESL holes EHOLE is implemented by continuously performing wet etching and dry etching. In the undercut structure UC of the ESL holes EHOLE, as shown in FIG. 12 , the side surface of the etch stopper pattern ESL from the inside under the first photoresist pattern PR1 gradually decreases with a low slope. is formed with If only wet etching is performed, the oxide semiconductor pattern ACT may also be melted due to the etchant that melts the inorganic insulating layer, and the oxide semiconductor pattern ACT may be lost. In order to prevent this problem, the third photomask process reduces the wet etch process time and further etches the etch stop layer ESL by a dry etch process following the wet etch process to prevent damage to the oxide semiconductor pattern ACT without damaging the etch stopper. The pattern ESL is patterned into an undercut structure.

In a state in which the ESL holes EHOLE are formed with the undercut structure UC, a contact hole filling process for realizing a short channel of the TFT is performed. In the contact hole filling process, the contact metal is formed in the ESL hole EHOLE separated with the short channel of the TFT interposed therebetween, and the pixel electrode PXL is formed at the same time. The contact metal may be formed of indium-tin oxide (ITO).

In the contact hole filling process, first, as shown in FIG. 6A , a contact metal CM is deposited to cover the first photoresist pattern PR1 and the gate insulating layer GI, and a second photoresist is applied thereon. Subsequently, in the contact hole filling process, an ashing process is performed to lower the thickness of the second photoresist to form the second photoresist pattern PR2 . The second photoresist pattern PR2 covers the contact metal in the ESL holes and covers the pixel electrode PXL made of the contact metal in the opening region of the pixel. The second photoresist pattern PR2 is filled in the ESL holes EHOLE of the undercut structure to protect the contact metal CM thereunder ( FIG. 6B ). Subsequently, the contact hole filling process removes the exposed contact metal CM by wet etching the contact metal CM ( FIG. 6C ). As a result, the contact metal pattern remains in the shape of a bowl extending to the side of the lower concave portion of the undercut structure UC in the ESL holes EHOLE. The contact metal pattern remaining in the opening region of the pixel remains as the pixel electrode PXL ( FIGS. 6D and 6E ). 6D and 6E are a cross-sectional view and a plan view of an example in which the contact metal pattern of the pixel electrode PXL and the contact metal pattern of the TFT are separated.

Only when the ESL holes EHOLE have the undercut structure UC, the second photoresist pattern PR2 can prevent over-etching of the contact metal CM and protect the oxide semiconductor pattern ACT from the etchant.

Regardless of the ashing imbalance of the second photoresist, a long wet etching process time may be applied based on a portion where ITO used as a contact metal is less exposed in the ESL holes EHOLE. Even if the wet etching process time is prolonged, the penetration path of the etchant is lengthened due to the second photoresist pattern PR2 filled in the lower concave portion of the undercut structure UC, so even if the wet etching process is prolonged, the ITO may be overetched or oxide The semiconductor pattern ACT is not lost. When the second photoresist pattern PR2 is removed by performing a strip process, unnecessary ITO is removed. In the strip process, the ITO film is removed together with the second photoresist pattern by the same method as the lift off process, so that an unnecessary entire ITO film is not left. Since the photoresist and the contact metal are partially lifted off on the substrate, there is no problem that the PR strip nozzle is clogged by the remaining ITO film caused when the lift-off process is performed on the entire substrate.

The fourth photomask process will be described with reference to FIGS. 7A and 7B . 7A is a cross-sectional view, and FIG. 7B is a plan view.

Referring to FIGS. 7A and 7B , in the fourth photomask process, a source-drain metal is deposited on a substrate, and the source-drain metal is partially etched to form a source-drain metal pattern. The source-drain metal may be copper (Cu), but is not limited thereto. The source-drain metal pattern includes a data line DL, a source metal pattern S of the TFT, and a Vcom contact electrode C, and the like. The data line DL is integrated with the drain of the TFT. The Vcom contact electrode C connects the Vcom bus line CBUS and the common electrode COM. The drain and the source of the TFT are in contact with the oxide semiconductor pattern ACT through the contact metal pattern CM, respectively. The contact metal pattern CM is an oxide semiconductor pattern defined by the first contact metal pattern formed in the drain contact region of the oxide semiconductor pattern ACTG defined by the first ESL hole EHOLE and the second ESL hole EHOLE. It is divided into a second contact metal pattern formed in the source contact region of (ACTG).

In the fourth photomask process, only the source-drain metal is patterned using a general photomask without using a halftone mask. Therefore, since there is no ITO under the source-drain metal pattern, there is no ITO tail protruding out of the source-drain metal pattern.

According to the current photomask process technology, in order to prevent a defect in which the source and drain of the TFT are short-circuited, the distance between the drain and the source must be at least 7 μm or more and the margin (MG) length must be greater than or equal to 7 μm. Therefore, the current photomask process technology makes it difficult to make the channel length of the TFT smaller than 7 μm, so that it is impossible to implement a short channel of the TFT. According to the present invention, a length smaller than the margin MG by forming adjacent ESL holes EHOLE with an etch stopper pattern ESL interposed therebetween and forming contact metal patterns CM therein through a contact hole filling process L) can be implemented. The short channel length L of the TFT is equal to the distance between the ESL holes EHOLE, and may be formed as short as 5 to 6 μm as possible through the contact hole filling process.

The fifth photomask process will be described with reference to FIGS. 8A and 8B . 8A is a cross-sectional view, and FIG. 8B is a plan view.

Referring to FIGS. 8A and 8B , in the fifth photomask process, a passivation layer material is deposited on the entire substrate to cover the source-drain metal pattern and the pixel electrode PXL, and the passivation layer material is partially etched. The passivation layer material may be SiOx, but is not limited thereto. As a result of the fifth photomask process, a contact hole CNT exposing the Vcom contact electrode C is formed in the passivation layer PAS.

The sixth photomask process will be described with reference to FIGS. 9A and 9B . 9A is a cross-sectional view, and FIG. 9B is a plan view.

9A and 9B , in the present invention, a common electrode COM is formed by depositing a transparent electrode material on a substrate SUBS and performing a sixth photomask process to partially etch the transparent electrode material. The common electrode COM is connected to the Vcom contact electrode C and the Vcom bus line CBUS through the contact hole CNT. The transparent electrode material may be selected as ITO. The pixel electrode PIX is connected to the source of the TFT and is formed in the opening region of the pixel to form an electric field together with the common electrode COM. The pixel electrode PIX is directly connected to the contact metal pattern CM through the source metal pattern S of the TFT formed of the source-drain metal pattern, or is integrated with the contact metal pattern CM as shown in FIGS. 11A and 11B .

The inventors of the present invention discovered a problem in that, if the ESL holes (EHOLE) are not formed as an undercut structure in the contact hole filling process through experiments, the ESL holes become non-uniform and the oxide semiconductor is damaged during wet etching of the contact metal. Hereinafter, an example in which a contact hole filling process is performed without an undercut structure will be described as a comparative example.

10A to 10E , in the comparative example, an ESL hole having no undercut structure is formed by etching the inorganic insulating layer exposed in the first photoresist pattern PR1 , and then the first photoresist pattern PR1 and the ESL are formed. A contact metal (CM) is deposited on the entire surface of the substrate to cover the holes. Next, in Comparative Example, a second photoresist is coated on the contact metal CM and then an ashing process is performed to lower the thickness of the second photoresist to form a second photoresist pattern PR2 . The second photoresist is filled in the ESL holes defined by the first photoresist pattern PR1 to protect the contact metal CM thereunder.

The thickness of the second photoresist and the ashing process are difficult to be uniform across the entire substrate. Due to the difference in ashing, the thickness of the second photoresist pattern PR2 in the ESL holes may vary depending on the position on the substrate. (a) of FIG. 10C is an example in which a large amount of the contact electrode CM is exposed in the ESL holes, and (b) of FIG. 10C shows that the thickness of the second photoresist pattern PR2 is relatively thick in the ESL holes. (CM) shows an example where the exposed portion is small.

When the contact metal (CM) is wet-etched based on (b) of FIG. 10C, the contact metal (CM) with many exposed portions in the ESL hole is over-etched, so that an oxide semiconductor pattern with an etchant as shown in (a) of FIG. 10D (ACT) may be lost. When the contact metal CM is wet-etched based on (a) of FIG. 10C , the small contact metal CM exposed in the ESL hole remains in a bowl shape as shown in FIG. 10D (b). Therefore, if the contact hole filling process is performed in a state in which the ESL hole is not formed into an undercut structure, the level of process defect is greatly affected by the thickness difference of the second photoresist and the non-uniformity of the ashing process. In Comparative Example, since the penetration path of the etchant is short, the oxide semiconductor may be easily damaged. In contrast, in the present invention, in the contact hole filling process, the ESL hole is formed into an undercut structure to lengthen the penetration path of the etchant, so that the contact metal in the ESL hole can be uniformly retained even if there is a difference in the thickness of the second photoresist and uneven ashing process. Also, the loss of the oxide semiconductor pattern ACT may be prevented.

In the comparative example, as shown in FIG. 10A , the source-drain metal and the pixel electrode may be patterned in one photomask process using a halftone mask. In this case, the pixel electrode protrudes out of the source-drain metal pattern due to the difference in the etch rate. The opening area of the pixel is reduced by the protruding portion (ITO tail) of the pixel electrode. In the comparative example, since the source-dray metal and the pixel electrode are formed in one photomask process after the contact metal pattern is formed, the contact metal pattern and a portion of the pixel electrode are stacked in the ESL hole. The present invention prevents the pixel electrode from protruding out of the source-drain metal pattern by patterning the contact metal and the pixel electrode in the ESL hole by the contact hole filling process and patterning the source-drain metal by the photomask process using a general photomask. do. In the present invention, since the contact metal and the pixel electrode are simultaneously patterned without a photomask, the number of manufacturing steps is not increased compared to the comparative example. In addition, since the present invention simultaneously patterns the contact metal and the pixel electrode, only a single-layered contact metal pattern is formed in the ESL hole. The contact hole filling process of the present invention may integrate the contact metal pattern CM and the pixel electrode PXL as shown in FIGS. 11A and 11B . A neck end PXL_neck of the pixel electrode PXL is connected to the contact metal pattern CM. In this case, the source of the TFT may be connected to the pixel electrode PXL without the source-drain metal pattern. 6A and 6E show that the contact metal pattern CM and the pixel electrode PXL are simultaneously formed in the contact hole filling process, but the pixel electrode pattern is separated from the contact metal pattern CM so that the patterns are mutually formed as a source-drain metal pattern. A linked example is shown.

13 is a view showing an effect of improving the aperture ratio in the display device of the present invention.

Referring to FIG. 13 , the figure on the left is a comparative example (Ref.) in which Cu (source-drain metal pattern) and ITO (pixel electrode) are simultaneously formed by a photomask process using a halftone mask, and contact holes without undercut structures This is an example in which contact metal patterns are formed by performing a peeling process. In the figure on the right, contact metal patterns and pixel electrodes are simultaneously formed of ITO by performing a contact hole filling process in a state in which ESL holes having an undercut structure are formed, and Cu selected as a source-drain metal is formed by a separate photomask process. It is an embodiment of the present invention. In the present invention, since there is no ITO tail, the aperture ratio of the pixel is widened by 12.3% compared to the comparative example (Ref.).

The display device of the present invention can be applied to any flat panel display device in which a TFT is formed for each pixel. For example, the TFT array substrate of the above-described embodiment may be applied to a liquid crystal display of an In-Plane Switching (IPS) mode or a Fringe Field Switching (FFS) mode. In the above embodiment, when the pixel electrode PXL is connected to the anode of an organic light emitting diode (OLED), it can be applied as an organic light emitting diode display (OLED Display).

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUBS: Substrate GI: Gate Insulation Film
GE, GL: Gate metal pattern ACT: Oxide semiconductor pattern
DL, C, S: source-drain metal pattern ESL: etch stopper pattern
EHOLE: ESL hole PR1, PR2: photoresist pattern
CM: contact metal pattern PAS: protective film
COM: common electrode PXL: pixel electrode

Claims (12)

A display device comprising: a thin film transistor formed at an intersection of a gate line and a data line; and a pixel electrode connected to the thin film transistor;
The thin film transistor,
a gate connected to the gate line;
a first insulating film covering the gate;
an oxide semiconductor pattern disposed on the first insulating layer to overlap the gate;
a second insulating layer having first and second holes exposing top surfaces of the drain region and the source region of the oxide semiconductor pattern, respectively;
a first contact metal pattern located in the first hole, in contact with an upper surface of a drain region of the oxide semiconductor pattern and a sidewall of the second insulating layer, and connected to the data line; and
a second contact metal pattern located in the second hole, in contact with an upper surface of the source region of the oxide semiconductor pattern and another sidewall of the second insulating layer, and connected to the pixel electrode, the first and second contact metal patterns; A display device in which the pixel electrode is formed of the same transparent electrode, and the data line is formed of a metal different from that of the transparent electrode. The method of claim 1,
A display device in which the second contact metal pattern and the pixel electrode are integrated. The method of claim 1,
The thin film transistor,
a drain metal pattern integrated with the data line and in contact with one end of the oxide semiconductor pattern; and
and a source metal pattern formed of the same metal as the data line and contacting the other end of the oxide semiconductor pattern,
the source metal pattern connects the second contact metal pattern and the pixel electrode;
A gap between the first and second contact metal patterns is narrower than a gap between the drain of the thin film transistor and the source metal pattern. forming a gate metal pattern including a gate line and a Vcom bus line on a substrate and forming a first insulating layer covering the gate metal pattern on the substrate;
forming an oxide semiconductor pattern on the first insulating layer; and
A second insulating layer is formed to cover the oxide semiconductor, a first photoresist pattern is formed on the second insulating layer, and an undercut structure is formed in the second insulating layer under the first photoresist pattern, a drain region of the oxide semiconductor and A first contact metal pattern in contact with the oxide semiconductor pattern in the first hole and a first contact metal pattern in the second hole by performing a contact hole filling process in a state in which first and second holes respectively exposing the upper surface of the source region are formed and simultaneously forming a second contact metal pattern in contact with the oxide semiconductor pattern, and a pixel electrode,
the first contact metal pattern is located in the first hole and is in contact with an upper surface of a drain region of the oxide semiconductor pattern and a sidewall of the second insulating layer;
The second contact metal pattern is located in the second hole, is in contact with an upper surface of the source region of the oxide semiconductor pattern and the other sidewall of the second insulating layer, and is connected to the pixel electrode.
A method of manufacturing a display device in which the first and second contact metal patterns and the pixel electrode are formed of the same transparent electrode. The method of claim 4,
The method of manufacturing a display device, wherein the undercut structure of the first and second holes is formed by wet etching the second insulating layer and then dry etching the second insulating layer. The method of claim 5,
The contact hole filling process,
depositing a contact metal to cover the first photoresist pattern and the first insulating layer;
forming a second photoresist pattern covering the contact metal in the first and second holes and covering the opening area of the pixel;
wet etching the exposed contact metal over the first and second photoresist patterns;
and removing unnecessary contact metal by removing the first and second photoresist patterns, and simultaneously forming the first contact metal pattern, the second contact metal pattern, and the pixel electrode. The method of claim 4,
A method of manufacturing a display device in which the second contact metal pattern and the pixel electrode are integrated. delete The method of claim 1,
The pixel electrode and the second contact metal pattern are separated from each other. The method of claim 9,
The pixel electrode is positioned in a third hole formed in the second insulating layer in a pixel region, and is in contact with an upper surface of the first insulating layer and a sidewall of the second insulating layer. The method of claim 4,
The pixel electrode and the second contact metal pattern are separated from each other. The method of claim 11,
The pixel electrode is positioned in a third hole formed in the second insulating layer in a pixel region, and is in contact with an upper surface of the first insulating layer and a sidewall of the second insulating layer.

Images