CN108198825B - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- CN108198825B CN108198825B CN201810058977.7A CN201810058977A CN108198825B CN 108198825 B CN108198825 B CN 108198825B CN 201810058977 A CN201810058977 A CN 201810058977A CN 108198825 B CN108198825 B CN 108198825B
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- 239000000758 substrate Substances 0.000 title claims abstract description 109
- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 239000010410 layer Substances 0.000 claims description 268
- 229920002120 photoresistant polymer Polymers 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 41
- 239000011229 interlayer Substances 0.000 claims description 25
- 229910044991 metal oxide Inorganic materials 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 238000004380 ashing Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 22
- 239000000463 material Substances 0.000 abstract description 20
- 239000010409 thin film Substances 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 239000012212 insulator Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The application discloses an array substrate, a preparation method thereof and a display panel, which are used for simplifying the preparation process flow of the array substrate, reducing the number of photomask times and reducing the production cost. An array substrate provided by the embodiment of the application comprises: a substrate and a thin film transistor disposed over the substrate; the thin film transistor includes: the thin film transistor comprises a source electrode, a drain electrode, an active layer, a first grid insulating layer and a grid electrode, wherein the source electrode and the drain electrode are sequentially arranged on the substrate, the active layer is connected with the source electrode and the drain electrode, and the thin film transistor further comprises: a light-shielding layer provided between the active layer and the substrate and between the source electrode and the drain electrode; the light shielding layer comprises a metal layer made of the same material as the source electrode and the drain electrode, and an insulating layer covering the adjacent surface of the metal layer and the active layer.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
Because of its high mobility, Low Temperature Polysilicon (LTPS) array substrates are widely used in Organic Light-Emitting Diode (OLED) displays and Liquid Crystal (LC) displays. As polycrystalline silicon (P-Si) is irradiated by light and can generate carriers to increase device leakage current, which affects device performance, especially for LC display, as shown in fig. 1, the LTPS includes a light shielding layer 4, an insulating layer 9, a source contact region 23, a drain contact region 24, an active layer 5, a gate insulating layer 6, a gate electrode 7, a source electrode 2, and a drain electrode 3, which are sequentially disposed on a substrate 1, the active layer is P-Si, that is, the LTPS array substrate for LC display needs to additionally dispose a light shielding layer to prevent a backlight source from irradiating P-Si, so that the basic preparation process of the LTPS array is complex; for the OLED display, although a backlight source is not required to be arranged, the LTPS array substrate in the prior art is not provided with a light shielding layer, but for the transparent OLED display, light still irradiates on P-Si, the device performance is affected, the increase of the light shielding layer increases the array substrate preparation process, and because the light shielding layer needs to be patterned layer by layer, the number of times of a photomask (mask) needs to be additionally increased. In summary, the light shielding layer arranged in the prior art for preventing the light from irradiating the P-Si has complex process flow and many mask times.
Disclosure of Invention
The embodiment of the application provides an array substrate, a preparation method of the array substrate and a display panel, which are used for simplifying the preparation process flow of the array substrate, reducing mask times and reducing production cost.
An array substrate provided by the embodiment of the application includes: a substrate and a thin film transistor disposed over the substrate; the thin film transistor includes: the thin film transistor comprises a source electrode, a drain electrode, an active layer, a first grid insulating layer and a grid electrode, wherein the source electrode and the drain electrode are sequentially arranged on the substrate, the active layer is connected with the source electrode and the drain electrode, and the thin film transistor further comprises: a light-shielding layer provided between the active layer and the substrate and between the source electrode and the drain electrode; the light shielding layer comprises a metal layer made of the same material as the source electrode and the drain electrode, and an insulating layer covering the adjacent surface of the metal layer and the active layer.
According to the array substrate provided by the embodiment of the application, as the light shielding layer is arranged between the active layer and the substrate and between the source electrode and the drain electrode, and the light shielding layer comprises the metal layer which is the same as the material of the source electrode and the drain electrode, namely the source electrode, the drain electrode and the light shielding layer are arranged on the same layer and comprise the same metal material, no additional light shielding layer material is required to be deposited when the array substrate is prepared, and the source electrode, the drain electrode and the light shielding layer can be formed by adopting a mask, so that the preparation process flow of the array substrate is simplified, the use times of the light shielding layer are reduced, and the production cost is reduced.
Optionally, the insulating layer is a metal oxide of the metal layer.
Optionally, a gap exists between the light-shielding layer and the source electrode, and a gap exists between the light-shielding layer and the drain electrode;
the active layer is filled in the gap.
Optionally, the array substrate further includes:
the first electrode is arranged on the same layer as the grid electrode, and the second grid insulating layer, the second electrode, the insulating flat layer and the metal electrode are sequentially arranged on the first grid electrode and the first electrode;
the first electrode and the second electrode form a capacitor structure;
the metal electrode is connected with the drain electrode through a via hole penetrating through the first gate insulating layer, the second gate insulating layer and the insulating flat layer.
Optionally, the insulating planarization layer includes an interlayer insulating layer and a planarization layer located above the interlayer insulating layer, and the planarization layer and the interlayer insulating layer are made of the same material.
According to the array substrate, the interlayer insulating layer and the planarization layer can be made of the same material, so that after the interlayer insulating layer and the planarization layer are deposited, the interlayer insulating layer and the planarization layer can be formed only by adopting one step of mask and etching process, the preparation process of the array substrate is further simplified, the mask and the etching are further reduced, and the production cost is saved.
The display panel provided by the embodiment of the application comprises the array substrate provided by the embodiment of the application.
The array substrate preparation method provided by the embodiment of the application is characterized by comprising the following steps:
forming patterns of a source electrode, a light shielding layer and a drain electrode on the substrate;
forming a pattern of an active layer over the pattern of the source electrode, the light-shielding layer, and the drain electrode;
forming a first gate insulating layer over the pattern of the active layer;
a gate electrode is patterned over the first gate insulating layer.
Optionally, forming a pattern of a source electrode, a light shielding layer, and a drain electrode on the substrate specifically includes:
depositing a metal layer on the substrate;
coating photoresist on the metal layer;
processing the photoresist by adopting a halftone mask process, and forming a photoresist pattern in a region where a source electrode, a drain electrode and a light shielding layer are required to be formed, wherein the thickness of the photoresist pattern in the region where the light shielding layer is required to be formed is smaller than the thickness of the photoresist pattern in the region where the source electrode and the drain electrode are required to be formed;
etching the metal layer to form patterns of a source electrode, a shading metal layer and a drain electrode;
processing the photoresist pattern by adopting an ashing process, completely removing the photoresist pattern on the shading metal layer, and forming a metal oxide on the surface of the shading metal layer to obtain a pattern of a shading layer;
and stripping the residual photoresist above the source electrode and the drain electrode by adopting a photoresist stripping process.
According to the array substrate preparation method provided by the embodiment of the application, when the photoresist pattern is processed by adopting an ashing process, the photoresist pattern on the shading metal layer is completely removed by using oxygen plasma, and the oxygen plasma reacts with the shading metal layer to form a pattern of a shading layer comprising a metal layer and metal oxide; and, because the photoresist is processed by adopting the half-tone mask process, the thickness of the photoresist pattern of the region where the light shielding layer needs to be formed is smaller than that of the region where the source electrode and the drain electrode need to be formed, so that the photoresist pattern on the light shielding layer is completely removed and the metal oxide is formed in the ashing process of the photoresist pattern after the metal layer is etched, and the photoresist pattern of the region of the source electrode and the drain electrode is not completely removed, thereby the source electrode and the drain electrode pattern can be prevented from being oxidized while the light shielding layer comprising the metal oxide is formed, namely, the array substrate preparation method provided by the embodiment of the application can form the patterns of the source electrode, the drain electrode and the light shielding layer by only one mask under the condition that only one metal layer is deposited and the source electrode and the drain electrode are not damaged, compared with the prior art, the array substrate preparation process flow can be simplified, the number of times of using the photomask is reduced, and the production cost is reduced.
Optionally, the method further comprises:
forming a pattern of a first electrode while forming a pattern of a gate electrode;
forming a second gate insulating layer over the pattern of the gate electrode and the first electrode;
forming a pattern of a second electrode over the second gate insulating layer;
forming an insulating planarization layer over the pattern of the second electrode;
forming a via hole penetrating through the first gate insulating layer, the second gate insulating layer and the insulating flat layer;
and forming a pattern of a metal electrode on the insulating flat layer, wherein the pattern of the metal electrode is connected with the drain electrode through the via hole.
Optionally, the forming of the insulating planarization layer over the pattern of the second electrode specifically includes:
and sequentially depositing two layers of the same insulating materials on the pattern of the second electrode and carrying out a patterning process to form an insulating layer comprising an interlayer insulating layer and a planarization layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a LTPS array substrate including a light-shielding layer according to the prior art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural view of another array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 6 is a schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic view illustrating another method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic view illustrating a method for manufacturing another array substrate according to an embodiment of the present disclosure.
Detailed Description
The embodiment of the application provides an array substrate, a preparation method thereof and a display panel, which are used for simplifying the preparation process flow of the array substrate, reducing the mask times and reducing the production cost.
As shown in fig. 2, the array substrate provided in the embodiment of the present application includes: a substrate 1 and a thin film transistor disposed over the substrate 1; the thin film transistor includes: the thin film transistor comprises a source electrode 2, a drain electrode 3, an active layer 5 connected with the source electrode 2 and the drain electrode 3, a first gate insulating layer 6 and a gate electrode 7 which are sequentially arranged on the substrate 1, and further comprises: a light-shielding layer 4 provided between the active layer 5 and the substrate 1 and between the source electrode 2 and the drain electrode 3; the light shielding layer 4 includes a metal layer 8 made of the same material as the source electrode and the drain electrode, and an insulating layer 9 covering a surface of the metal layer 8 adjacent to the active layer 5.
According to the array substrate provided by the embodiment of the application, the light shielding layer is arranged between the active layer and the substrate and between the source electrode and the drain electrode, and the light shielding layer comprises the metal layer which is the same as the source electrode and the drain electrode in material, namely the source electrode, the drain electrode and the light shielding layer are arranged on the same layer and comprise the same metal material, so that the light shielding layer material does not need to be additionally deposited when the array substrate is prepared, and the source electrode, the drain electrode and the light shielding layer can be formed by adopting one mask, so that the preparation process flow of the array substrate is simplified, the use times of the light shielding layer are reduced.
Optionally, in the array substrate shown in fig. 2 provided in this embodiment of the present application, the insulating layer 9 is a metal oxide of the metal layer 8. The metal layer in the light-shielding layer may be made of the same material as that of the source and the drain, for example, aluminum or tungsten, and correspondingly, the insulating layer may be aluminum oxide or tungsten oxide. Of course, the material of the metal layer, the source electrode and the drain electrode can also be selected from other metal materials which can form oxide with good insulating property.
Optionally, in the array substrate shown in fig. 2 provided in this embodiment of the present application, a gap exists between the light-shielding layer 4 and the source electrode 2, and a gap exists between the light-shielding layer 4 and the drain electrode 3;
the active layer 5 fills the gap.
Optionally, the active layer is made of polysilicon, that is, the array substrate provided in this embodiment of the present application is an LTPS array substrate.
Optionally, as shown in fig. 3, in the array substrate provided in the embodiment of the present application, the substrate 1 includes a substrate base plate 11 and a buffer layer 10 located on the substrate base plate 11. As shown in fig. 3, there is a gap between the light-shielding layer and the source and drain electrodes, and after the active layer is disposed, there is an active layer material in the gap, and the buffer layer is disposed to prevent the active layer material from directly contacting the substrate, thereby preventing the active layer from being damaged by components in the substrate.
The array substrate provided by the embodiment of the application can be applied to liquid crystal display and also can be applied to OLED display.
When the array substrate provided in the embodiment of the present application is applied to an OLED display, optionally, as shown in fig. 4, the array substrate provided in the embodiment of the present application includes: the organic Light Emitting Diode (LED) comprises a substrate 11, a buffer Layer 10, a source electrode 2, a drain electrode 3, a shading Layer 4, an active Layer 5, a first Gate Insulator (GI) 6, a gate electrode 7, a first electrode 12, a second gate insulator 13, a second electrode 14, an insulating flat Layer 22 and a metal electrode 18, wherein the buffer Layer 10, the source electrode 2, the drain electrode 3 and the shading Layer 4 are sequentially arranged on the substrate 11, the insulating flat Layer 22 comprises an interlayer Insulator (ILD) 15 and a Planarization Layer (PLN) 16, the first electrode 12 and the second electrode 16 form a capacitor structure, and the metal electrode 18 is connected with the drain electrode 3 through a via hole penetrating through the first gate insulator 6, the second gate insulator 13 and the insulating flat Layer 22.
In fig. 4, the interlayer insulating layer 15 and the planarization layer 16 may be made of the same material, so that after the interlayer insulating layer and the planarization layer are deposited, the interlayer insulating layer and the planarization layer may be formed only by using a mask and an etching process, thereby further simplifying the array substrate preparation process, further reducing the mask and the etching, and saving the production cost.
Of course, the array substrate applied to the OLED display provided in the embodiment of the present application may also be combined with the interlayer insulating layer 15 and the planarization layer 16 into the same film layer as shown in fig. 5, so as to further simplify the array substrate manufacturing process.
When the same material is used for the interlayer insulating layer and the planarizing layer, the material of the interlayer insulating layer and the planarizing layer may be, for example, silicon on insulator (SOG). The metal electrode 18 in fig. 4, 5 may be an anode, for example.
The display panel provided by the embodiment of the application comprises the array substrate provided by the embodiment of the application.
Corresponding to the array substrate provided in the embodiment of the present application, an embodiment of the present application further provides a method for manufacturing an array substrate, as shown in fig. 6, the method includes:
s501, forming patterns of a source electrode, a shading layer and a drain electrode on the substrate;
s502, forming a pattern of an active layer on the pattern of the source electrode, the shading layer and the drain electrode;
s503, forming a first gate insulating layer on the pattern of the active layer;
and S504, forming a grid pattern on the first grid insulating layer.
According to the array substrate preparation method provided by the embodiment of the application, the source electrode, the drain electrode and the shading layer are arranged on the same layer and comprise the same metal material, so that extra shading layer material does not need to be deposited, and a mask can be adopted to form the source electrode, the drain electrode and the shading layer, so that the thin film transistor preparation process flow is simplified, the use times of a photomask are reduced, and the production cost is reduced.
Optionally, the step S501 of forming the pattern of the source electrode, the light-shielding layer, and the drain electrode on the substrate specifically includes:
depositing a metal layer on the substrate;
coating photoresist on the metal layer;
processing the photoresist by adopting a halftone mask process, and forming a photoresist pattern in a region where a source electrode, a drain electrode and a light shielding layer are required to be formed, wherein the thickness of the photoresist pattern in the region where the light shielding layer is required to be formed is smaller than the thickness of the photoresist pattern in the region where the source electrode and the drain electrode are required to be formed;
etching the metal layer to form patterns of a source electrode, a shading metal layer and a drain electrode;
processing the photoresist pattern by adopting an ashing process, completely removing the photoresist pattern on the shading metal layer, and forming a metal oxide on the surface of the shading metal layer to obtain a pattern of a shading layer;
and stripping the residual photoresist above the source electrode and the drain electrode by adopting a photoresist stripping process.
According to the array substrate preparation method provided by the embodiment of the application, when the photoresist pattern is processed by adopting an ashing process, for example, oxygen plasma can be utilized, so that the photoresist pattern on the light shielding metal layer is completely removed, and the oxygen plasma reacts with the light shielding metal layer to form the pattern of the light shielding layer comprising the metal layer and the metal oxide. Moreover, because the photoresist is processed by adopting the halftone mask process, the thickness of the photoresist pattern of the region where the light shielding layer needs to be formed is smaller than the thickness of the photoresist pattern of the region where the source and the drain need to be formed, for example, the thickness of the photoresist pattern of the region where the source and the drain need to be formed is 5 micrometers, and the thickness of the photoresist pattern of the region where the light shielding layer needs to be formed is 2 micrometers, thus, in the process of performing the ashing process on the photoresist pattern, the photoresist pattern on the pattern of the light shielding metal layer is completely removed and the metal oxide is formed, while the photoresist pattern of the region of the source and the drain is not completely removed, so that the source and the drain patterns can be prevented from being oxidized while the light shielding layer including the metal oxide is formed, namely, the array substrate preparation method provided by the embodiment of the present application can prevent the source and the drain from being oxidized while only depositing one, the patterns of the source electrode, the drain electrode and the shading layer can be formed by only one mask, compared with the prior art, the array substrate manufacturing process flow can be simplified, the use times of the photomask can be reduced, and the production cost can be reduced.
Taking an example that a substrate includes a substrate base plate and a buffer layer, and the photoresist layer is processed by using a halftone mask process, the array substrate preparation method provided by the embodiment of the present application is exemplified, as shown in fig. 7, the array substrate preparation method provided by the embodiment of the present application includes the following steps:
s601, forming a buffer layer 10 on a substrate 11, and depositing a metal material 19 on the buffer layer 10 to form a metal layer;
s602, coating the photoresist 20, processing the photoresist 20 by adopting a half-tone mask process, and forming a photoresist pattern in a region where a source electrode, a drain electrode and a light shielding layer need to be formed, wherein the thickness of the photoresist pattern in the region where the light shielding layer needs to be formed is smaller than the thickness of the photoresist pattern in the region where the source electrode and the drain electrode need to be formed;
s603, etching the metal layer to form patterns of the source electrode 2, the drain electrode 3 and the shading metal layer 21;
s604, processing the photoresist 20 by adopting an ashing process, completely removing the photoresist on the pattern of the shading metal layer 21, and forming a metal oxide 9 on the surface of the shading metal layer 21 to obtain the pattern of the shading layer 4;
s605, stripping the residual photoresist layer on the source electrode 2 and the drain electrode 3 by adopting a photoresist stripping process;
s606, forming a pattern of the active layer 5;
s607, forming a first gate insulating layer 6;
and S608, forming a pattern of the grid 7.
When the OLED array substrate is manufactured, optionally, the method for manufacturing an array substrate provided in the embodiment of the present application further includes:
forming a pattern of a first electrode while forming a pattern of a gate electrode;
forming a second gate insulating layer over the pattern of the gate electrode and the first electrode;
forming a pattern of a second electrode over the second gate insulating layer;
forming an insulating planarization layer over the pattern of the second electrode;
forming a via hole penetrating through the first gate insulating layer, the second gate insulating layer and the insulating flat layer;
and forming a pattern of a metal electrode on the insulating flat layer, wherein the pattern of the metal electrode is connected with the drain electrode through the via hole.
Optionally, the forming of the insulating planarization layer over the pattern of the second electrode specifically includes:
and sequentially depositing two layers of the same insulating materials on the pattern of the second electrode and carrying out a patterning process to form an insulating layer comprising an interlayer insulating layer and a planarization layer.
According to the array substrate preparation method provided by the embodiment of the application, the interlayer insulating layer and the planarization layer are made of the same material, so that after the interlayer insulating layer and the planarization layer are deposited, the interlayer insulating layer and the planarization layer can be formed only by adopting a mask and an etching process, the array substrate preparation process is further simplified, the mask and the etching are further reduced, and the production cost is saved. Of course, the interlayer insulating layer and the planarization layer can be combined into the same film layer, so that the preparation flow of the array substrate is further simplified.
Next, taking the fabrication of the OLED array substrate as an example, the fabrication method of the array substrate provided in the embodiment of the present application, in step S608, forms the pattern of the first electrode 12 while forming the pattern of the gate electrode 7, and as shown in fig. 8 after step S608, further includes the following steps:
s609, forming a second gate insulating layer 13;
s610, forming a pattern of the second electrode 14;
s611, forming an interlayer insulating layer 15 and a planarization layer 16;
s612, forming a via hole 17 penetrating through the first gate insulating layer 6, the second gate insulating layer 13, the interlayer insulating layer 15 and the planarization layer 16;
s613, a pattern of the metal electrode 18 is formed on the planarization layer 16, and the pattern of the metal electrode 18 is connected to the drain electrode 3 through the via 17.
In summary, according to the array substrate, the manufacturing method thereof and the display panel provided in the embodiment of the present application, the light shielding layer is disposed between the active layer and the substrate and between the source electrode and the drain electrode, and the light shielding layer includes the same metal layer as the source electrode and the drain electrode, that is, the source electrode, the drain electrode and the light shielding layer are disposed on the same layer and include the same metal material, so that an additional light shielding layer material is not required to be deposited when the array substrate is manufactured, and a mask can be used to form the source electrode, the drain electrode and the light shielding layer, thereby simplifying the manufacturing process of the array substrate, reducing the number of times of using the mask, and reducing the. According to the OLED array substrate provided by the embodiment of the application, the interlayer insulating layer and the planarization layer can be made of the same material, so that after the interlayer insulating layer and the planarization layer are deposited, the interlayer insulating layer and the planarization layer can be formed only by adopting a mask and an etching process, the preparation process of the array substrate is further simplified, the mask and the etching are further reduced, and the production cost is saved. According to the array substrate preparation method provided by the embodiment of the application, when the photoresist pattern is processed by adopting an ashing process, the photoresist on the pattern of the shading metal layer is completely removed, and the pattern of the shading layer comprising metal oxide is obtained; and because the photoresist is processed by adopting the halftone mask process, the thickness of the photoresist pattern in the area where the light shielding layer needs to be formed is smaller than that of the photoresist pattern in the area where the source electrode and the drain electrode need to be formed, so that the photoresist pattern in the area where the source electrode and the drain electrode need to be formed is not completely removed in the ashing process of the photoresist pattern.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (3)
1. A preparation method of an array substrate is characterized by comprising the following steps:
forming a pattern of a source electrode, a light shielding layer and a drain electrode on a substrate;
forming a pattern of an active layer over the pattern of the source electrode, the light-shielding layer, and the drain electrode;
forming a first gate insulating layer over the pattern of the active layer;
forming a pattern of a gate electrode over the first gate insulating layer;
forming a pattern of a source electrode, a shading layer and a drain electrode on the substrate, and specifically comprising:
depositing a metal layer on the substrate;
coating photoresist on the metal layer;
processing the photoresist by adopting a halftone mask process, and forming a photoresist pattern in a region where a source electrode, a drain electrode and a light shielding layer are required to be formed, wherein the thickness of the photoresist pattern in the region where the light shielding layer is required to be formed is smaller than the thickness of the photoresist pattern in the region where the source electrode and the drain electrode are required to be formed;
etching the metal layer to form patterns of a source electrode, a shading metal layer and a drain electrode;
processing the photoresist pattern by adopting an ashing process, completely removing the photoresist pattern on the shading metal layer, and forming a metal oxide on the surface of the shading metal layer to obtain a pattern of a shading layer;
and stripping the residual photoresist above the source electrode and the drain electrode by adopting a photoresist stripping process.
2. The method of claim 1, further comprising:
forming a pattern of a first electrode while forming a pattern of a gate electrode;
forming a second gate insulating layer over the pattern of the gate electrode and the first electrode;
forming a pattern of a second electrode over the second gate insulating layer;
forming an insulating planarization layer over the pattern of the second electrode;
forming a via hole penetrating through the first gate insulating layer, the second gate insulating layer and the insulating flat layer;
and forming a pattern of a metal electrode on the insulating layer, wherein the pattern of the metal electrode is connected with the drain electrode through the via hole.
3. The method of claim 2, wherein forming an insulating planarization layer over the pattern of second electrodes comprises:
and sequentially depositing two layers of the same insulating materials on the pattern of the second electrode and carrying out a patterning process to form an insulating flat layer comprising an interlayer insulating layer and a flat layer.
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| CN109326614B (en) * | 2018-10-15 | 2022-07-05 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN109360493A (en) * | 2018-11-21 | 2019-02-19 | 厦门天马微电子有限公司 | A kind of backlight module, display panel and electronic equipment |
| CN109638079A (en) * | 2018-11-30 | 2019-04-16 | 武汉华星光电技术有限公司 | A kind of array substrate and display panel |
| CN111128874A (en) * | 2019-12-18 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and OLED touch display device |
| CN111308850A (en) * | 2020-02-21 | 2020-06-19 | 京东方科技集团股份有限公司 | Mask plate, TFT preparation method, TFT and array substrate |
| CN111312731B (en) * | 2020-02-28 | 2022-08-23 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN112490282B (en) * | 2020-12-03 | 2022-07-12 | Tcl华星光电技术有限公司 | Thin film transistor and preparation method thereof |
| CN113437090A (en) * | 2021-06-11 | 2021-09-24 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
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| CN1592520A (en) * | 2003-08-28 | 2005-03-09 | 三星Sdi株式会社 | Organic electroluminescent display |
| CN107123686A (en) * | 2017-04-27 | 2017-09-01 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device |
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| US7285459B2 (en) * | 2001-08-06 | 2007-10-23 | Samsung Sdi Co., Ltd. | Flat panel display with high capacitance and method of manufacturing the same |
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| CN1592520A (en) * | 2003-08-28 | 2005-03-09 | 三星Sdi株式会社 | Organic electroluminescent display |
| CN107123686A (en) * | 2017-04-27 | 2017-09-01 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device |
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