CN108198825A - A kind of array substrate and preparation method thereof, display panel - Google Patents
A kind of array substrate and preparation method thereof, display panel Download PDFInfo
- Publication number
- CN108198825A CN108198825A CN201810058977.7A CN201810058977A CN108198825A CN 108198825 A CN108198825 A CN 108198825A CN 201810058977 A CN201810058977 A CN 201810058977A CN 108198825 A CN108198825 A CN 108198825A
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode
- pattern
- light shield
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
This application discloses a kind of array substrate and preparation method thereof, display panels, to simplify array substrate preparation process flow, reduce light shield number, reduce production cost.A kind of array substrate provided by the embodiments of the present application, including：Substrate and the thin film transistor (TFT) for being arranged on the substrate；The thin film transistor (TFT) includes：The source electrode and drain electrode set gradually over the substrate, the active layer, the first gate insulation layer, the grid that are connected with the source electrode and the drain electrode, the thin film transistor (TFT) further include：The light shield layer for being arranged between the active layer and the substrate and being arranged between the source electrode and the drain electrode；The light shield layer includes the insulating layer of the metal layer identical with the source electrode and the drain material and the covering metal layer and the active layer adjacent surface.
Description
Technical field
This application involves display technology field more particularly to a kind of array substrate and preparation method thereof, display panels.
Background technology
Low-temperature polysilicon silicon technology (Low Temperature Poly-silicon, LTPS) array substrate is higher due to having
Mobility, be widely used in Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED) display, liquid crystal
(Liquid Crystal, LC) is shown.Lead to device creepage since polysilicon (P-Si) can be generated carrier by light irradiation
Increase, influences device performance, is shown especially for LC, as shown in Figure 1, LTPS includes the shading set gradually on substrate 1
Layer 4, insulating layer 9, source contact area 23, drain contact region 24 and active layer 5, gate insulation layer 6, grid 7, source electrode 2 and drain electrode 3,
Active layer is P-Si, i.e. the LTPS array substrates that LC is shown need additional setting light shield layer that backlight is avoided to irradiate P-Si, make
It is complicated to obtain the basic preparation process of LTPS arrays；OLED is shown, although backlight need not be set, prior art LTPS array bases
Plate is simultaneously not provided with light shield layer, but transparent OLED is shown, light can still be irradiated to P-Si, influences device performance, increases shading
Layer will increase array substrate preparation process flow, and due to needing to light shield layer layer pattern, it is also necessary to additionally increase light
Cover (mask) number.To sum up, prior art setting avoids the technological process of the light shield layer of light irradiation P-Si complicated, mask number
It is more.
Invention content
The embodiment of the present application provides a kind of array substrate and preparation method thereof, display panel, to simplify array substrate
Preparation process flow reduces by mask number, reduces production cost.
A kind of array substrate provided by the embodiments of the present application, the array substrate include：Substrate and it is arranged on the substrate
On thin film transistor (TFT)；The thin film transistor (TFT) includes：The source electrode and drain electrode set gradually over the substrate and the source
Pole and active layer, the first gate insulation layer, the grid of the drain electrode connection, the thin film transistor (TFT) further include：Have described in being arranged on
Between active layer and the substrate and the light shield layer that is arranged between the source electrode and the drain electrode；The light shield layer includes and institute
State the insulation of the source electrode metal layer identical with the drain material and the covering metal layer and the active layer adjacent surface
Layer.
Array substrate provided by the embodiments of the present application, due to light shield layer is arranged between the active layer and the substrate,
And it is arranged between the source electrode and the drain electrode, and light shield layer includes the gold identical with the source electrode and the drain material
Belong to layer, i.e., described source electrode, the drain electrode and the light shield layer same layer are set and including identical metal material, in this way, making
Without additional deposition shading layer material during standby array substrate, and can also source electrode, drain electrode, shading be formed using a mask
Layer so as to simplify array substrate preparation process flow, reduces light shield access times, reduces production cost.
Optionally, the insulating layer is the metal oxide of the metal layer.
Optionally, there are gaps between the light shield layer and the source electrode, exist between the light shield layer and the drain electrode
Gap；
The active layer is filled in the gap.
Optionally, the array substrate further includes：
With the first electrode of grid same layer setting, set gradually on the first grid and the first electrode
The second gate insulation layer, second electrode, insulation flatness layer and metal electrode；
The first electrode and the second electrode form capacitance structure；
The metal electrode by run through first gate insulation layer, the second gate insulation layer and insulate flatness layer via with
The drain electrode connection.
Optionally, the insulation flatness layer includes interlayer insulating film and the planarization on the interlayer insulating film
The material identical of layer, the planarization layer and the interlayer insulating film.
Array substrate provided by the embodiments of the present application, interlayer insulating film and planarization layer can be identical material, so as to heavy
After product interlayer insulating film and planarization layer material, interlayer insulating film peace can be formed only with a step mask and etching technics
Smoothization layer so as to be further simplified array substrate preparation process, is further reduced mask and etching, saves production cost.
A kind of display panel provided by the embodiments of the present application, including array substrate provided by the embodiments of the present application.
Array substrate preparation method provided by the embodiments of the present application, which is characterized in that this method includes：
Source electrode, light shield layer and the pattern of drain electrode are formed over the substrate；
The pattern of active layer is formed on the source electrode, light shield layer and the pattern of drain electrode；
The first gate insulation layer is formed on the pattern of the active layer；
The pattern of grid is formed on first gate insulation layer.
Optionally, source electrode, light shield layer and the pattern of drain electrode are formed over the substrate, are specifically included：
Deposited metal layer over the substrate；
The coating photoresist on the metal layer；
Using photoresist described in intermediate tone mask process, need to be formed source electrode, drain electrode, light shield layer region formed
Photoetching agent pattern, wherein need to form the thickness of the photoetching agent pattern in the region of light shield layer, less than need to be formed the region of source electrode,
The thickness of the photoetching agent pattern in the region of drain electrode；
It etches the metal layer and forms source electrode, shading metal layer and the pattern of drain electrode；
The photoetching agent pattern is handled using cineration technics, the photoetching agent pattern on the shading metal layer is gone completely
It removes, forms metal oxide on the surface of the shading metal layer, obtain the pattern of light shield layer；
Using photoresist stripping process by the remaining photoresist lift off on the source electrode and the drain electrode.
Array substrate preparation method provided by the embodiments of the present application is handled photoetching agent pattern when using cineration technics
When, utilize oxygen gas plasma, so as to which the photoetching agent pattern on the shading metal layer be removed completely, oxygen gas plasma
It reacts with shading metal layer, forms the pattern for the light shield layer for including metal layer and metal oxide；Also, due to using half
Tone masking process handles photoresist so that the thickness for the photoetching agent pattern to form the region of light shield layer is needed, which to be less than, to be needed to be formed
Source electrode, drain electrode region photoetching agent pattern thickness, in this way, after etching sheet metal, grey chemical industry is carried out to photoetching agent pattern
In skill processing procedure, by the removal completely of the photoetching agent pattern on the pattern of the shading metal layer and metal oxide is formed,
And source electrode, the photoetching agent pattern in the region to drain do not remove completely, so as to form the shading for including metal oxide
Source electrode, drain pattern is avoided to be aoxidized while layer, i.e., array substrate preparation method provided by the embodiments of the present application can be only
In the case of depositing one layer of metal layer and not destroying source electrode and drain electrode, only source electrode, drain electrode, shading can be formed with a mask
The pattern of layer can simplify array substrate preparation process flow compared with prior art, reduce light shield access times, reduce production
Cost.
Optionally, this method further includes：
While the pattern for forming grid, the pattern of first electrode is formed；
The second gate insulation layer is formed on the grid and the pattern of first electrode；
The pattern of second electrode is formed on second gate insulation layer；
Insulation flatness layer is formed on the pattern of the second electrode；
Form the via through first gate insulation layer, the second gate insulation layer and the insulation flatness layer；
The pattern of metal electrode is formed on the insulation flatness layer, the pattern of the metal electrode passes through the via
It is connected with the drain electrode.
Optionally, insulation flatness layer is formed on the pattern of the second electrode to specifically include：
Two layers of identical insulating materials is sequentially depositing on the pattern of the second electrode and carries out patterning process, shape
Into the insulating layer for including interlayer insulating film and planarization layer.
Description of the drawings
In order to illustrate more clearly of the technical solution in the embodiment of the present application, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present application, for this
For the those of ordinary skill in field, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is the LTPS array base-plate structure schematic diagrames that the prior art includes light shield layer；
Fig. 2 is a kind of array base-plate structure schematic diagram provided by the embodiments of the present application；
Fig. 3 is another array base-plate structure schematic diagram provided by the embodiments of the present application；
Fig. 4 is another array base-plate structure schematic diagram provided by the embodiments of the present application；
Fig. 5 is another array base-plate structure schematic diagram provided by the embodiments of the present application；
Fig. 6 is a kind of array substrate preparation method schematic diagram provided by the embodiments of the present application；
Fig. 7 is another array substrate preparation method schematic diagram provided by the embodiments of the present application；
Fig. 8 is another array substrate preparation method schematic diagram provided by the embodiments of the present application.
Specific embodiment
The embodiment of the present application provides a kind of array substrate and preparation method thereof, display panel, to simplify array substrate
Preparation process flow reduces light shield number, reduces production cost.
Array substrate provided by the embodiments of the present application, as shown in Fig. 2, the array substrate includes：Substrate 1 and it is arranged on institute
State the thin film transistor (TFT) on substrate 1；The thin film transistor (TFT) includes：The source electrode 2 set gradually on the substrate 1 and drain electrode
3rd, active layer 5, the first gate insulation layer 6, the grid 7 being connect with the source electrode 2 and the drain electrode 3, the thin film transistor (TFT) also wrap
It includes：The light shield layer for being arranged between the active layer 5 and the substrate 1 and being arranged on the source electrode 2 between the drain electrode 3
4；The light shield layer 4 include the metal layer 8 identical with the source electrode and the drain material and the covering metal layer 8 with
The insulating layer 9 of 5 adjacent surface of active layer.
Array substrate provided by the embodiments of the present application, since light shield layer is arranged between active layer and substrate and is arranged on
Between source electrode and drain electrode, and light shield layer includes the metal layer with source electrode and drain electrode material identical, i.e. source electrode, drain electrode and screening
Photosphere same layer sets and including identical metal material, in this way, when preparing array substrate without additional deposition shading layer material,
And can also source electrode, drain electrode, light shield layer be formed using a mask, so as to simplify array substrate preparation process flow, subtracted
Few light shield access times, reduce production cost.
Optionally, array substrate as shown in Figure 2 provided by the embodiments of the present application, insulating layer 9 are the metal oxygen of metal layer 8
Compound.The material of metal layer in the light shield layer material identical with source electrode, drain electrode use for example can be aluminium, tungsten, correspondingly, absolutely
Edge layer can be aluminium oxide, tungsten oxide.Certainly, metal layer, source electrode, drain electrode material can also select other that can be formed well
The metal material of insulation performance oxide.
Optionally, array substrate as shown in Figure 2 provided by the embodiments of the present application, is deposited between light shield layer 4 and the source electrode 2
In gap, there are gaps between light shield layer 4 and the drain electrode 3；
The active layer 5 is filled in the gap.
Optionally, the material of the active layer is polysilicon, i.e., array substrate provided by the embodiments of the present application is LTPS times
Row substrate.
Optionally, as shown in figure 3, array substrate provided by the embodiments of the present application, the substrate 1 include underlay substrate 11 with
And the buffer layer 10 on the underlay substrate 11.As shown in figure 3, there are gap between light shield layer and source electrode and drain electrode,
After setting active layer, there are active layer materials in gap, and setting buffer layer can be direct with underlay substrate to avoid active layer material
Contact, so as to avoid ingredient, the destruction active layer in underlay substrate.
Array substrate provided by the embodiments of the present application can be applied to liquid crystal display, can also be shown applied to OLED.
When array substrate provided by the embodiments of the present application, which is applied to OLED, to be shown, optionally, as shown in figure 4, the application
The array substrate that embodiment provides includes：Underlay substrate 11, the buffer layer 10 set gradually on underlay substrate 11, same layer
The source electrode 2 of setting, drain electrode 3 and light shield layer 4, active layer 5, the first gate insulation layer (gate insulator, GI) 6, grid 7 and the
One electrode 12, the second gate insulation layer 13, second electrode 14, insulation flatness layer 22, metal electrode 18, wherein, insulate flatness layer 22
Including interlayer insulating film (Inter Layer Dielectric, ILD) 15 and planarization layer (Planarization, PLN) 16,
First electrode 12 and second electrode 16 form capacitance structure, and metal electrode 18 is by running through the first gate insulation layer 6, the second gate insulation
The via of layer 13 and the flatness layer 22 that insulate is connect with drain electrode 3.
Wherein, identical material may be used in interlayer insulating film 15 and planarization layer 16 in Fig. 4, so as to deposit layer insulation
After layer and planarization layer material, interlayer insulating film and planarization layer can be formed only with a step mask and etching technics, from
And array substrate preparation process is further simplified, mask and etching are further reduced, saves production cost.
Certainly, the array substrate provided by the embodiments of the present application shown applied to OLED can also be as shown in figure 5, by interlayer
Insulating layer 15 and planarization layer 16 merge into same film layer, so as to be further simplified array substrate preparation process.
When interlayer insulating film and planarization layer use identical material, the material of interlayer insulating film and planarization layer is for example
Can be organosilicon (SOG).Metal electrode 18 in Fig. 4,5 for example can be anode.
A kind of display panel provided by the embodiments of the present application, including above-mentioned array substrate provided by the embodiments of the present application.
Corresponding with array substrate provided by the embodiments of the present application, the embodiment of the present application additionally provides a kind of array substrate system
Preparation Method, as shown in fig. 6, this method includes：
S501, source electrode, light shield layer and the pattern of drain electrode are formed over the substrate；
S502, the pattern that active layer is formed on the source electrode, light shield layer and the pattern of drain electrode；
S503, the first gate insulation layer is formed on the pattern of the active layer；
S504, the pattern that grid is formed on first gate insulation layer.
Array substrate preparation method provided by the embodiments of the present application, source electrode, drain and light shield layer same layer setting and wrap
Include identical metal material, without additional deposition shading layer material, and can also using a mask come formed source electrode,
Drain electrode, light shield layer so as to simplify thin film transistor (TFT) preparation process flow, reduce light shield access times, reduce production cost.
Optionally, step S501 forms source electrode, light shield layer and the pattern of drain electrode and specifically includes over the substrate：
Deposited metal layer over the substrate；
The coating photoresist on the metal layer；
Using photoresist described in intermediate tone mask process, need to be formed source electrode, drain electrode, light shield layer region formed
Photoetching agent pattern, wherein need to form the thickness of the photoetching agent pattern in the region of light shield layer, less than need to be formed the region of source electrode,
The thickness of the photoetching agent pattern in the region of drain electrode；
It etches the metal layer and forms source electrode, shading metal layer and the pattern of drain electrode；
The photoetching agent pattern is handled using cineration technics, the photoetching agent pattern on the shading metal layer is gone completely
It removes, forms metal oxide on the surface of the shading metal layer, obtain the pattern of light shield layer；
Using photoresist stripping process by the remaining photoresist lift off on the source electrode and the drain electrode.
Array substrate preparation method provided by the embodiments of the present application is handled photoetching agent pattern when using cineration technics
When, such as oxygen gas plasma can be utilized, so as to which the photoetching agent pattern on the pattern of the shading metal layer be gone completely
It removes, oxygen gas plasma reacts with shading metal layer, forms the pattern for the light shield layer for including metal layer and metal oxide.
Also, due to using photoresist described in intermediate tone mask process so that need to form the photoresist figure in the region of light shield layer
The thickness of case be less than need to be formed source electrode, drain electrode region photoetching agent pattern thickness, such as need to be formed source electrode, drain electrode
The thickness of the photoetching agent pattern in region is 5 microns, and it is 2 microns to need to form the thickness of the photoetching agent pattern in the region of light shield layer,
In this way, photoetching agent pattern is carried out in cineration technics processing procedure, the photoetching agent pattern on the pattern of shading metal layer is complete
Full removal and formation metal oxide, and source electrode, the photoetching agent pattern in the region to drain do not remove completely, so as in shape
Source electrode, drain pattern is avoided to be aoxidized while into light shield layer including metal oxide, i.e., battle array provided by the embodiments of the present application
Row base plate preparation method, can be in the case where only depositing one layer of metal layer and not destroying source electrode and drain electrode, only with a mask
The pattern of source electrode, drain electrode, light shield layer can be formed, array substrate preparation process flow can be simplified compared with prior art,
Light shield access times are reduced, reduce production cost.
By substrate include underlay substrate and buffer layer, using photoresist layer described in intermediate tone mask process for, it is right
Array substrate preparation method provided by the embodiments of the present application is illustrated, as shown in fig. 7, to provided by the embodiments of the present application
Array substrate preparation method includes the following steps：
S601, buffer layer 10 is formed on underlay substrate 11, the deposited metal material 19 on buffer layer 10 forms metal
Layer；
S602, coating photoresist 20, using intermediate tone mask process photoresist 20, need to be formed source electrode, drain electrode,
The region of light shield layer forms photoetching agent pattern, wherein needing to form the thickness of the photoetching agent pattern in the region of light shield layer, less than need
Formed source electrode region, drain electrode region photoetching agent pattern thickness；
S603, etching sheet metal form the pattern of source electrode 2, drain electrode 3, shading metal layer 21；
S604, the photoresist 20 is handled using cineration technics, by the photoetching on the pattern of the shading metal layer 21
Glue removes completely, forms metal oxide 9 on the surface of shading metal layer 21, obtains the pattern of light shield layer 4；
S605, the remaining photoresist layer on the source electrode 2 and drain electrode 3 is removed using photoresist stripping process；
S606, the pattern for forming active layer 5；
S607, the first gate insulation layer 6 is formed；
S608, the pattern for forming grid 7.
When preparing OLED array, optionally, array substrate preparation method provided by the embodiments of the present application further includes：
While the pattern for forming grid, the pattern of first electrode is formed；
The second gate insulation layer is formed on the grid and the pattern of first electrode；
The pattern of second electrode is formed on second gate insulation layer；
Insulation flatness layer is formed on the pattern of the second electrode；
Form the via through first gate insulation layer, the second gate insulation layer and the insulation flatness layer；
The pattern of metal electrode is formed on the insulation flatness layer, the pattern of the metal electrode passes through the via
It is connected with the drain electrode.
Optionally, insulation flatness layer is formed on the pattern of the second electrode to specifically include：
Two layers of identical insulating materials is sequentially depositing on the pattern of the second electrode and carries out patterning process, shape
Into the insulating layer for including interlayer insulating film and planarization layer.
Array substrate preparation method provided by the embodiments of the present application, interlayer insulating film and planarization layer use identical material
After depositing interlayer insulating film and planarization layer material, interlayer can be formed only with a step mask and etching technics for material
Insulating layer and planarization layer so as to be further simplified array substrate preparation process, are further reduced mask and etching, save production
Cost.Certainly, also interlayer insulating film and planarization layer can be merged into same film layer, is prepared so as to be further simplified array substrate
Flow.
In the following, for preparing OLED array, array substrate preparation method provided by the embodiments of the present application, step
In S608, the pattern of first electrode 12 is formed while 7 pattern of grid is formed, as shown in figure 8, also wrapping after step S608
Include following steps：
S609, the second gate insulation layer 13 is formed；
S610, the pattern for forming second electrode 14；
S611, interlayer insulating film 15 and planarization layer 16 are formed；
S612, the mistake for running through the first gate insulation layer 6,13 interlayer insulating film 15 of the second gate insulation layer and planarization layer 16 is formed
Hole 17；
S613, the pattern that metal electrode 18 is formed on planarization layer 16, the pattern of metal electrode 18 pass through via 17
It is connect with drain electrode 3.
In conclusion array substrate provided by the embodiments of the present application and preparation method thereof, display panel, since light shield layer is set
It puts between active layer and substrate and is arranged between source electrode and drain electrode, and light shield layer includes and source electrode and drain electrode material phase
Same metal layer, i.e. source electrode, drain electrode and light shield layer same layer set and including identical metal materials, in this way, preparing array
Without additional deposition shading layer material during substrate, and can also source electrode, drain electrode, light shield layer be formed using a mask, from
And simplify array substrate preparation process flow, light shield access times are reduced, reduce production cost.It is provided by the embodiments of the present application
Identical material may be used in OLED array, interlayer insulating film and planarization layer, so as to deposit interlayer insulating film and flat
After changing layer material, interlayer insulating film and planarization layer can be formed only with a step mask and etching technics, so as to further
Simplify array substrate preparation process, be further reduced mask and etching, save production cost.Array provided by the embodiments of the present application
Base plate preparation method, when being handled using cineration technics photoetching agent pattern, on the pattern of the shading metal layer
Photoresist remove completely, obtain the pattern for the light shield layer for including metal oxide；Also, due to using intermediate tone mask technique
Handle the photoresist so that the thickness for the photoetching agent pattern to form the region of light shield layer is needed, which to be less than, to be needed to form source electrode, leakage
The thickness of the photoetching agent pattern in the region of pole, in this way, being carried out in cineration technics processing procedure to photoetching agent pattern, source electrode, drain electrode
The photoetching agent pattern in region do not remove completely, i.e., array substrate preparation method provided by the embodiments of the present application can be only
In the case of depositing one layer of metal layer and not destroying source electrode and drain electrode, only source electrode, drain electrode, shading can be formed with a mask
Layer can simplify array substrate preparation process flow compared with prior art, reduce light shield access times, reduce production cost.
Obviously, those skilled in the art can carry out the application essence of the various modification and variations without departing from the application
God and range.In this way, if these modifications and variations of the application belong to the range of the application claim and its equivalent technologies
Within, then the application is also intended to include these modifications and variations.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate includes：Substrate and the film for being arranged on the substrate
Transistor；The thin film transistor (TFT) includes：The source electrode and drain electrode set gradually over the substrate and the source electrode and the leakage
Active layer, the first gate insulation layer, the grid of pole connection, the thin film transistor (TFT) further include：It is arranged on the active layer and described
Between substrate and the light shield layer that is arranged between the source electrode and the drain electrode；The light shield layer includes and the source electrode and institute
State the insulating layer of the identical metal layer of drain material and the covering metal layer and the active layer adjacent surface.
2. array substrate according to claim 1, which is characterized in that the insulating layer is aoxidized for the metal of the metal layer
Object.
3. array substrate according to claim 1, which is characterized in that between existing between the light shield layer and the source electrode
Gap, there are gaps between the light shield layer and the drain electrode；
The active layer is filled in the gap.
4. array substrate according to claim 1, which is characterized in that the array substrate further includes：
With the first electrode of grid same layer setting, the set gradually on the first grid and the first electrode
Two gate insulation layers, second electrode, insulation flatness layer and metal electrode；
The first electrode and the second electrode form capacitance structure；
The metal electrode by run through first gate insulation layer, the second gate insulation layer and insulate flatness layer via with it is described
Drain electrode connection.
5. array substrate according to claim 4, which is characterized in that the insulation flatness layer includes interlayer insulating film and position
The material identical of planarization layer on the interlayer insulating film, the planarization layer and the interlayer insulating film.
6. a kind of display panel, which is characterized in that including Claims 1 to 5 any one of them array substrate.
7. a kind of Claims 1 to 5 any one of them array substrate preparation method, which is characterized in that this method includes：
Source electrode, light shield layer and the pattern of drain electrode are formed over the substrate；
The pattern of active layer is formed on the source electrode, light shield layer and the pattern of drain electrode；
The first gate insulation layer is formed on the pattern of the active layer；
The pattern of grid is formed on first gate insulation layer.
8. the method according to the description of claim 7 is characterized in that source electrode, light shield layer and drain electrode are formed over the substrate
Pattern specifically includes：
Deposited metal layer over the substrate；
The coating photoresist on the metal layer；
Using photoresist described in intermediate tone mask process, needing to form the region formation photoetching of source electrode, drain electrode, light shield layer
Wherein needing to form the thickness of the photoetching agent pattern in the region of light shield layer, the region of source electrode, drain electrode are formed less than needing for glue pattern
Region photoetching agent pattern thickness；
It etches the metal layer and forms source electrode, shading metal layer and the pattern of drain electrode；
The photoetching agent pattern is handled using cineration technics, the photoetching agent pattern on the shading metal layer is removed completely,
Metal oxide is formed on the surface of the shading metal layer, obtains the pattern of light shield layer；
Using photoresist stripping process by the remaining photoresist lift off on the source electrode and the drain electrode.
9. the method according to the description of claim 7 is characterized in that this method further includes：
While the pattern for forming grid, the pattern of first electrode is formed；
The second gate insulation layer is formed on the grid and the pattern of first electrode；
The pattern of second electrode is formed on second gate insulation layer；
Insulation flatness layer is formed on the pattern of the second electrode；
Form the via through first gate insulation layer, the second gate insulation layer and the insulation flatness layer；
The pattern of metal electrode is formed on the insulating layer, the pattern of the metal electrode passes through the via and the leakage
Pole connects.
10. it according to the method described in claim 9, is put down it is characterized in that, forming insulation on the pattern of the second electrode
Smooth layer specifically includes：
Two layers of identical insulating materials is sequentially depositing on the pattern of the second electrode and carries out patterning process, forms packet
Include the insulation flatness layer of interlayer insulating film and planarization layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810058977.7A CN108198825B (en) | 2018-01-22 | 2018-01-22 | Array substrate, preparation method thereof and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810058977.7A CN108198825B (en) | 2018-01-22 | 2018-01-22 | Array substrate, preparation method thereof and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108198825A true CN108198825A (en) | 2018-06-22 |
| CN108198825B CN108198825B (en) | 2021-01-15 |
Family
ID=62590097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810058977.7A Active CN108198825B (en) | 2018-01-22 | 2018-01-22 | Array substrate, preparation method thereof and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108198825B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109326614A (en) * | 2018-10-15 | 2019-02-12 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method, display device |
| CN109360493A (en) * | 2018-11-21 | 2019-02-19 | 厦门天马微电子有限公司 | A kind of backlight module, display panel and electronic equipment |
| CN109638079A (en) * | 2018-11-30 | 2019-04-16 | 武汉华星光电技术有限公司 | A kind of array substrate and display panel |
| CN111128874A (en) * | 2019-12-18 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and OLED touch display device |
| CN111308850A (en) * | 2020-02-21 | 2020-06-19 | 京东方科技集团股份有限公司 | Mask plate, TFT preparation method, TFT and array substrate |
| CN111312731A (en) * | 2020-02-28 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN112490282A (en) * | 2020-12-03 | 2021-03-12 | Tcl华星光电技术有限公司 | Thin film transistor and preparation method thereof |
| WO2022257186A1 (en) * | 2021-06-11 | 2022-12-15 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method therefor, and display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592520A (en) * | 2003-08-28 | 2005-03-09 | 三星Sdi株式会社 | Organic electroluminescent display |
| US20050189578A1 (en) * | 2001-08-06 | 2005-09-01 | Samsung Sdi Co., Ltd. | Flat panel display with high capacitance and method of manufacturing the same |
| CN107123686A (en) * | 2017-04-27 | 2017-09-01 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device |
-
2018
- 2018-01-22 CN CN201810058977.7A patent/CN108198825B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050189578A1 (en) * | 2001-08-06 | 2005-09-01 | Samsung Sdi Co., Ltd. | Flat panel display with high capacitance and method of manufacturing the same |
| CN1592520A (en) * | 2003-08-28 | 2005-03-09 | 三星Sdi株式会社 | Organic electroluminescent display |
| CN107123686A (en) * | 2017-04-27 | 2017-09-01 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109326614A (en) * | 2018-10-15 | 2019-02-12 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method, display device |
| US11075228B2 (en) | 2018-10-15 | 2021-07-27 | Boe Technology Group Co., Ltd. | Display substrate, method for manufacturing the same, and display device |
| CN109360493A (en) * | 2018-11-21 | 2019-02-19 | 厦门天马微电子有限公司 | A kind of backlight module, display panel and electronic equipment |
| CN109638079A (en) * | 2018-11-30 | 2019-04-16 | 武汉华星光电技术有限公司 | A kind of array substrate and display panel |
| CN111128874A (en) * | 2019-12-18 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and OLED touch display device |
| CN111308850A (en) * | 2020-02-21 | 2020-06-19 | 京东方科技集团股份有限公司 | Mask plate, TFT preparation method, TFT and array substrate |
| CN111312731A (en) * | 2020-02-28 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN111312731B (en) * | 2020-02-28 | 2022-08-23 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN112490282A (en) * | 2020-12-03 | 2021-03-12 | Tcl华星光电技术有限公司 | Thin film transistor and preparation method thereof |
| CN112490282B (en) * | 2020-12-03 | 2022-07-12 | Tcl华星光电技术有限公司 | Thin film transistor and preparation method thereof |
| WO2022257186A1 (en) * | 2021-06-11 | 2022-12-15 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method therefor, and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108198825B (en) | 2021-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108198825A (en) | A kind of array substrate and preparation method thereof, display panel | |
| CN107017287B (en) | Thin film transistor, display device, and method for manufacturing thin film transistor | |
| CN107452808A (en) | Thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| CN108493195B (en) | Manufacturing method of flexible TFT backboard and flexible TFT backboard | |
| CN109671726A (en) | Array substrate and its manufacturing method, display panel, display device | |
| CN104733492B (en) | A kind of organic light-emitting display device and preparation method thereof | |
| CN104851789B (en) | Thin film transistor (TFT) and production method, array base palte and production method and display device | |
| KR20110134687A (en) | Display device and method for manufacturing the same | |
| CN108417580B (en) | Array substrate, manufacturing method thereof and display panel | |
| CN102830560A (en) | Array substrate and method for manufacturing same | |
| WO2018209761A1 (en) | Array substrate, method for manufacturing same, and liquid crystal display panel | |
| WO2017031940A1 (en) | Array substrate, fabrication method therefor, and display device | |
| CN107170748A (en) | A kind of array base palte, display panel and display device | |
| CN110148601A (en) | A kind of array substrate, its production method and display device | |
| CN106898617A (en) | Substrate and preparation method thereof, display panel and display device | |
| CN108493216B (en) | TFT array substrate, display device and preparation method of TFT array substrate | |
| US11309428B2 (en) | Transistor and manufacturing method thereof, display substrate and display device | |
| US10096788B2 (en) | Reducing undesirable capacitive coupling in transistor devices | |
| JP2017535961A (en) | Thin film transistor substrate manufacturing method and manufacturing apparatus | |
| CN109728003A (en) | The manufacturing method of display base plate, display device and display base plate | |
| CN102723365B (en) | TFT (Thin Film Transistor), manufacturing method thereof, array substrate and display device | |
| KR100470260B1 (en) | Method and apparatus for manufacturing active matrix device including top gate type tft | |
| CN105826329B (en) | A kind of production method of array substrate, array substrate and liquid crystal display panel | |
| CN104701264B (en) | A kind of organic LED display panel and preparation method thereof, display device | |
| JP2007138301A (en) | Thin film forming apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |