CN107123686A - A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device - Google Patents

A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device Download PDF

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Publication number
CN107123686A
CN107123686A CN201710287331.1A CN201710287331A CN107123686A CN 107123686 A CN107123686 A CN 107123686A CN 201710287331 A CN201710287331 A CN 201710287331A CN 107123686 A CN107123686 A CN 107123686A
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grid
source electrode
breach
film transistor
tft
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CN107123686B (en
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周宏儒
赵永亮
毕鑫
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention provides a kind of thin film transistor (TFT) and preparation method thereof, display panel, display device, including：The first grid, source electrode and drain electrode with layer are on substrate, the first breach is formed between the source electrode and the first grid, the second breach is formed between the drain electrode and the first grid；It is covered in the gate insulator on the first grid；It is covered in the source electrode, the gate insulator, in the drain electrode and is filled in the semiconductor layer of first breach and second breach, so as to simplify the technological process of double-gate film transistor, and then improves the yield of product.

Description

A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device
Technical field
The present invention relates to display technology field, more particularly to a kind of thin film transistor (TFT) and preparation method thereof, display panel, Display device.
Background technology
TFT-LCD (Thin Film Transistor-Liquid Crystal Display) is that current main flow is shown Product, in recent years major panel manufacturer all constantly expanding the scale of production, the market demand is increasing, improves production efficiency and life It is the key dominated the market to produce high-quality liquid crystal display product.
Making thin film transistor (TFT) in the prior art needs to carry out grid single Patternized technique processing, Ran Hou Once single patterned process is carried out to source electrode and drain electrode, the processing of gate insulator is being carried out, in above-mentioned processing procedure, Need individually to handle grid, source electrode and drain electrode respectively, the technological process for making thin film transistor (TFT) is complex, and grid Pole easily produces interlayer segment difference with source electrode and drain electrode, adds open circuit risk.
The content of the invention
It is how simple to solve the invention provides a kind of thin film transistor (TFT) and preparation method thereof, display panel, display device Change the technological process of double-gate film transistor, and then the problem of the yield of raising product.
In order to solve the above problems, the invention discloses a kind of thin film transistor (TFT), including：
The first grid, source electrode and drain electrode with layer, shape between the source electrode and the first grid are on substrate Into there is the first breach, the second breach is formed between the drain electrode and the first grid；
It is covered in the gate insulator on the first grid；
It is covered in the source electrode, the gate insulator, in the drain electrode and is filled in first breach and described The semiconductor layer of second breach.
Optionally, the source electrode includes the first source electrode and the second source electrode, between first source electrode and the first grid, And second be respectively formed with first breach between source electrode and the first grid.
Optionally, first breach or second notch geometry include one of following shape：For arc, square, W Shape.
Optionally, the thin film transistor (TFT) also includes：
Passivation layer on the semiconductor layer；
Second grid on the passivation layer, the second grid is located above the first grid；Described first Grid and the second grid are connected by gate connection line, and first source electrode and second source electrode pass through source connection lines Connection.
In order to solve the above problems, the invention also discloses a kind of display panel, including any one of claim 1-4 institute The thin film transistor (TFT) stated.
In order to solve the above problems, the invention also discloses a kind of display device, including the display surface described in claim 5 Plate.
In order to solve the above problems, the invention also discloses a kind of preparation method of thin film transistor (TFT), including：
First grid, source electrode and drain electrode are formed by a patterned process on substrate；The source electrode and described first The first breach is formed between grid, the second breach is formed between the drain electrode and the first grid；
Gate insulator is formed on the first grid；
Semiconductor layer is formed, wherein, semiconductor layer is formed in the first grid, the source electrode and the drain electrode, and Semi-conducting material is filled with first breach and second breach.
Optionally, first breach or second notch geometry include one of following shape：For arc, square, W Shape.
Optionally, the source electrode includes the first source electrode and the second source electrode, between first source electrode and the first grid, And second be respectively formed with first breach between source electrode and the first grid.
Optionally, methods described also includes：
Passivation layer is formed on the semiconductor layer；
Form grid via and source electrode via；
Form metal conducting layer；
The metal conducting layer is etched to form second grid, the second grid is located at the top of the first grid, Wherein, the first grid and the second grid are connected by the gate connection line of the grid via, first source electrode Connected with second source electrode by the source connection lines of the source electrode via.
Compared with prior art, the present invention includes advantages below：
First, the present invention is formed first grid, source electrode and drain electrode in same layer by a Patternized technique, is simplified Technological process, while first grid, source electrode and drain electrode are formed in same layer can also avoid interlayer segment difference, reduces open circuit wind Danger, improves product yield.
Secondly, first grid and second grid can act as the effect of switch, and sound can be greatly improved in the double-grid structure Between seasonable.
Certainly, any product for implementing the present invention is not necessarily required to while reaching all the above advantage.
Brief description of the drawings
Fig. 1 is a kind of structural representation of thin film transistor (TFT) described in the embodiment of the present invention one；
Fig. 2 is the schematic top plan view that the present invention forms pixel electrode；
Fig. 3 is that the present invention forms first grid, source electrode and the schematic top plan view of drain electrode；
Fig. 4 is the schematic top plan view that the present invention forms semiconductor layer；
Fig. 5 is a kind of flow chart of the preparation method of thin film transistor (TFT) described in the embodiment of the present invention four；
Fig. 6 is the schematic top plan view that the present invention forms gate insulation layer；
Fig. 7 is the schematic top plan view that the present invention forms grid via and source electrode via over the passivation layer；
Fig. 7-1 is the diagrammatic cross-section of grid via in Fig. 7 of the present invention；
Fig. 8 is the schematic top plan view that the present invention forms double-gate film transistor；
Fig. 8-1 is profile of the thin film transistor (TFT) of the invention formed in B-B directions；
Fig. 8-2 is profile of the thin film transistor (TFT) of the invention formed in A-A directions.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real Applying mode, the present invention is further detailed explanation.
Embodiment one
Reference picture 1, it illustrates a kind of structural representation of thin film transistor (TFT) described in the embodiment of the present invention one.
The thin film transistor (TFT) includes：It is on substrate with the first grid 101 of layer, source electrode 102 and drain electrode 103, institute State and the first breach is formed between source electrode 102 and the first grid 101, be formed between the drain electrode and the first grid Second breach.
It is covered in the gate insulator 104 on the first grid.
Be covered in the source electrode 102, the gate insulator 104, it is described drain electrode 103 on and be filled in described first lack The semiconductor layer 105 of mouth and second breach.
In the structure, substrate can use principal component to be formed for the transparent glass material of silica, form the material of substrate Material is not limited to transparent glass material, or transparent plastic material, the substrate is preferably glass substrate.
It is on substrate and uses once patterning to form first grid 101, source electrode 102 and drain electrode 103, the source with layer The first breach is formed between pole 102 and the first grid 101, is formed between the drain electrode 103 and the first grid 101 There is the second breach, to form first grid, source electrode, drain electrode, the first breach and the second breach by once patterning, simplify technique Flow.
In actual fabrication process, as shown in Fig. 2 being initially formed pixel electrode 106 on substrate, then on the pixel electrode First grid 101, source electrode 102 and drain electrode 103 are formed by once patterning, drain electrode 103 is realized with pixel electrode 106 and connects Connect, as shown in Figure 3.
Wherein, source electrode 102 as shown in Figure 3 includes the first source electrode 1021 and the second source electrode 1022, first source electrode It is respectively formed between 1021 and the first grid 101, and between the second source electrode 1022 and the first grid 101 described First breach 301, the second breach 302 is formed between the drain electrode 103 and the first grid 101.
First breach 301 or the shape of the second breach 302 include one of following shape：For arc, square, W shapes, circle Shape etc., the present invention is not specifically limited to this, it is preferred that the first breach or the second breach are arc.
First gate electrode 101, source electrode 102, drain electrode 103 are prepared using metal material, and it can be molybdenum (Mo), titanium (Ti), one or more heap stack combinations in aluminium (Al), copper (Cu), but be not restricted to this, or other metal materials Material.
It should be noted that as shown in figure 1, gate insulator 104 is covered on first grid 101, and source electrode 102 and leakage Gate insulator 104 need not be covered on pole 103.
After formation first grid 101, source electrode 102 and drain electrode 103, and the first breach 301 and the second breach 302, Semiconductor layer 105 is formed, as shown in Figure 4.
Deposited semiconductor layer 105, then carries out a patterned process on semiconductor layer 105 first, is formed and is located at source Semiconductor layer 105 on pole 102, gate insulator 104, drain electrode 103 and first breach 301, the second breach 302.
Semiconductor layer material can be metal-oxide semiconductor (MOS) or amorphous silicon semiconductor, but be not restricted to this, also may be used Think other metal materials.
Semiconductor is generally performed etching using wet method, and source electrode, drain electrode are also to use wet etching, therefore source electrode, drain electrode On all still retain semiconductor layer, prevent metal level to be etched.
Wherein, circular arc raceway groove, second source electrode 1022 and institute are formed between the first source electrode 1021 and the drain electrode 103 State and form composite channel between drain electrode 103, the present invention instead of traditional U-shaped raceway groove by circular arc raceway groove and composite channel, Due to the length of circular arc raceway groove can do it is larger, it is smaller that width can be done, therefore can effectively improve the operation of ion, excellent Change electrology characteristic, improve the response time.
The embodiment of the present invention, first, first grid, source electrode, drain electrode, the first breach and second is formed by once patterning Breach, can reduce grid, source electrode, drain electrode MASK technique number of times, and simplification of flowsheet saves production cost.Further, by Formed in grid, source electrode and drain electrode in same layer, interlayer segment difference can be avoided to produce, reduced open circuit risk, improve film crystal The yield of pipe.
Secondly, positioned at the first grid of same layer, drain electrode, double source (the first source electrode and the second source electrode), and answering of being formed Raceway groove is closed, same layer driving function can also be realized, the response time is improved.
Again, due to there is first grid separate between source-drain electrode, it is to avoid the short circuit generation of source-drain electrode, and first grid with There is gate insulator between source-drain electrode, the short circuit between first grid and source-drain electrode can be effectively prevent, and then improve product Yield.
Further, the thin film transistor (TFT) also includes：
Passivation layer 108 on the semiconductor layer 105.
Second grid 107 on the passivation layer 105, the second grid 107 is located at the first grid 101 Top, wherein, the first grid 101 and the second grid 107 are connected by gate connection line, first source electrode 1021 Connected with second source electrode 1022 by source connection lines 109.
Wherein, the material of passivation layer is in silicon oxide sio x, silicon nitride SiNx, silicon oxynitride SiON, aluminium oxide Al 2O3 One or more, but it is not restricted to this.
Formed on the passivation layer 108 after grid via and source electrode via, depositing metal conductive layer, metal conducting layer sinks Product is into grid via and source electrode via, so as to form gate connection line and source connection lines.Then metal conducting layer is entered again Row etching, you can form second grid 107, the second grid 107 is located at the top of first grid 101, and with first grid 101 simultaneously Connection, when first grid 101 adds driving voltage, first grid 101 and second grid 107 can play a part of switch, This double-gate structure can be improved the response time, and when any one grid fails in first grid or second grid, it is another Individual grid can ensure being normally added for voltage signal, effectively increase the yield of product.
Embodiment two
The invention also discloses the thin film transistor (TFT) in a kind of display panel, including embodiment one.
The thin film transistor (TFT) has all advantages of thin film transistor (TFT) in above-described embodiment one, will not be repeated here.
Embodiment three
The invention also discloses the display panel in a kind of display device, including embodiment two.
It should be noted that the display device in the present embodiment can be：Mobile phone, tablet personal computer, television set, notebook electricity Any product or part with display function such as brain, DPF, navigator.
The display device has all advantages of display base plate in above-described embodiment two, will not be repeated here.
Example IV
Reference picture 5, it illustrates a kind of flow chart of the preparation method of thin film transistor (TFT) described in the embodiment of the present invention four.
The preparation method of the thin film transistor (TFT) can be formed on substrate after pixel electrode, then scheme on the pixel electrode Caseization formation first grid, source electrode and drain electrode, make drain electrode be connected with pixel electrode realization, and the can also be directly formed on substrate One grid, source electrode and drain electrode, are not specifically limited to this present invention, after the present embodiment is with the formation pixel electrode on substrate, To be formed by once patterning exemplified by first grid, source electrode and drain electrode, the preparation method for introducing thin film transistor (TFT).
Step 501：Substrate is provided, deposits, pattern and etching layer of transparent pixel electrode 106 on the substrate.Such as Fig. 2 It is shown.
Step 502：First grid 101, source electrode 102 and drain electrode 103 are formed by a patterned process on substrate.
Specifically, being deposited on substrate, a patterned process and etching form first grid 101, the and of source electrode 102 Drain electrode 103；It is formed with the first breach 301 between the source electrode 102 and the first grid 101, the drain electrode 103 and described the The second breach 302 is formed between one grid 101.
Specifically, the source electrode 102 includes the first source electrode 1021 and the second source electrode 1022, first source electrode 1021 and institute State between first grid 101, and first breach is respectively formed between the second source electrode 1022 and the first grid 101 301, as shown in Figure 3.
Specifically, the source electrode 1022 of first grid 101 and second, and the formation of the source electrode 1021 of first grid 101 and first First breach 301 is to be symmetrical arranged or asymmetric setting, and second is formed between the drain electrode 103 and the first grid 101 Breach 302, second breach 302 can be located at the top of the first breach 301, or other positions, to this present invention not Make concrete restriction.
It should be noted that the first breach or second notch geometry include one of following shape：Arc, square, W Shape, U-shaped, but it is not restricted to this.
Step 503：Gate insulator 104 is formed on the first grid 101.
Specifically, using aumospheric pressure cvd, low-pressure chemical vapor deposition, plasma asistance body chemical vapor phase growing Or the method such as sputtering, deposition is such as silicon oxide sioX, silicon nitride SiNX, silicon oxynitride SiON, aluminium oxide Al2O3, hafnium oxide HfO2, oxygen Change zirconium ZrO2, titanium oxide TiO2, yittrium oxide Y2O3, lanthana La2O3, tantalum oxide Ta2O5Deng the single or multiple lift of oxide formation Gate insulator, and etched simultaneously using insulating barrier etch mask version, gate insulation layer 104 is formed, as shown in Figure 6.
Step 504：Form semiconductor layer 105.
Wherein, semiconductor layer 105, and institute are formed in the first grid 101, the source electrode 102 and the drain electrode 103 State and semi-conducting material is filled with the first breach 301 and second breach 302, as shown in Figure 4.
Step 505：Passivation layer 108 is formed on the semiconductor layer 105.
Deposit, pattern and etch on the semiconductor layer 105 and form passivation layer 108 (not marking in the figure 7), and Grid via (701,702) and source electrode via (703,704) are formed on passivation layer 108, as shown in Figure 7.
Passivation layer is patterned, etches to form grid via and source electrode via, in order to better illustrate in passivation layer Upper formation grid via, referring to Fig. 7-1, it illustrates the schematic cross-section of grid via dotted line position in Fig. 7.
Step 506：Metal conducting layer is formed, the metal conducting layer is etched to form second grid 107, the second gate Pole 107 is located at the top of the first grid 101.
Wherein, the first grid 101 and the second grid 107 are connected by the gate connection line of the grid via Connect, first source electrode and second source electrode are connected by the source connection lines of the source electrode via, as shown in Figure 8.
Referring to Fig. 8-1 it illustrates the thin film transistor (TFT) by above-mentioned steps formation in fig. 8 from the section view in B-B directions Figure.
Referring to Fig. 8-2 it illustrates the thin film transistor (TFT) by above-mentioned steps formation in fig. 8 from the section view in A-A directions Figure.
The embodiment of the present invention, is formed first grid, source electrode and drain electrode in same layer by a Patternized technique, is simplified Technological process, while first grid, source electrode and drain electrode are formed in same layer can also avoid interlayer segment difference, reduces open circuit wind Danger, improves product yield.
It should be noted that for foregoing embodiment of the method, in order to be briefly described, therefore it is all expressed as a series of Combination of actions, but those skilled in the art should know, the present invention is not limited by described sequence of movement, because according to According to the present invention, some steps can be carried out sequentially or simultaneously using other.Secondly, those skilled in the art should also know, Embodiment described in this description belongs to preferred embodiment, and involved action is not necessarily essential to the invention.
For said apparatus embodiment, because it is substantially similar to embodiment of the method, so description is fairly simple, Related part illustrates referring to the part of shown embodiment of the method.
Each embodiment in this specification is described by the way of progressive, what each embodiment was stressed be with Between the difference of other embodiment, each embodiment identical similar part mutually referring to.
It would have readily occurred to a person skilled in the art that be：Any combination application of each above-mentioned embodiment is all feasible, therefore Any combination between each above-mentioned embodiment is all embodiment of the present invention, but this specification exists as space is limited, This is not just detailed one by one.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality Body or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or deposited between operating In any this actual relation or order.Moreover, term " comprising ", "comprising", not only including those key elements, but also are wrapped Include other key elements being not expressly set out, or also include for this process, method, article or equipment intrinsic want Element.In the absence of more restrictions, the key element limited by sentence " including ... ", it is not excluded that including the key element Also there is other identical element in process, method, article or equipment.
Moreover, "and/or" above represent both to have contained herein " and " relation, also contains the relation of "or", its In：If option A and option b be " and " relation, then it represents that option A and option b can be included in certain embodiment simultaneously；If Option A and the relation that option b is "or", then it represents that can individually include option A in certain embodiment, or individually include option b.
, but those skilled in the art once know basic creation although preferred embodiments of the present invention have been described Property concept, then can make other change and modification to these embodiments.So, appended claims are intended to be construed to include excellent Select embodiment and fall into having altered and changing for the scope of the invention.
Above to a kind of thin film transistor (TFT) provided by the present invention and preparation method thereof, display panel, display device, carry out It is discussed in detail, specific case used herein is set forth to the principle and embodiment of the present invention, above example Explanation be only intended to help to understand the method and its core concept of the present invention；Simultaneously for those of ordinary skill in the art, According to the thought of the present invention, it will change in specific embodiments and applications, in summary, in this specification Appearance should not be construed as limiting the invention.

Claims (10)

1. a kind of thin film transistor (TFT), it is characterised in that including：
The first grid, source electrode and drain electrode with layer are on substrate, is formed between the source electrode and the first grid First breach, is formed with the second breach between the drain electrode and the first grid；
It is covered in the gate insulator on the first grid；
It is covered in the source electrode, the gate insulator, in the drain electrode and is filled in first breach and described second The semiconductor layer of breach.
2. thin film transistor (TFT) according to claim 1, it is characterised in that the source electrode includes the first source electrode and the second source Pole, is respectively formed with institute between first source electrode and the first grid, and between the second source electrode and the first grid State the first breach.
3. thin film transistor (TFT) according to claim 1, it is characterised in that first breach or second notch geometry Including one of following shape：For arc, square, W shapes.
4. the thin film transistor (TFT) according to Claims 2 or 3, it is characterised in that the thin film transistor (TFT) also includes：
Passivation layer on the semiconductor layer；
Second grid on the passivation layer, the second grid is located above the first grid；The first grid Connected with the second grid by gate connection line, first source electrode and second source electrode are connected by source connection lines Connect.
5. a kind of display panel, it is characterised in that including the thin film transistor (TFT) any one of claim 1-4.
6. a kind of display device, it is characterised in that including the display panel described in claim 5.
7. a kind of preparation method of thin film transistor (TFT), it is characterised in that including：
First grid, source electrode and drain electrode are formed by a patterned process on substrate；The source electrode and the first grid Between be formed with the first breach, the second breach is formed between the drain electrode and the first grid；
Gate insulator is formed on the first grid；
Semiconductor layer is formed, wherein, semiconductor layer is formed in the first grid, the source electrode and the drain electrode, and it is described Semi-conducting material is filled with first breach and second breach.
8. method according to claim 7, it is characterised in that the source electrode includes the first source electrode and the second source electrode, described Described first is respectively formed between first source electrode and the first grid, and between the second source electrode and the first grid to lack Mouthful.
9. method according to claim 7, it is characterised in that under first breach or second notch geometry include One of row shape：For arc, square, W shapes.
10. method according to claim 8 or claim 9, it is characterised in that methods described also includes：
Passivation layer is formed on the semiconductor layer；
Form grid via and source electrode via；
Form metal conducting layer；
The metal conducting layer is etched to form second grid, the second grid is located at the top of the first grid, wherein, The first grid and the second grid are connected by the gate connection line of the grid via, first source electrode and described Second source electrode is connected by the source connection lines of the source electrode via.
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CN104752477A (en) * 2013-12-31 2015-07-01 乐金显示有限公司 Organic light emitting display device and method of manufacturing the same
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