KR20150078996A - Display device and method of driving the same - Google Patents

Abstract

The present invention relates to a display device and a method of driving the same. Especially, a technical purpose is to provide a display device and a method of driving the same, capable of receiving at least two clocks including phase change clocks with a changed phase and outputting a phase change scan pulse to a gate line by using the phase change clock. For this, the display device according to an embodiment of the present invention includes a panel where a pixel is formed in each intersection region of the gate lines and the data lines; and an embedded gate driver which is embedded in the non-display region of the panel, receives at least two clocks including a phase change clock with a changed phase, and outputs the phase change scan pulse with a changed phase to the gate line by using the phase change clock.

Description

DISPLAY APPARATUS AND DRIVING METHOD THEREOF

The present invention relates to a display device and a driving method thereof, and more particularly to a display device and a driving method thereof using an embedded gate driver.

The gate driver sequentially outputs a plurality of scan pulses to sequentially drive gate lines of a display device such as a liquid crystal display device and an organic light emitting display device.

The gate driver may be formed of an integrated circuit (IC), then mounted on a panel of the display device, or directly mounted on the panel.

The built-in gate driver, which is directly embedded in the panel, includes a shift register, and the shift register includes a plurality of stages that sequentially output the scan pulses. However, the shift register may mean the built-in gate driver.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is an exemplary view schematically showing the structure of a shift register constituting a conventional built-in gate driver. FIG. FIG. 2 is a timing chart illustrating waveforms of clocks input to the shift register shown in FIG. 1 and scan signals output from the shift register shown in FIG.

As shown in Fig. 1, the shift register 10 constituting a conventional built-in gate driver is constituted by a plurality of stages 11, Any one of the clocks as shown in FIG. In addition, the shift register 10 outputs the scan signals Vout using the clocks.

The scan signal Vout may include a scan pulse having a turn-on voltage capable of turning on a switching element of each pixel connected to a gate line formed on the panel, and a scan pulse having a turn- And a turn-off signal for maintaining the off state. 2 (b) shows the scan signals Vout including the scan pulse. The number of the scan pulses output during one frame may be the same as the number of the gate lines.

In the conventional shift register 10, as shown in FIG. 2A, a plurality of clocks are sequentially input. In particular, FIG. 2 (a) shows six clocks input to the shift register 10.

The shift register 1 sequentially outputs the scan pulses to the gate lines using the six clocks. In Fig. 2, scan pulses having the same pulse width and having the same output interval are shown. However, in the display device, a scan pulse having a pulse width different from the pulse width of the other scan pulses may be required, or a scan pulse having an output interval different from the output interval of the other scan pulses may be required It is possible.

However, in the conventional shift register 10, only the clocks Clk1 to Clk6 having a constant pulse width and having a constant interval are input as shown in Fig. Therefore, in the conventional shift register 10, only the scan pulses having a constant pulse width and having a constant interval are outputted.

That is, in the conventional shift register 10, various types of scan pulses can not be output.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned problems, and it is an object of the present invention to provide a phase change clock which receives at least two clocks including a phase change clock whose phase has been changed, A display device and a method of driving the same are provided.

According to an aspect of the present invention, there is provided a display device including: a panel having pixels formed at intersections of gate lines and data lines; And at least two clocks that are embedded in a non-display area of the panel and include a phase change clock whose phase has been changed, and outputs a phase change scan pulse whose phase is changed using the phase change clock to the gate line , And an embedded gate driver consisting of a shift register.

According to another aspect of the present invention, there is provided a method of driving a display device, comprising: receiving at least two clocks including a phase-change clock whose phase is changed; And outputting a phase change scan pulse having a phase changed using the phase change clock to a gate line formed on the panel.

According to the present invention, the output pattern of the scan pulse can be variously changed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a structure of a shift register constituting a conventional built-in gate driver; FIG.
FIG. 2 is a timing chart showing waveforms of clocks input to the shift register shown in FIG. 1 and scan signals output from the shift register shown in FIG. 1;
Fig. 3 schematically shows a display device according to the present invention. Fig.
FIG. 4 is a schematic view showing a structure of a shift register constituting a built-in gate driver according to the present invention; FIG.
FIGS. 5 to 7 are timing diagrams illustrating clocks supplied to the shift register and scan pulses output from the shift register, which constitute the built-in gate driver according to the present invention.
8 and 9 are exemplary views showing a timing controller and a level shifter applied to a display device according to the present invention.
10 to 13 are various exemplary views schematically showing a circuit of a stage applied to a display device according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view schematically showing a display device according to the present invention.

3, the display device according to the present invention includes a panel (P) 110 having pixels (P) 110 formed at intersections of the gate lines GL1 to GLg and the data lines DL1 to DLd 100), receiving at least two or more clocks embedded in a non-display area of the panel and including a phase change clock whose phase is changed, and outputting a phase change scan pulse having a phase changed using the phase change clock to the gate line A data driver 300 for supplying a data voltage to the data lines DL1 to DLd formed on the panel 100, a data driver 300 for supplying data voltages to the data lines DL1 to DLd, A timing controller 400 for controlling the functions of the built-in gate driver 200 and the data driver 300 and amplifying the clocks generated by the timing controller 400, And a level shifter 500 for transmission to the register 600. The display device may be a liquid crystal display device, an organic light emitting display device, and various other kinds of display devices. However, in the following, a display device and a driving method thereof according to the present invention will be described in detail by taking an organic light emitting display device as an example.

First, a pixel P 110 is formed in the panel 100 in an area where a plurality of gate lines GL1 to GLg and a plurality of data lines DL1 to DLd intersect each other.

Each of the pixels 110 includes an organic light emitting diode (OLED) for outputting light and a pixel circuit for driving the organic light emitting diode.

First, the organic light emitting diode (OLED) includes a substrate, an anode formed on the substrate, an organic light emitting layer formed on the anode, and a cathode formed on the organic light emitting layer.

The anode outputs light by a current transmitted by a driving transistor formed in the pixel circuit, and an upper substrate is bonded to the cathode upper end. The anode may be formed of a transparent conductive material, for example, indium tin oxide (ITO) (hereinafter, simply referred to as ITO). The cathode may also be made of the ITO.

The organic light emitting layer may include a hole transporting layer, a light emitting material layer, and an electron transporting layer. In order to improve the luminous efficiency of the organic light emitting layer, a hole injection layer may be formed between the anode and the hole transport layer, and an electron injection layer may be formed between the cathode and the electron transport layer.

The structure and function of the organic light emitting diode (OLED) are the same as the structure and function of the organic light emitting diode applied to the conventional organic light emitting display, and a detailed description thereof will be omitted.

Second, the pixel circuit includes at least two transistors and a storage capacitor connected to the data lines DL and the gate lines GL to control the organic light emitting diode OLED .

The anode of the organic light emitting diode (OLED) is connected to a first power supply of the pixel circuit, and the cathode is connected to a second power supply of the pixel circuit. The organic light emitting diode OLED outputs light of a predetermined luminance corresponding to the current supplied from the driving transistor.

The pixel circuit controls the amount of current supplied to the organic light emitting diode OLED according to the data voltage Vdata supplied to the data line DL when the scan pulse is supplied to the gate line GL do.

In particular, the phase change scan pulse may be supplied to the pixel circuit. The phase change scan pulse may be output after a delay of a predetermined period after the scan pulse output before the phase change scan pulse is output.

The phase change scan pulse may be output for a period longer than a period during which the scan pulse other than the phase change scan pulse is output for a predetermined period of time.

For example, the pixel circuit may be composed of transistors of various structures to compensate for a change in characteristics of the organic light emitting diode, and various types of control signals may be supplied to configure the transistors .

In this case, the phase-change scan pulse having a pulse width or an output period different from that of the scan pulses may be supplied from the shift register 600 to the pixel circuit. The phase change scan pulse will be described with reference to FIGS. 5 to 7. FIG.

The structure and function of the pixel circuit can be variously changed according to the configuration and function of the pixel circuit, and a detailed description thereof will be omitted.

Next, the timing controller 400 generates a gate control signal GCS for controlling the embedded gate driver 200 using a vertical synchronizing signal, a horizontal synchronizing signal and a clock signal supplied from an external system (not shown) And outputs a data control signal DCS for controlling the data driver 300.

The gate control signals GCS include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal VST and a clock CLK. In addition, the gate control signals GCS may include various kinds of control signals for controlling the shift register 600.

A source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL are input to the data control signals DCS generated by the timing controller 400 .

The timing controller samples the input image data input from the external system, rearranges the input image data, and supplies the rearranged digital image data to the data driver 300.

That is, the timing controller 400 rearranges the input image data supplied from the external system to transmit the rearranged digital image data to the data driver 300, and outputs the clock signal supplied from the external system and the horizontal A gate control signal GCS for controlling the built-in gate driver 200 using a synchronous signal, a vertical synchronous signal (the signals are simply referred to as a timing signal) and a data enable signal DE, And transmits the generated data control signal DCS to the built-in gate driver 200 and the data driver 300.

In addition, the timing controller 400 controls the shift register 600 to output at least two or more clocks including a phase-changed clock having a phase changed to the shift register 600 so that the phase- And performs the function of transmitting.

The phase change clock may be amplified by the level shifter 500 and then transmitted to the shift register 600.

Next, the level shifter 500 amplifies the clocks and the phase change clock, and transmits the amplified clocks to the shift register 600. The phase change clock may be generated in the timing controller 400 and amplified in the level shifter 500. The manner in which the phase change clock is generated will be described with reference to Figs. 8 and 9. Fig.

Next, the data driver 300 converts the image data inputted from the timing controller 400 into an analog data voltage, and supplies a data voltage of one horizontal line in each horizontal period in which the gate pulse is supplied to the gate line To the data lines.

Finally, the built-in gate driver 200 is formed of a gate-in-panel (GIP) method mounted on the panel 100. In this case, the gate control signals for controlling the built-in gate driver 200 may include a start signal VST and a clock CLK.

The built-in gate driver 200 sequentially supplies scan pulses to the gate lines GL1 to GLg of the panel 100 in response to the gate control signal input from the timing controller 400. [

As the scan pulse is supplied to the gate lines, the thin film transistors (TFT) formed on each pixel of the corresponding horizontal line to which the scan pulse is input are turned on, and the image is output to each pixel P have. That is, the scan pulse has a turn-on voltage capable of turning on a switching element (thin film transistor) formed in the pixel.

In particular, the functions described above are performed in the shift register 600 constituting the built-in gate driver 200.

That is, the shift register 600 sequentially applies the scan pulses to the gate lines sequentially for one frame by using the start signal VST and the clock CLK transmitted from the timing controller 400 Supply. Here, one frame refers to a period during which one image is output through the panel 100. [

The shift register 600 supplies a turn-off signal that can turn off the switching element to the gate line during the remaining period of the frame during which the scan pulse is not supplied.

In the following description, the scan pulse and the turn-off signal are generically referred to as the scan signal. That is, the scan signal includes a scan pulse having a turn-on voltage capable of turning on a switching element of each pixel connected to the gate line, a scan pulse for turning on the switch for a remaining period of one frame Off signal.

4 is a schematic view illustrating the structure of a shift register constituting a built-in gate driver according to the present invention.

The shift register 600 constituting the built-in gate driver 200 according to the present invention includes g stages 690 as shown in FIG. That is, the number of the stages 690 is equal to the number of the gate lines GL1 to GLg. However, the number of stages 690 does not necessarily match the number of gate lines.

The shift register 600 transmits one scan signal Vout to the pixels 110 formed in the one horizontal line through one gate line formed in one horizontal line, At least one of the gate lines is connected to each of the stages.

The first stage Stage 1 of the stages 690 starts driving by the start signal transmitted from the timing controller 400 and outputs the first clock CLK1 as the scan pulse.

The second stage Stag2 is driven by the first scan pulse output from the first stage and outputs the second clock signal CLK2 as the scan pulse.

That is, two or more clocks may be supplied to the shift register 600, and the shift register 600 outputs a plurality of scan pulses using the clocks.

Hereinafter, as shown in FIG. 4, the present invention will be described by exemplifying a shift register that sequentially outputs the scan pulses to the gate lines by using six clocks. In this case, in FIG. 3, six clocks (CLK) are supplied from the level shifter 500 to the shift register 600.

The clocks (CLK) include a phase change clock whose phase has changed. The phase change clock means a clock having a different pulse width or an output interval different from the output interval between other clocks when compared with other clocks. The clocks including the phase change clocks are generated in the timing controller 400 and the level shifter 500 and then transferred to the shift register 600.

The phase change scan pulse is a scan pulse generated by the phase change clock and output to the gate line. Therefore, the phase change scan pulse has a different pulse width when compared with other scan pulses, or has an output gap different from the output gap between the other scan pulses.

In other words, the shift register 600 sequentially outputs the scan pulses to the gate lines using the clocks CLK, and at least one of the scan pulses sequentially output to the gate lines One of them is the phase change scan pulse.

In addition, the shift register 600 outputs the phase change scan pulse, which is delayed by a predetermined period, to the gate line after the output scan pulse is output before the phase change scan pulse is output. That is, as described above, the phase change scan pulse may have an output interval different from an output interval between other scan pulses.

The shift register 600 may output the phase change scan pulse having a pulse width larger than the pulse width of the scan pulse other than the phase change scan pulse. That is, the phase change scan pulse may have a different pulse width when compared with other scan pulses.

The shift register 600 outputs at least one of the phase change scan pulses for every frame or outputs at least one phase change scan pulse for every predetermined frame, Can be output at random.

That is, at least one of the phase change scan pulses may be output every frame, output every predetermined frame, or randomly output.

5 to 7 are timing diagrams illustrating clocks supplied to a shift register and scan pulses output from the shift register of the embedded gate driver according to the present invention.

Referring to FIG. 5A, six clocks (CLK1 to CLK6) are sequentially supplied to the shift register 600.

Particularly, among the clocks shown in FIG. 5A, the first clock CLK1 may be the phase change clock.

That is, the second pulse among the pulses constituting the first clock CLK1 is a pulse that is output after the first pulse of the sixth clock CLK6 is outputted as shown in FIG. 5 (a) , And is output after being delayed by a predetermined period (A).

In other words, the intervals of all the pulses except the second pulse of the first clock CLK1 and the first pulse of the sixth clock CLK6 are constant. That is, when a pulse constituting one clock is output, a pulse constituting another clock is outputted immediately. However, as shown in FIG. 5A, the second pulse of the first clock CLK1 may be output after the first pulse of the sixth clock CLK6 is output, And is outputted after being delayed by the period (A).

In the above example, the period A to be delayed may be a period during which one pulse is output as described above, but may be a period during which two or more pulses are output.

Also, the period (A) is not necessarily formed in pulse units.

Also, the period A may be a positive value, as shown in FIG. 5A, but may be a negative value.

Also, as shown in Fig. 7 (a), there may be a delay period even when the pulse width is different.

5 (b), the seventh scan pulse Vout7, which is output after the sixth scan pulse is output and is delayed by the period (A), is output by the phase change clock as described above, Phase shift scan pulse.

That is, unlike the other scan pulses, the seventh scan pulse Vout7 is output after being delayed by the period A after the immediately precedingly output sixth scan pulse Vout6.

Next, among the clocks shown in FIG. 6A, the third clock CLK3 may be the phase change clock.

That is, among the pulses constituting the third clock signal CLK3, the second pulse signal is output after the second pulse of the second clock signal CLK2 is output, as shown in FIG. 6 (a) , And is output after being delayed by a predetermined period.

In other words, the intervals of all the pulses except the second pulse of the third clock CLK3 and the second pulse of the second clock CLK2 are constant. That is, when a pulse constituting one clock is output, a pulse constituting another clock is outputted immediately. However, as shown in FIG. 6A, the second pulse of the third clock CLK3 may be a pulse after the second pulse of the second clock CLK2 is outputted, And is outputted after being delayed by the period (A).

Also, the third pulse of the third clock CLK3 is also output after the third pulse of the second clock CLK2 is output after being delayed by the period (A).

In this example, since two phase change clocks are supplied to the shift register 600 in one frame, as shown in FIG. 6 (b), in the one frame, two phase change scans A pulse can be output.

That is, in this example, each of the ninth scan pulse Vout9 and the fifteenth scan pulse Vout15 becomes the phase change scan pulse.

In the above example, the ninth scan pulse Vout9 and the fifteenth scan pulse Vout15, which are the phase change scan pulses, are output after being delayed by the same period (A). However, the delay period A of the two phase change scan pulses generated by one clock may be different from each other.

Lastly, among the clocks shown in FIG. 7A, the third clock CLK3 may be the phase change clock.

That is, the second pulse among the clocks constituting the third clock CLK3 is a pulse that is output after the second pulse of the second clock CLK2 is outputted as shown in FIG. 7 (a) And is output continuously for a period (A) during which two pulses are output. That is, the phase change clock has a pulse width two times larger than the pulse width of the other clocks.

However, the phase change clock may have a pulse width three times larger than the pulse width of the other clocks.

Also, among the clocks constituting the third clock (CLK3), the third output pulse is a pulse which is generated after the third pulse of the second clock (CLK2) is outputted , And output after being delayed by a predetermined period (A).

By the phase change clock as described above, the ninth scan pulse (Vout9) and the fifteenth scan pulse (Vout15) become phase change scan pulses, as shown in (b) of FIG.

That is, the ninth scan pulse Vout9 is a phase change scan pulse having a pulse width two times larger than the pulse width of the other scan pulses.

As described above, the phase change scan pulse is generated by the phase change clock, and the phase change scan pulse is output after being delayed by a predetermined period (A) Width, or may have a pulse width less than the pulse width of the other scan pulses.

8 and 9 illustrate a timing controller and a level shifter applied to a display device according to the present invention, and show how the phase change clock is generated.

First, referring to FIG. 8A, the phase change clock may be generated from the level shifter 500 by changing a control signal supplied to the level shifter 500.

For example, the control signal generator 410 of the timing controller 400 generates a phase change signal PDS together with the general clocks not including the phase change clock, that is, the circulation control signal CCS, .

The operation unit 420 of the timing controller 400 generates the phase modulation signal PMS using the circulation control signal CCS and the phase change signal PDS.

The phase modulated signal PMS is supplied to the level shifter 500. The level shifter 500 generates the phase modulated clock or the clock using the phase modulated signal PMS. In this case, the structure of the level shifter 500 may be the same as that of the conventional level shifter 500.

For example, as shown in FIG. 8B, the level shifter 500 uses the first phase modulation signal PMS1 and the second phase modulation signal PMS2 to switch the first switch SW1 ) And the second switch SW2 are turned on and the other is turned off, thereby generating clocks including the phase change clock as shown in Figs. 5 to 7 (a).

In this case, the scan pulses including the phase change scan pulse as shown in FIGS. 5 to 7B may be output to the gate lines by the clocks including the phase change clock.

Referring to FIG. 9A, the phase change clock may be generated from the level shifter 500 by changing the structure of the level shifter 500.

For example, the timing controller 400 generates a phase change signal PDS together with the general clocks not including the phase change clock, that is, the circulation control signal CCS.

The circulation control signal CCS and the phase change signal PDS are supplied to the level shifter 500. The level shifter 500 uses the circulation control signal CCS and the phase change signal PDS, And generates the phase change clock or the clock. In this case, the structure of the level shifter 500 may be different from that of the conventional level shifter 500.

For example, the level shifter 500 may be formed of four switches SW1, SW2, SW3, and SW4, as shown in FIG. 9 (b). The level shifter 500 uses the first circulation control signal CCS, the second circulation control signal CCS2, the first phase change signal PDS1, and the second phase change signal PDS2, By turning the switches SW1 to SW4 on and off, it is possible to generate clocks including the phase change clock as shown in FIGS. 5 to 7 (a).

In this case, the scan pulses including the phase change scan pulse as shown in FIGS. 5 to 7B may be output to the gate lines by the clocks including the phase change clock.

10 to 13 are various exemplary diagrams schematically showing a circuit of a stage applied to a display device according to the present invention.

The shift register 600 includes a plurality of stages 690, and each of the stages 690 may be formed in various structures as shown in FIGS. 10 to 13. That is, in the following, the structure of the stage 690 described with reference to Figs. 10 to 13 is described as an example. Therefore, the structure of the stage 690 can be variously changed.

The stage 690 shown in FIG. 10 includes an output unit for outputting the phase-change scan pulse or the scan pulse using any one of the clocks including the phase-change clock, the start signal Vst And a reset unit for preventing the output unit from outputting the phase change scan pulse or the scan pulse using a reset signal and a driver for causing the output unit to output the phase change scan pulse or the scan pulse.

The driver may include a first transistor (T1) and various power sources (VD). A start signal Vst is supplied to the first transistor T1. The start signal Vst may be transmitted from the timing controller 400 or may be a carry signal transmitted from the previous stage.

The output unit may be composed of a pull-up transistor Tpu. The pull-up transistor Tpu may be turned on by a signal transmitted from the driver and may be used to scan any one of the phase change scan pulse and the scan pulse using any one of the clocks CLK including the phase change clock. And outputs a pulse Vout to the gate line.

The reset unit may include a second transistor T2 and various power sources VSS. A reset signal Vreset is supplied to the second transistor T2. The reset signal Vreset may be a carry signal transmitted from the next stage or may be a clock different from the clock CLK supplied to the output unit. The reset signal may be a separate signal transmitted from the timing controller.

The power source VSS applied to the reset unit may be another clock, an output of the current stage, or another separate power source.

The charging or discharging of the Q node Q of the output device can be performed in various forms by the output (carry signal) of the previous stage, the output (carry signal) of the next stage and the various power sources (VD, VSS) ≪ / RTI >

Here, the shearing stage is not limited to the stage just before the stage shown in Fig. Thus, the front stage may be two or three stages before. Likewise, the next stage is not limited to the stage immediately after the stage shown in Fig. Thus, the next stage may be two or more stages.

The clock CLK supplied to the output unit may be any one of the first to sixth clocks CLK1 to CLK6 shown in FIGS. Therefore, the clock (CLK) supplied to the output unit may be a phase change clock.

11, the stage 690 includes an output unit for outputting the phase-change scan pulse or the scan pulse using any one of the clocks including the phase-change clock, the start signal Vst using the start signal Vst And a reset unit for preventing the output unit from outputting the phase change scan pulse or the scan pulse using a reset signal and a driver for causing the output unit to output the phase change scan pulse or the scan pulse. The difference between the stage 690 shown in FIG. 11 and the stage shown in FIG. 10 is that the carry signal Vcarry is output separately from the scan pulse Vout in the output unit.

To this end, the output unit is provided with a second pull-up transistor Tpu2 for outputting the scan pulse Vout and a first pull-up transistor Tpu1 for outputting the carry signal Vcarry. The gate terminals of the first pull-up transistor and the second pull-up transistor are connected to the Q node, and when the gate terminal is turned on, the clock terminal CLK is output.

Third, the stage 690 shown in FIG. 12 also includes the output device, the driver, and the reset device, and in particular, has a structure similar to the stage shown in FIG. The difference from the stage 690 shown in Fig. 12 and the stage shown in Fig. 10 is that a pull-down transistor Tpd for outputting a turn-off signal to the gate line is formed in the output unit.

An inverter is formed in the output unit for driving the pull-down transistor Tpd.

For example, when the start signal Vst is high, the pull-up transistor Tpu is turned on by the start signal, and the clock CLK is output as the scan pulse to the gate line . In this case, a low signal is supplied to the QB node which is the gate terminal of the pull-down transistor Tpd by the inverter. Thus, the pull-down transistor Tpd is turned off.

When the start signal is low, the pull-up transistor is turned off by the start signal and the scan pulse is not output. In this case, a high signal is supplied to the QB node by the inverter, and the pull-down transistor Tpd is turned on. Therefore, a turn-off signal is output to the gate line by the power supply VSS3 to which the pull-down transistor is connected.

Fourth, the stage 690 shown in FIG. 13 also includes the above-described output device, the driver, and the reset device, and particularly has a structure similar to the stage shown in FIG. The difference from the stage 690 shown in Fig. 13 and the stage shown in Fig. 11 is that a pull-down transistor Tpd for outputting a turn-off signal to the gate line is formed in the output unit.

An inverter is formed in the output unit for driving the pull-down transistor Tpd.

For example, when the start signal Vst is high, the first pull-up transistor Tpu1 and the second pull-up transistor Tpu2 are turned on by the start signal and the clock CLK is turned on The scan pulse is output to the gate line. In this case, a low signal is supplied to the QB node which is the gate terminal of the pull-down transistor Tpd by the inverter. Thus, the pull-down transistor Tpd is turned off.

When the start signal is low, the pull-up transistors are turned off by the start signal, and the scan pulse is not output. In this case, a high signal is supplied to the QB node by the inverter, and the pull-down transistor Tpd is turned on. Therefore, a turn-off signal is output to the gate line by the power supply VSS3 to which the pull-down transistor is connected.

The stage 690 applied to the present invention may have various structures other than the structures shown in FIGS. 10 to 13, and the inverter may have various structures.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200: gate driver
300: Data driver 400: Timing controller
600: shift register 690: stage
500: Level shifter

Claims (10)

Receiving at least two clocks including a phase-changed clock whose phase has changed; And
And outputting a phase change scan pulse whose phase is changed using the phase change clock to a gate line formed on the panel. The method according to claim 1,
The step of outputting the phase change scan pulse includes:
Wherein the scan driver sequentially outputs scan pulses to the gate lines using the clocks, and at least one of the scan pulses sequentially output to the gate lines is the phase change scan pulse. . 3. The method of claim 2,
Wherein the phase change scan pulse is delayed by a predetermined period of time after the scan pulse output before the phase change scan pulse is output, and then output. 3. The method of claim 2,
Wherein the pulse width of the phase change scan pulse is larger than the pulse width of the scan pulse other than the phase change scan pulse. The method according to claim 1,
Wherein the phase change scan pulses are outputted at least one frame at every frame or at least one frame every predetermined frame or are randomly output. A panel in which pixels are formed for each intersection region of the gate lines and the data lines; And
And a phase change scan pulse that is embedded in a non-display area of the panel and receives at least two clocks including a phase change clock whose phase has been changed, A display device comprising an embedded gate driver configured as a shift register. The method according to claim 6,
The shift register includes:
And sequentially outputs scan pulses to the gate lines using the clocks, and at least one of the scan pulses sequentially output to the gate lines is the phase change scan pulse. 8. The method of claim 7,
The shift register includes:
Wherein the phase change scan pulse is output to the gate line after the output of the scan pulse output before the phase change scan pulse is output and after the delay is delayed by a predetermined period. 8. The method of claim 7,
The shift register includes:
And outputs the phase change scan pulse having a pulse width larger than the pulse width of the scan pulse other than the phase change scan pulse. The method according to claim 6,
The shift register includes:
Characterized in that at least one phase change scan pulse is outputted for every frame or at least one phase change scan pulse is outputted for every predetermined frame or the phase change scan pulse is outputted at random Device.

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