KR20150078981A - Flat panel display and driving method the same - Google Patents

Abstract

The present invention relates to a flat panel display and a driving method the same. The present invention includes a display panel; a system which operates according to a slip in mode having a dormant state, a normal mode of transmitting a clock signal and image data, and a slip out mode of transmitting the clock signal required for generating driving voltages in a range between the slip in mode and the normal mode; and a panel driving circuit which drives the display panel and has a charge pump which generates a gate high voltage and a gate low voltage for driving the display panel by using the clock signal. The system successively transmits the clock signal in the slip mode, transmits a clock signal in the normal mode, and doesn′t transmit the clock signal according to a blank period between frames.

Description

Technical Field [0001] The present invention relates to a flat panel display,

The present invention relates to a flat panel display and a driving method thereof.

2. Description of the Related Art Flat panel displays include a liquid crystal display (LCD) using a liquid crystal, a plasma display panel (PDP) using an inert gas discharge, an organic light emitting diode (OLED) Hereinafter referred to as "OLED") display device.

The interface circuit technology for data transmission in such a flat panel display device is being developed as a low voltage, high speed serial transmission technology. The Mobile Industry Processor Interface (MIPI) interface, which is the standard of serial interface, is realized as an optimal interface technology in mobile environment by implementing low voltage and high speed data transfer. The mobile information device using the MIPI interface can respond to standard commands of the MIPI interface by providing a sleep mode, a sleep out mode, a normal driving mode or a display on mode ), And the operation mode can be switched to the DLP (Dimmed Low Power, hereinafter referred to as "DLP") mode. In the sleep-in mode and the DLP mode, the driving voltages of the display panel maintain the ground voltage (GND), and the display panel driving circuit does not operate, thereby reducing the power consumption of the mobile information device. In the sleep-out mode, the driving voltages of the display panel rise to the driving voltage level and the driving circuits of the display panel start to operate. In the normal driving mode, the driving circuit of the display panel normally operates to display an image input from the phone main chip.

However, the conventional mobile information apparatus has a problem in that the driving voltage of the display panel can not maintain the driving voltage level because the load of the driving voltage supply line is rapidly increased when the sleep mode or the DLP mode is switched to the sleep-out mode. The drop of the driving voltage of the display panel causes a malfunction of the driving circuits and causes a deterioration of the image quality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a liquid crystal display device capable of stabilizing a driving voltage for driving a display panel when switching from a sleep mode or a DLP mode to a sleep mode, It is an object of the present invention to provide a flat panel display and a driving method thereof.

According to an aspect of the present invention, there is provided a flat panel display comprising: a display panel; A sleep mode having a sleep state, a normal mode for transmitting a clock signal and image data, and a sleep mode for transmitting the clock signal required for generating driving voltages in a period between the sleep mode and the normal mode A system that operates separately; A panel drive circuit having a charge pump for driving the display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal; The system continuously transmits the clock signal in the sleep-out mode, transmits the clock signal in the normal mode, and does not transmit the clock signal in every blank period between frames.

According to another aspect of the present invention, there is provided a flat panel display comprising: a display panel; A sleep mode having a sleep state, a normal mode for transmitting a clock signal and image data, and a sleep mode for transmitting the clock signal required for generating driving voltages in a period between the sleep mode and the normal mode A system that operates separately; A panel drive circuit having a charge pump for driving the display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal; The system does not transmit the clock signal for every blank period between frames, and the panel driving circuit generates a clock signal, which generates a dummy clock signal having the same phase as the clock signal and continuously output in the sleep-out mode The charge pump generates the gate high voltage and the gate low voltage using the dummy clock signal instead of the clock signal in the sleep-out mode.

Further comprising: a voltage generator for generating and outputting a high potential voltage from the DC input voltage; Wherein the charge pump charges the DC input voltage during the normal mode to generate a reference voltage and uses the reference voltage to generate the gate low voltage; In the sleep-out mode, the direct-current input voltage is charge-pumped to generate the reference voltage, and the gate-low voltage is generated using the high-potential voltage provided from the voltage generator.

The panel drive circuit further comprises a register for controlling the charge pump to vary a level of the gate high voltage and the gate low voltage generated from the charge pump; Wherein the register varies the gate high voltage higher than a setting value corresponding to the normal mode and changes the gate low voltage lower than a setting value corresponding to the normal mode in the sleep-out mode.

According to another aspect of the present invention, there is provided a method of driving a flat panel display device including a sleep mode having a sleep state, a normal mode transmitting a clock signal and image data, And a sleep-out mode for transmitting the clock signal required for generation of driving voltages in a period between the normal mode and the normal mode; And a charge pump for driving a display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal, the method comprising: The system continuously transmitting the clock signal in the sleep-out mode; The system transmitting the clock signal in the normal mode but not transmitting the clock signal in every blank period between frames.

According to another aspect of the present invention, there is provided a method of driving a flat panel display device including a sleep mode having a sleep state, a normal mode transmitting a clock signal and image data, And a sleep-out mode for transmitting the clock signal required for generation of driving voltages in a period between the normal mode and the normal mode; And a charge pump for driving a display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal, the method comprising: The system transmitting the clock signal but not transmitting the clock signal every blank period between frames; Generating a dummy clock signal having the same phase as the clock signal and being continuously output in the sleep-out mode; And generating the gate high voltage and the gate low voltage by using the dummy clock signal instead of the clock signal when the charge pump is in the sleep-out mode.

Further comprising the step of generating and outputting a high-potential voltage from a DC input voltage separately provided from the panel drive circuit; Wherein the charge pump charges the DC input voltage during the normal mode to generate a reference voltage and uses the reference voltage to generate the gate low voltage; In the sleep-out mode, the direct-current input voltage is charge-pumped to generate the reference voltage, and the gate-low voltage is generated using the high-potential voltage provided from the voltage generator.

The panel drive circuit further comprises a register for controlling the charge pump to vary a level of the gate high voltage and the gate low voltage generated from the charge pump; Wherein the register varies the gate high voltage higher than a setting value corresponding to the normal mode and changes the gate low voltage lower than a setting value corresponding to the normal mode in the sleep-out mode.

In the sleep-out mode, the charge pump supplies a continuous clock signal to the charge pump to prevent the drop of the drive voltages so that the charge pump can continuously perform the switching operation.

In addition, in the sleep-out mode, the gate-low voltage is generated by pumping the high-potential power supply voltage provided from the external voltage generator instead of the reference voltage generated in the charge pump in the sleep-out mode, have.

Further, in the sleep-out mode, the present invention varies the set values of the gate high voltage and the gate low voltage to compensate for the drop of the gate high voltage and the gate low voltage.

Therefore, the present invention can stabilize the driving voltage including the gate high voltage and the gate low voltage in the sleep-out mode, thereby preventing the deterioration of image quality due to malfunction of the driving circuit.

1 is a configuration diagram of an OLED display device according to an embodiment of the present invention.
2 is a view for explaining the mode switching of the host system 60. As shown in Fig.
3 is a diagram showing a mode conversion of the host system 60 according to the first embodiment.
4 is a diagram showing a part of the constitution of the panel driving circuit chip 100 according to the second embodiment.
5 is a drive waveform diagram of the panel drive circuit chip 100 shown in Fig.
6 is a block diagram showing a part of the charge pump 80 of the prior art.
7 is a diagram showing a part of the constitution of the panel driving circuit chip 100 according to the third embodiment.
8 is a configuration diagram showing a part of the charge pump 80 shown in Fig.
9 is a diagram showing a part of the constitution of the panel drive circuit chip 100 according to the fourth embodiment.
10 is a driving waveform diagram of the panel driving circuit chip 100 shown in Fig.

Hereinafter, a flat panel display according to an embodiment of the present invention and a driving method thereof will be described in detail with reference to the accompanying drawings.

The flat panel display of the present invention may be implemented as a liquid crystal display, a plasma display panel, an OLED display, or the like. Hereinafter, the OLED display device will be mainly described, but the present invention is not limited to the OLED display device.

1 is a configuration diagram of an OLED display device according to an embodiment of the present invention.

1, an OLED display according to an exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a gate driver 30, a voltage generator 50, and a timing controller 40 do.

The display panel 10 includes data lines to which a data voltage is supplied, gate lines that are sequentially supplied with a scan pulse (SCAN) and a light emission control pulse (EM) intersecting with the data lines, (11). The high-potential power supply voltage VDDEL is applied to the light-emitting cells 11. [ The light emitting cells 11 include a plurality of thin film transistors (hereinafter referred to as "TFTs "), a capacitor Cb and an OLED.

The data driver 20 converts the digital video data RGB to a gamma compensation voltage under the control of the timing controller 40 to generate a data voltage and supply the data voltage to the data lines.

The gate driver 30 supplies the scan lines SCAN and the emission control pulses EM to the gate lines under the control of the timing controller 40. [ The gate driver 30 may be embedded in the non-display area of the display panel 10. [ Although not shown, the gate driver 30 may be integrated and connected to one side of the display panel 10. This gate driver 30 is supplied with the gate high voltage VGH and the gate low voltage VGL provided from the charge pump incorporated in the timing controller 8. [

The voltage generator 50 may be configured as a DC-DC converter. The DC-DC converter is enabled in a sleep-out mode and a normal driving mode to generate a high-potential power supply voltage VDDEL for driving the light-emitting cells 11. The dc-to-dc converter is disabled in the sleep-in mode and the DLP mode and does not generate an output.

The timing controller 40 generates timing control signals for controlling the operation timing of the data driver 20 and the gate driver 30 based on a timing signal input from the host system 60. [ The timing signal may include a vertical / horizontal synchronizing signal, a clock signal, and the like. The timing controller 40 supplies input image data from the host system 60 to the data driver 20 in the normal drive mode.

The data driver 20, the gate driver 30, and the timing controller 40 may be integrated into a single chip to form the panel driving circuit chip 100.

The host system 60 may be a phone system in a mobile information appliance. The host system 60 is connected to a communication module (not shown), a camera module, an audio processing module, an interface module, a battery, a user input device, and a panel driving circuit chip 100.

2 is a view for explaining the mode switching of the host system 60. As shown in Fig.

2, the host system 60 includes a sleep mode in a sleep state or a DLP mode in a low power mode, a normal mode in which a clock signal CLK and image data are transmitted, And a sleep-out mode for transmitting a clock signal (CLK) necessary for generating driving voltages in a period between the modes. The host system 60 generates a mode switching command for switching the driving mode and supplies it to the panel driving circuit chip 100.

For reference, in the prior art MIPI interface, the host system 60 transmits the clock signal CLK but does not transmit the clock signal CLK every blank period between the frames. This is to prevent an image quality defect due to electro magnetic interference when the clock signal (CLK) is transmitted. In this case, the host system 60 does not transmit the clock signal CLK every frame for a specific period even in the sleep-out mode. When the clock signal CLK is not transmitted, the charge pump for generating the drive voltage in the panel drive circuit chip 100 stops switching, and the drop of the drive voltage due to the load increase of the drive voltage supply line is further intensified.

In order to solve the above-described problems, the present invention proposes the following configuration and driving methods.

First Embodiment

3 is a diagram showing a mode conversion of the host system 60 according to the first embodiment.

Referring to FIG. 3, in the first embodiment, the host system 60 continuously transmits the clock signal CLK in the sleep-out mode, transmits the clock signal CLK in the normal mode, The clock signal CLK is not transmitted.

Then, the charge pump of the panel drive circuit chip 100 continuously performs the switching operation during the sleep-out mode to generate the driving voltages, so that the drop of the driving voltage due to the increase in the load of the driving voltage supply line is prevented.

Since the first embodiment can prevent the driving voltage from dropping in the sleep-out mode period only by changing the clock signal CLK transmitted from the host system 60, it is possible to improve the image quality without adding a separate circuit.

Second Embodiment

4 is a diagram showing a part of the constitution of the panel driving circuit chip 100 according to the second embodiment. 5 is a drive waveform diagram of the panel drive circuit chip 100 shown in Fig.

Referring to FIG. 4, the panel driving circuit chip 100 according to the second embodiment includes a charge pump 80 for generating driving voltages from a DC input voltage VPNL, A register 70 for varying the gate high voltage VGH and the gate low voltage VGL generated from the dummy clock signal 80 and a dummy clock signal CLK having the same phase as the clock signal CLK in the sleep- And a clock generator 90 for generating DCLK.

In the second embodiment, the host system 60 does not transmit the clock signal CLK in the sleep-out mode every frame for a specific period as in the prior art.

However, the second embodiment includes a clock generator 90 that operates only in the sleep-out mode and outputs the dummy clock signal DCLK. The dummy clock signal DCLK has the same phase as the clock signal CLK and is continuously output as shown in Fig. The charge pump 80 of the panel drive circuit chip 100 uses the dummy clock signal DCLK provided from the clock generator 90 instead of the clock signal CLK provided from the host system 60 in the sleep- .

Then, the charge pump 80 continuously performs the switching operation during the sleep-out mode to generate the driving voltages, so that the drop of the driving voltage due to the increase in the load of the driving voltage supply line is prevented.

Third Embodiment

6 is a block diagram showing a part of the charge pump 80 of the prior art. 7 is a diagram showing a part of the constitution of the panel driving circuit chip 100 according to the third embodiment. 8 is a configuration diagram showing a part of the charge pump 80 shown in Fig.

In the third embodiment, the host system 60 does not transmit the clock signal CLK in the sleep-out mode every frame for a specific period, as in the prior art.

For reference, the prior art charge pump charges the DC input voltage (VPNL) in the sleep-out mode or the normal mode to generate the reference voltage (DDVDH). And the charge pump charges the reference voltage DDVDH to generate the gate-low voltage VGL, as shown in Fig. This prior art technique has a problem that the reference voltage DDVDH generated from the charge pump and the gate generated by charge pumping the reference voltage DDVDH due to the fact that the clock signal CLK is not transmitted every frame for a specific period in the sleep- There is a problem that the low voltage VGL drops in a chain.

Referring to FIG. 7, the charge pump 80 according to the third embodiment applies a direct current input voltage VPNL and a high potential power supply voltage VDDEL provided from the voltage generator 50. The charge pump 80 charges the DC input voltage VPNL to generate the reference voltage DDVDH. 8, the charge pump 80 switches the reference voltage DDVDH or the high potential power supply voltage VDDEL and uses either the reference voltage DDVDH or the high potential power supply voltage VDDEL Thereby generating a gate-low voltage VGL. Specifically, in the normal mode, the charge pump 80 generates the gate-low voltage VGL using the reference voltage DDVDH. The charge pump 80 generates the gate-low voltage VGL using the high-potential power supply voltage VDDEL in the sleep-out mode.

This third embodiment charges the high-potential power supply voltage VDDEL provided from the voltage generator 50 instead of the reference voltage DDVDH generated in the charge pump to generate the gate-low voltage VGL, (VGL) can be prevented.

Fourth Embodiment

9 is a diagram showing a part of the constitution of the panel drive circuit chip 100 according to the fourth embodiment. 10 is a driving waveform diagram of the panel driving circuit chip 100 shown in Fig.

9, the panel driving circuit chip 100 according to the fourth embodiment includes a charge pump 80 for generating driving voltages from a DC input voltage VPNL, And a register 70 for varying the gate high voltage VGH and the gate low voltage VGL generated from the gate 80.

In the fourth embodiment, the host system 60 does not transmit the clock signal CLK in the sleep-out mode every frame for a specific period, as in the prior art.

However, in the fourth embodiment, as shown in FIG. 10, when the charge pump 80 of the panel drive circuit chip 100 generates the gate high voltage VGH in the sleep-out mode higher than the setting value corresponding to the normal mode , And generates the gate-low voltage (VGL) lower than the setting value corresponding to the normal mode. Then, even if a drop of the gate high voltage VGH and the gate low voltage VGL generated from the charge pump occurs due to the clock signal CLK not being transmitted in the sleep-out mode, the gate high voltage VGH and the gate The low voltage VGL maintains the set value corresponding to the normal mode.

The fourth embodiment is similar to the first embodiment except that the setting of the register 70 capable of varying the gate high voltage VGH and the gate low voltage VGL output from the charge pump 80 is changed, Since it is possible to prevent the voltage from dropping, it is possible to improve the image quality without adding a separate circuit.

As described above, according to the present invention, in the sleep-out mode, a continuous clock signal is supplied to the charge pump to prevent the drop of the drive voltages so that the charge pump can continuously perform the switching operation. In addition, in the sleep-out mode, the gate-low voltage is generated by pumping the high-potential power supply voltage provided from the external voltage generator instead of the reference voltage generated in the charge pump in the sleep-out mode, have. Further, in the sleep-out mode, the present invention varies the set values of the gate high voltage and the gate low voltage to compensate for the drop of the gate high voltage and the gate low voltage. Therefore, the present invention can stabilize the driving voltage including the gate high voltage and the gate low voltage in the sleep-out mode, thereby preventing the deterioration of image quality due to malfunction of the driving circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

70: Register 80: Charge pump
90: clock generator

Claims (8)

A display panel;
A sleep mode having a sleep state, a normal mode for transmitting a clock signal and image data, and a sleep mode for transmitting the clock signal required for generating driving voltages in a period between the sleep mode and the normal mode A system that operates separately;
A panel drive circuit having a charge pump for driving the display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal;
Wherein the system continuously transmits the clock signal in the sleep-out mode, transmits the clock signal in the normal mode, and does not transmit the clock signal in each blank period between frames. A display panel;
A sleep mode having a sleep state, a normal mode for transmitting a clock signal and image data, and a sleep mode for transmitting the clock signal required for generating driving voltages in a period between the sleep mode and the normal mode A system that operates separately;
A panel drive circuit having a charge pump for driving the display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal;
The system does not transmit the clock signal every blank period between frames,
Wherein the panel driving circuit further comprises a clock generator for generating a dummy clock signal having the same phase as the clock signal and continuously output in the sleep-out mode,
Wherein the charge pump generates the gate high voltage and the gate low voltage using the dummy clock signal instead of the clock signal in the sleep-out mode. The method of claim 2,
Further comprising: a voltage generator for generating and outputting a high potential voltage from the DC input voltage;
The charge pump
In the normal mode, charge the dc input voltage to generate a reference voltage, and generate the gate low voltage using the reference voltage;
Wherein the controller generates the reference voltage by charge pumping the DC input voltage in the sleep-out mode, and generates the gate-low voltage using the high-potential voltage provided from the voltage generator. The method of claim 2,
The panel drive circuit further comprises a register for controlling the charge pump to vary a level of the gate high voltage and the gate low voltage generated from the charge pump;
Wherein the register changes the gate high voltage to a value higher than a setting value corresponding to the normal mode and changes the gate low voltage to a value lower than a setting value corresponding to the normal mode in the sleep-out mode, Device. A sleep mode having a sleep state, a normal mode for transmitting a clock signal and image data, and a sleep mode for transmitting the clock signal required for generating driving voltages in a period between the sleep mode and the normal mode A system that operates separately; And a charge pump for driving a display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal, the method comprising:
The system continuously transmitting the clock signal in the sleep-out mode;
Wherein the system is configured to transmit the clock signal in the normal mode but not to transmit the clock signal during each blank period between frames. A sleep mode having a sleep state, a normal mode for transmitting a clock signal and image data, and a sleep mode for transmitting the clock signal required for generating driving voltages in a period between the sleep mode and the normal mode A system that operates separately; And a charge pump for driving a display panel and generating a gate high voltage and a gate low voltage for driving the display panel using the clock signal, the method comprising:
The system transmitting the clock signal but not transmitting the clock signal every blank period between frames;
Generating a dummy clock signal having the same phase as the clock signal and being continuously output in the sleep-out mode;
And generating the gate high voltage and the gate low voltage using the dummy clock signal instead of the clock signal when the charge pump is in the sleep-out mode. The method of claim 6,
Further comprising the step of generating and outputting a high-potential voltage from a DC input voltage separately provided from the panel drive circuit;
The charge pump
In the normal mode, charge the dc input voltage to generate a reference voltage, and generate the gate low voltage using the reference voltage;
Wherein the controller generates the reference voltage by charge-pumping the DC input voltage in the sleep-out mode, and generates the gate-low voltage using the high-potential voltage provided from the voltage generator. Way. The method of claim 6,
The panel drive circuit further comprises a register for controlling the charge pump to vary a level of the gate high voltage and the gate low voltage generated from the charge pump;
Wherein the register changes the gate high voltage to a value higher than a setting value corresponding to the normal mode and changes the gate low voltage to a value lower than a setting value corresponding to the normal mode in the sleep-out mode, A method of driving a device.

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