KR102508439B1 - Display panel driving apparatus, method of driving display panel using the same and display apparatus having the same - Google Patents

Abstract

The display panel driving device includes a gate driver and a data driver. The gate driver outputs a gate signal to the gate line of the display panel. The data driver includes a plurality of data driving integrated circuits that output data signals to the data lines of the display panel, and transmits data signals whose slew rate values are adjusted based on the smallest slew rate value among slew rate values of the data signals. print out Accordingly, the display quality of the display device can be improved.

Description

DISPLAY PANEL DRIVING APPARATUS, METHOD OF DRIVING DISPLAY PANEL USING THE SAME AND DISPLAY APPARATUS HAVING THE SAME}

The present invention relates to a display device, and more particularly, to a display panel driving device, a display panel driving method using the same, and a display device including the same.

The display device includes a display panel and a display panel driving device for driving the display panel. The display panel includes gate lines, data lines, and pixels. The display panel driving device includes a gate driver, a data driver, and a timing controller.

The gate driver outputs a gate signal to the gate line to drive the gate line of the display panel. The data driver outputs a data signal to the data line to drive the data line of the display panel. The timing controller outputs a gate control signal for controlling timing of the gate driver to the gate driver and outputs a data control signal for controlling timing of the data driver to the data driver.

The data driver may include a plurality of data driving integrated circuits (ICs) that output the data signal. However, there is a problem in that display quality of the display device is degraded due to variation in charging rates of the data signals output from the data driving integrated circuits.

Accordingly, a technical problem of the present invention has been focused on in this regard, and an object of the present invention is to provide a display panel driving device capable of improving display quality of a display device.

Another object of the present invention is to provide a display panel driving method using the display panel driving device.

Another object of the present invention is to provide a display device including the display panel driving device.

A display panel driving device according to an embodiment for realizing the above object of the present invention includes a gate driving unit and a data driving unit. The gate driver outputs a gate signal to a gate line of a display panel. The data driver includes a plurality of data driving integrated circuits outputting data signals to data lines of the display panel, and the slew rate values are adjusted based on the smallest slew rate value among slew rate values of the data signals. outputs the data signals that are

In one embodiment of the present invention, slew rate values of the data signals may be controlled to be close to the smallest slew rate value.

In one embodiment of the present invention, the display panel driving apparatus may further include a slew rate controller controlling a slew rate value of the data signal.

In one embodiment of the present invention, the slew rate control unit may include: a counter unit calculating average slew rate values of the data signals output from each of the data driving integrated circuits and outputting the average slew rate values; a comparator that compares slew rate values and outputs a comparison signal, and outputs a slew rate control signal for controlling slew rate values of the data signals based on the smallest average slew rate value according to the comparison signal may include an adjustment unit.

In one embodiment of the present invention, the counter unit calculates a slew rate value of a data signal output from a first channel and a slew rate value of a data signal output from a last channel among the data signals output from the data driving integrated circuit. The average slew rate value may be output by calculating an average value.

In one embodiment of the present invention, the counter unit may calculate an average value of the data signals output from the data driving integrated circuit and output the average slew rate value.

In one embodiment of the present invention, the counter unit may calculate average slew rate values of the data signals during one frame period.

In one embodiment of the present invention, the display panel driving device may further include a timing controller outputting image data and a clock signal to the data driver, and the counter unit based on the frequency of the image data and the clock signal. The average slew rate values may be calculated using a unit time of .

In one embodiment of the present invention, when each of the data signals rises from a low level to a high level, the slew rate control unit determines a point where the data signal is X% of the high level as the lowest average slew rate. A data signal having a value can be matched to a point that is X% of the high level.

In one embodiment of the present invention, when the timing of the gate signal is changed from a first time point to a second time point earlier than the first time point, 'X' may decrease.

In one embodiment of the present invention, the slew rate control unit may include: a counter unit calculating slew rate values of the data signals output from each of the data driving integrated circuits and outputting the slew rate values; a comparison unit that compares data signals and outputs a comparison signal; and a slew rate controller that outputs a slew rate control signal for controlling slew rate values of the data signals based on the smallest slew rate value according to the comparison signal. do.

In one embodiment of the present invention, the counter unit may calculate slew rate values of the data signals during one frame period.

In one embodiment of the present invention, the display panel driving device may further include a timing controller outputting image data and a clock signal to the data driver, and the counter unit based on the frequency of the image data and the clock signal. The slew rate values may be calculated using a unit time of .

In one embodiment of the present invention, when each of the data signals rises from a low level to a high level, the slew rate control unit determines a point where the data signal is X% of the high level as the smallest slew rate value. A data signal having ? can be matched to a point that is X% of the high level.

In one embodiment of the present invention, when the timing of the gate signal is changed from a first time point to a second time point earlier than the first time point, 'X' may decrease.

In one embodiment of the present invention, the slew rate control unit may control the slew rate value of the data signal during a vertical blank period between frame periods.

In one embodiment of the present invention, the data driver may include an amplifier outputting the data signal, and the slew rate controller controls a slew rate value of the data signal by controlling a current bias applied to the amplifier. can do.

In one embodiment of the present invention, the data driver may include a charge sharing capacitor that is charged as an analog voltage by sharing a current charged in a load capacitor of the display panel, and the data driver integrated circuit outputs a target voltage. and a switch selectively connecting the amplifier and the charge sharing capacitor to the data line of the display panel.

A display panel driving method according to an embodiment for realizing the object of the present invention described above includes receiving data signals output from data driving integrated circuits, and a slew of the data signals output from each of the data driving circuits. calculating rate values, comparing the slew rate values and outputting a comparison signal, and providing a slew rate control signal for controlling a slew rate value of the data signal based on the smallest slew rate value according to the comparison signal outputting the data signal to a data line of a display panel by controlling a slew rate value of the data signal based on the smallest slew rate value according to the slew rate control signal, and outputting the data signal to a data line of the display panel; and outputting the gate signal to the line.

A display device according to an exemplary embodiment for realizing the above object of the present invention includes a display panel and a display panel driving device. The display panel displays an image and includes a gate line and a data line. The display panel driving device includes a gate driver outputting a gate signal to the gate line of the display panel and a plurality of data driving integrated circuits outputting data signals to data lines of the display panel, and and a data driver outputting the data signals whose slew rate values are adjusted based on a smallest slew rate value among slew rate values.

According to such a display panel driving device, a display panel driving method using the same, and a display device including the same, deviations in charging rates in which pixels are charged with data signals output from data driving integrated circuits can be reduced. Accordingly, the display quality of the display device can be improved.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a pixel of FIG. 1 .
FIG. 3 is a block diagram illustrating a first data driving integrated circuit of FIG. 1 .
FIG. 4 is a circuit diagram illustrating the display panel of FIG. 1 , a buffer unit, a charge sharing unit, and a switch unit of FIG. 3 .
FIG. 5 is a graph showing gate signals and data signals of FIG. 1 .
FIG. 6 is a block diagram illustrating a slew rate controller of FIG. 1 .
7 is a flowchart illustrating a display panel driving method using the display panel driving device of FIG. 1 .
8 is a block diagram illustrating a display device according to an exemplary embodiment.
9 is a circuit diagram illustrating a pixel of FIG. 8 .

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail.

Example 1

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the display device 100 according to the present exemplary embodiment includes a display panel 110, a gate driver 130, a data driver 200, a timing controller 150, a voltage provider 170, and a slew. A rate controller 400 is included.

The display panel 110 displays an image by receiving a data signal DS based on the image data DATA provided from the timing controller 150 . The display panel 110 includes gate lines GL, data lines DL, and a plurality of pixels 120 . The gate lines GL extend in a first direction D1 and are arranged in a second direction D2 perpendicular to the first direction D1. The data lines DL extend in the second direction D2 and are arranged in the first direction D1. Here, the first direction D1 may be parallel to the long side of the display panel 110 , and the second direction D2 may be parallel to the short side of the display panel 110 .

FIG. 2 is a circuit diagram illustrating the pixel 120 of FIG. 1 .

1 and 2 , the pixels 120 are defined by each of the gate lines GL and each of the data lines DL. For example, the pixel 120 includes a thin film transistor 121 electrically connected to the gate line GL and the data line DL, a liquid crystal capacitor 123 connected to the thin film transistor 121, and a storage capacitor ( 125) may be included. Accordingly, the display panel 110 may be a liquid crystal display (LCD) panel, and the display device 100 may be a liquid crystal display (LCD) device.

The gate driver 130, the data driver 200, the timing controller 150, the gamma voltage output unit 170, and the slew rate controller 400 are display panels for driving the display panel 110. It can be defined as a driving device.

The gate driver 130 generates a gate signal GS in response to a vertical start signal STV and a first clock signal CLK1 provided from the timing controller 150, and converts the gate signal GS to the first clock signal CLK1. output through the gate line GL.

The data driver 200 receives the image data DATA from the timing controller 150, generates the data signal DS based on the image data DATA, and The data signal DS is output to the data line DL in response to the horizontal start signal STH and the second clock signal CLK2 provided from . The data driver 200 may include a plurality of data driving integrated circuits 210 , 220 , 230 , and 240 that generate and output the data signal DS. For example, the data driving integrated circuits 210, 220, 230, and 240 include a first data driving integrated circuit 210, a second data driving integrated circuit 220, a third data driving integrated circuit 230, and A fourth data driving integrated circuit 240 may be included.

The first data driving integrated circuit 210, the second data driving integrated circuit 220, the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240 are the timing controller 150 A charge sharing mode signal (QCMODE) may be received from When the charge sharing mode signal QCMODE is in an active state, the first data driving integrated circuit 210, the second data driving integrated circuit 220, the third data driving integrated circuit 230 and the fourth The data driving integrated circuit 240 may be driven in a charge sharing mode, and when the charge sharing mode signal QCMODE is in an inactive state, the first data driving integrated circuit 210 and the second data driving integrated circuit ( 220), the third data driving integrated circuit 230 and the fourth data driving integrated circuit 240 may be driven in a normal mode. For example, when the charge sharing mode signal QCMODE is at a high level, the charge sharing mode signal QCMODE may be in an active state, and when the charge sharing mode signal QCMODE is at a low level, the charge sharing mode signal (QCMODE) may be in an inactive state. Alternatively, when the charge sharing mode signal QCMODE is at a low level, the charge sharing mode signal QCMODE may be in an active state, and when the charge sharing mode signal QCMODE is at a high level, the charge sharing mode signal ( QCMODE) may be in an inactive state.

The timing controller 150 receives the image data DATA and control signal CON from the outside. The control signal CON may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal CLK. The timing controller 150 generates the horizontal start signal STH using the horizontal synchronization signal Hsync and then outputs the horizontal start signal STH to the data driver 200 . Also, the timing controller 150 generates the vertical start signal STV using the vertical synchronization signal Vsync and then outputs the vertical start signal STV to the gate driver 130 . In addition, the timing controller 150 generates the first clock signal CLK1 and the second clock signal CLK2 by using the clock signal CLK, and then transmits the first clock signal CLK1 to the second clock signal CLK1. The second clock signal CLK2 is output to the gate driver 130 and the data driver 200 . The timing controller 150 further outputs the charge sharing mode signal QCMODE to the data driver 200 .

The voltage providing unit 170 generates the first analog voltage QAVDD and outputs the first analog voltage QAVDD to the data driver 200 . Also, the voltage providing unit 170 may further output a common voltage to the display panel 110 . Also, the voltage providing unit 170 may further output a gate-on voltage and a gate-off voltage used to generate the gate signal GS to the gate driver 130 .

The slew rate controller 400 receives the data signals DS from the data driver 200 . The slew rate controller 400 transmits a slew rate control signal SRCS for controlling the slew rate values of the data signals DS based on the slew rate values of the data signals DS to the data driver ( 200) output. In FIG. 1 , the slew rate controller 400 is disposed outside the timing controller 150 and the data driver 200 , but is not limited thereto. For example, the slew rate controller 400 may be included in the timing controller 150 . Alternatively, the slew rate controller 400 may be included in the data driver 200 .

FIG. 3 is a block diagram illustrating the first data driving integrated circuit 210 of FIG. 1 .

1 and 3, the first data driving integrated circuit 210 includes a shift register 310, a serial/parallel converter 320, a latch 330, a digital/analog converter 340, and a buffer unit. 350, a charge sharing unit 360 and a switch unit 370.

The shift register 310 receives the horizontal start signal STH and shifts the horizontal start signal STH to the second data driving integrated circuit 220 . In addition, the shift register 310 sequentially provides parallel data DATA1, ..., DATAk to the latch 330. Specifically, the shift register 310 sequentially outputs activation signals En1, ..., Enk to sequentially store the parallel data DATA1, ..., DATAk in the latch 330. .

The serial/parallel conversion unit 320 receives the image data DATA, converts the image data DATA into the parallel data DATA1, ..., DATAk, and converts the parallel data DATA1, .. ., DATAk) is output.

The digital/analog converter 340 converts the parallel data DATA1, ..., DATAk into analog data ADATA1, ..., ADATAk to obtain the analog data ADATA1, ..., ADATAk. output to the buffer unit 350.

The buffer unit 350 amplifies the analog data ADATA1, ..., ADATAk and outputs target voltages VTAR1, ..., VTARk. The buffer unit 350 receives the slew rate control signal SRCS. The slew rate control signal SRCS may control slew rate values of each of the target voltages VTAR1, ..., VTARk. For example, the slew rate control signal SRCS controls current biases of amplifiers included in the buffer unit 350 to obtain the slew rate of the target voltages VTAR1, ..., VTARk. values can be controlled.

The charge sharing unit 360 receives the first analog voltage QAVDD and outputs a precharge voltage VPRE.

The switch unit 370 selectively outputs the precharge voltage VPRE and the target voltages VTAR1, ..., VTARk. The switch unit 370 receives the charge sharing mode signal QCMODE and the second clock signal CLK2, and performs the precharging according to the charge sharing mode signal QCMODE and the second clock signal CLK2. The voltage VPRE and the target voltages VTAR1, ..., VTARk may be selectively output. The switch unit 370 transmits the precharge voltage VPRE and the target voltages VTAR1, ..., VTARk to data signals DS1, ..., CHk through channels CH1, ..., CHk. ., DSk). The data signals DS1, ..., DSk may be included in the data signals DS.

The configuration and function of each of the second data driving integrated circuit 220, the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240 of FIG. 1 is the first data driving integrated circuit of FIG. 3 The configuration and function of the integrated circuit 210 are substantially the same.

FIG. 4 is a circuit diagram illustrating the display panel 110 of FIG. 1 , the buffer unit 350 , the charge sharing unit 360 and the switch unit 370 of FIG. 3 .

1, 3 and 4, the display panel 110 includes a panel load resistor 111 and a panel load capacitor 113. The panel load resistor 111 and the panel load capacitor 113 may be formed on the data line DL.

The buffer unit 350 may include an amplifier 351. The amplifier 351 amplifies the analog data ADATA and outputs the target voltage VTAR. The analog data ADATA may be one of the analog data ADATA1, ..., ADATAk. The target voltage VTAR may be one of the target voltages VTAR1, ..., VTARk. The amplifier 351 receives the slew rate control signal SRCS. The amplifier 351 may control the slew rate value of the target voltage VTAR according to the slew rate control signal SRCS.

The switch unit 370 includes a switch 371. The switch 371 selectively connects the charge sharing capacitor 361 included in the output terminal of the amplifier 351 and the charge sharing unit 360 and charged with the first analog voltage QAVDD to the data line DL. ) connect to The switch 371 may selectively connect the amplifier 351 and the charge sharing capacitor 361 to the data line DL according to the charge sharing mode signal QCMODE and the second clock signal CLK2. there is. For example, when the charge sharing mode signal QCMODE is active and the second clock signal CLK2 is active, the switch 371 disconnects the charge sharing capacitor 361 and the data line DL. can be electrically connected. The switch 371 may electrically connect the charge sharing capacitor 361 and the data line DL according to the pulse width of the second clock signal CLK2. When the charge sharing mode signal QCMODE is in an inactive state or the second clock signal CLK2 is in an inactive state, the switch 371 may electrically connect the amplifier 351 and the data line DL.

The charge sharing unit 360 includes the charge sharing capacitor 361 . The charge sharing capacitor 361 includes one end selectively connected to the data line DL by the switch 371 and the other end connected to a terminal to which the second analog voltage HAVDD is applied. The second analog voltage HAVDD may be half of the first analog voltage QAVDD, and the second analog voltage HAVDD may be provided from the voltage providing unit 170 of FIG. 1 . Alternatively, the second analog voltage HAVDD may be generated using the first analog voltage QAVDD. Depending on the embodiment, the second analog voltage HAVDD may be replaced with a ground voltage.

FIG. 5 is a graph illustrating the gate signal GS and the data signals DS of FIG. 1 .

1 and 3 to 5, the data signals DS may include a g-th data signal DSg, an h-th data signal DSh, and an i-th data signal DSi. For example, the g-th data signal DSg may be output from the first data driving integrated circuit 210, and the h-th data signal DSg may be output from the second data driving integrated circuit 220. and the i-th data signal DSi may be output from the third data driving integrated circuit 230 . Also, for example, the first data driving integrated circuit 210 and the third data driving integrated circuit 230 may display a stripe pattern, and the second data driving integrated circuit 230 may display a white image or A black image can be displayed. In this case, in order to prevent temperature increase of the first data driving integrated circuit 210 and the third data driving integrated circuit 230, the first data driving integrated circuit 210 and the third data driving integrated circuit are It can be driven in the charge sharing mode. In addition, in order to prevent a decrease in the charging rate at which the pixel 120 is charged with the h-th data signal DSh output from the second data driving integrated circuit 220, the second data driving integrated circuit 220 may be driven in the normal mode.

The g-th data signal DSg rises from 0 to the first precharge voltage VPRE1 during the precharge period PC. The precharge period PC may correspond to the pulse width of the second clock signal CLK2. The g-th data signal DSg is output from 0 to the first analog voltage QAVDD charged in the charge sharing capacitor 361 of the charge sharing unit 360 during the precharge period PC. It may rise to the precharge voltage VPRE1. The g-th data signal DSg rises from the first precharge voltage VPRE1 to the target voltage VTAR during the main charging period MC after the precharging period PC.

Since the h-th data signal DSh is output from the second data driving integrated circuit 220 driven in the normal mode, the h-th data signal DSh corresponds to the pre-charge period PC and the main charge period. It rises from 0 to the target voltage VTAR without distinction of (MC).

The ith data signal DSi rises from 0 to the second precharge voltage VPRE2 during the precharge period PC. The second precharge voltage VPRE2 may be greater than the first precharge voltage VPRE1. The ith data signal DSi is transmitted from 0 to the second analog voltage QAVDD charged in the charge sharing capacitor 361 of the charge sharing unit 360 during the precharge period PC. It may rise to the precharge voltage VPRE2. The ith data signal DSi rises from the second precharge voltage VPRE2 to the target voltage VTAR during the main charging period MC after the precharge period PC.

The slew rate value of the g-th data signal DSg, the slew rate value of the h-th data signal DSh, and the slew rate value of the i-th data signal DSi are different. The slew rate value of the g-th data signal DSg may be a first value, the slew rate value of the h-th data signal DSh may be a second value greater than the first value, and the i-th data signal ( The slew rate value of DSi) may be a third value between the first value and the second value. Therefore, the slew rate value of the g-th data signal DSg is smaller than the slew rate value of each of the h-th data signal DSh and the slew rate value of the i-th data signal DSi. Here, the slew rate value of the g-th data signal DSg may be a slope between a point at which the g-th data signal DSg starts to rise and a point at which it reaches X% of the target voltage VTAR. The slew rate value of the h-th data signal DSh may be a slope between a point at which the h-th data signal DSh starts rising and a point at which it reaches X% of the target voltage VTAR. The slew rate value of the i-th data signal DSi may be a slope between a point at which the i-th data signal DSi starts to rise and a point at which it reaches X% of the target voltage VTAR. For example, 'X%' may be about 90%. 'X %' may change according to the load of the display panel 110 or the timing of the gate signal GS. Specifically, when the rising time point of the gate signal GS changes from a first time point to a second time point earlier than the first time point, 'X %' may decrease. For example, when the rising time of the gate signal GS changes from the first time point to the second time point earlier than the first time point, 'X%' may change from about 90% to about 80%. .

FIG. 6 is a block diagram illustrating the slew rate controller 400 of FIG. 1 .

Referring to FIGS. 1 and 3 to 6 , the slew rate control unit 400 includes a counter unit 410 , a comparison unit 420 and a slew rate adjustment unit 430 .

The counter unit 410 includes the data signals DS output from the first data driving integrated circuit 210, the data signals DS output from the second data driving integrated circuit 220, the The data signals DS output from the third data driving integrated circuit 230 and the data signals DS output from the fourth data driving integrated circuit 240 are received. The counter unit 410 calculates an average slew rate value (ASRV) of the data signals DS output from the first data driving integrated circuit 210 and the data output from the second data driving integrated circuit 220. an average slew rate value (ASRV) of the signals DS, an average slew rate value (ASRV) of the data signals DS output from the third data driving integrated circuit 230, and the fourth data driving integrated circuit The average slew rate values ASRV of the data signals DS outputted from 240 are calculated and the average slew rate values ASRV are output.

For example, the counter unit 410 outputs a data signal DS output from the first channel CH1 and the k-th channel CHk of the first data driving integrated circuit 210 during one frame period. ) can calculate the average slew rate value (ASRV). Also, the counter unit 410 controls the number of data signals DS output from the first channel CH1 and the k-th channel CHk of the second data driving integrated circuit 220 during one frame period. The average slew rate value (ASRV) can be calculated. In addition, the counter unit 410 controls the number of data signals DS output from the first channel CH1 and the k-th channel CHk of the third data driving integrated circuit 230 during one frame period. The average slew rate value (ASRV) can be calculated. In addition, the counter unit 410 controls the number of data signals DS output from the first channel CH1 and the k-th channel CHk of the fourth data driving integrated circuit 240 during one frame period. The average slew rate value (ASRV) can be calculated.

In contrast, the counter unit 410 outputs data signals (output from the first to kth channels CH1, ..., CHk) of the first data driving integrated circuit 210 during one frame period. An average slew rate value (ASRV) of DSs may be calculated. In addition, the counter unit 410 outputs data signals DS from the first to kth channels CH1 , ..., CHk of the second data driving integrated circuit 220 during one frame period. ) can calculate the average slew rate value (ASRV). In addition, the counter unit 410 outputs data signals DS from the first to kth channels CH1 , ..., CHk of the third data driving integrated circuit 230 during one frame period. ) can calculate the average slew rate value (ASRV). In addition, the counter unit 410 outputs data signals DS from the first to kth channels CH1, ..., CHk of the fourth data driving integrated circuit 240 during one frame period. ) can calculate the average slew rate value (ASRV).

Depending on the embodiment, the counter unit 410 may calculate slew rate values of each of the data signals DS. The counter unit 410 may calculate slew rate values of each of the data signals DS during one frame period.

The counter unit 410 may calculate the average slew rate values ASRV or the slew rate values of the data signals DS using a unit time. For example, if the frequencies of the image data DATA and the second clock signal CLK2 applied from the timing controller 150 to the data driver 200 are about 1.6 Gbps, the unit time is about 0.625 ns. can be In this case, a typical slew rate time can be about 1 us, which is about 1600 unit hours. Here, the slew rate time is, when the data signal DS rises from the low level to the high level, from the point at which the data signal DS starts to rise to a point X% of the high level It may be the time until reaching the point.

The comparison unit 420 receives the average slew rate values ASRV from the counter unit 410 . The comparator 420 compares the average slew rate values ASRV and outputs a comparison signal CS. The comparator 420 calculates the average slew rate value ASRV of the data signals DS output from the first data driving integrated circuit 210 and the average slew rate value ASRV output from the second data driving integrated circuit 220. the average slew rate value ASRV of the data signals DS, the average slew rate value ASRV of the data signals DS output from the third data driving integrated circuit 230, and the fourth data The average slew rate of the data signals DS output from the first data driving integrated circuit 210 by comparing the average slew rate value ASRV of the data signals DS output from the driving integrated circuit 240 A rate value (ASRV), the average slew rate value (ASRV) of the data signals DS output from the second data driving integrated circuit 220), and the output from the third data driving integrated circuit 230 The lowest average slew rate among the average slew rate value ASRV of the data signals DS and the average slew rate value ASRV of the data signals DS output from the fourth data driving integrated circuit 240 value can be judged. For example, the comparator 420 may include a comparator.

The comparison signal CS is applied to the first data driving integrated circuit 210, the second data driving integrated circuit 220, the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240. A data driving integrated circuit that outputs data signals DS having the smallest average slew rate value among them. Depending on the embodiment, the comparison signal CS may represent a data signal having the smallest slew rate value among the data signals DS.

The slew rate adjusting unit 430 receives the comparison signal CS from the comparing unit 420 and receives the average slew rate values ASRV from the counter unit 410 . The slew rate adjusting unit 430 adjusts the slew rate of the data signal DS output from each of the first data driving integrated circuits 210 based on the lowest average slew rate value according to the comparison signal CS. A rate value, a slew rate value of the data signal DS output from the second data driving integrated circuit 220, and a slew rate value of the data signal DS output from the third data driving integrated circuit 230 , and the slew rate control signal SRCS for controlling the slew rate value of the data signal DS output from the fourth data driving integrated circuit 240 are output.

The slew rate control signal SRCS is a slew rate value of the data signal DS output from each of the first data driving integrated circuits 210 and the data output from the second data driving integrated circuit 220 The slew rate value of the signal DS, the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and the data signal output from the fourth data driving integrated circuit 240 The slew rate value of the data signal DS output from the first data driving integrated circuit 210 so that the slew rate value of DS is close to the smallest average slew rate value, the second data driving integrated circuit ( 220), the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240 ) adjusts the slew rate value of the data signal DS output from .

When each of the data signals DS rises from a low level to a high level, the slew rate control signal SRCS determines a point at which the data signal DS is X% of the high level as the lowest average slew. A data signal having a rate value (ASRV) may coincide with a point at X% of the high level.

Depending on the embodiment, the slew rate control signal SRCS may control the slew rate values of the data signals DS based on the data signal having the smallest slew rate value. Specifically, the slew rate control signal SRCS may control the slew rate values of each of the data signals DS so that the slew rate values of each of the data signals DS are close to the smallest slew rate value. there is. More specifically, when each of the data signals DS rises from a low level to a high level, the slew rate control signal SRCS determines the point at which the data signal DS is X% of the high level. A data signal having the smallest slew rate value can be matched to a point at X% of the high level.

The slew rate control signal SRCS controls the current biases of the amplifiers included in the buffer unit 350 to obtain a slew rate value of the data signal DS output from the first data driving integrated circuit 210 , the slew rate value of the data signal DS output from the second data driving integrated circuit 220, the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and A slew rate value of the data signal DS output from the fourth data driving integrated circuit 240 may be controlled.

The slew rate adjusting unit 430 adjusts the slew rate value of the data signal DS output from the first data driving integrated circuit 210 during the vertical blank period between frame periods and the second data driving integrated circuit 220 ), the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240 A slew rate value of the data signal DS output from the controller may be controlled.

FIG. 7 is a flowchart illustrating a display panel driving method using the display panel driving device of FIG. 1 .

1 and 3 to 7 , the data signals DS output from the data driving integrated circuits 210, 220, 230, and 240 are received (step S110). Specifically, the counter unit 410 controls the data signals DS output from the first data driving integrated circuit 210 and the data signal DS output from the second data driving integrated circuit 220. , the data signals DS output from the third data driving integrated circuit 230 and the data signals DS output from the fourth data driving integrated circuit 240 are received.

The slew rate values of the data signals DS output from each of the data driving integrated circuits 210, 220, 230, and 240 are calculated (step S120). Specifically, the counter unit 410 calculates the average slew rate value ASRV of the data signals DS output from the first data driving integrated circuit 210 and the second data driving integrated circuit 220. The average slew rate value ASRV of the output data signals DS, the average slew rate value ASRV of the data signals DS output from the third data driving integrated circuit 230, and the The average slew rate values ASRV of the data signals DS output from the fourth data driving integrated circuit 240 are calculated and the average slew rate values ASRV are output.

For example, the counter unit 410 may output the data signals (output from the first channel CH1 and the k-th channel CHk of the first data driving integrated circuit 210 during one frame period). The average slew rate value (ASRV) of DSs may be calculated. In addition, the counter unit 410 controls the data signal DS output from the first channel CH1 and the k-th channel CHk of the second data driving integrated circuit 220 during one frame period. It is possible to calculate the average slew rate value (ASRV) of Also, the counter unit 410 controls the data signal DS output from the first channel CH1 and the k-th channel CHk of the third data driving integrated circuit 230 during one frame period. It is possible to calculate the average slew rate value (ASRV) of In addition, the counter unit 410 controls the data signal DS output from the first channel CH1 and the k-th channel CHk of the fourth data driving integrated circuit 240 during one frame period. It is possible to calculate the average slew rate value (ASRV) of

In contrast, the counter unit 410 outputs the data signals from the first to kth channels CH1, ..., CHk of the first data driving integrated circuit 210 during one frame period. The average slew rate value (ASRV) of (DSs) may be calculated. In addition, the counter unit 410 may output the data signals (output from the first to kth channels CH1 , ..., CHk of the second data driving integrated circuit 220 during one frame period). The average slew rate value (ASRV) of DSs may be calculated. In addition, the counter unit 410 may output the data signals (output from the first to kth channels CH1, ..., CHk of the third data driving integrated circuit 230 during one frame period). The average slew rate value (ASRV) of DSs may be calculated. In addition, the counter unit 410 outputs the data signals (output from the first to kth channels CH1, ..., CHk) of the fourth data driving integrated circuit 240 during one frame period. The average slew rate value (ASRV) of DSs may be calculated.

Depending on the embodiment, the counter unit 410 may calculate the slew rate values of each of the data signals DS. The counter unit 410 may calculate slew rate values of each of the data signals DS during one frame period.

The counter unit 410 may calculate the average slew rate values ASRV or the slew rate values of the data signals DS using the unit time. For example, if the frequencies of the image data DATA and the second clock signal CLK2 applied from the timing controller 150 to the data driver 200 are about 1.6 Gbps, the unit time is about 0.625 ns. can be In this case, the typical slew rate time may be about 1 us as about 1600 unit time.

The comparison signal CS is output by comparing the slew rate values (step S130). Specifically, the comparison unit 420 receives the average slew rate values ASRV from the counter unit 410 . The comparator 420 compares the average slew rate values ASRV and outputs the comparison signal CS. The comparator 420 calculates the average slew rate value ASRV of the data signals DS output from the first data driving integrated circuit 210 and the average slew rate value ASRV output from the second data driving integrated circuit 220. the average slew rate value ASRV of the data signals DS, the average slew rate value ASRV of the data signals DS output from the third data driving integrated circuit 230, and the fourth data The average slew rate of the data signals DS output from the first data driving integrated circuit 210 by comparing the average slew rate value ASRV of the data signals DS output from the driving integrated circuit 240 A rate value (ASRV), the average slew rate value (ASRV) of the data signals DS output from the second data driving integrated circuit 220), and the output from the third data driving integrated circuit 230 The lowest average slew rate among the average slew rate value ASRV of the data signals DS and the average slew rate value ASRV of the data signals DS output from the fourth data driving integrated circuit 240 value can be judged. For example, the comparator 420 may include a comparator.

The comparison signal CS is applied to the first data driving integrated circuit 210, the second data driving integrated circuit 220, the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240. The data driving integrated circuit outputting the data signals DS having the smallest average slew rate value among them. Depending on the embodiment, the comparison signal CS may represent a data signal having the smallest slew rate value among the data signals DS.

The data signal DS controlled by the smallest slew rate value according to the slew rate control signal SRCS is output to the data line DL of the display panel 110 (step S150). Specifically, the slew rate adjusting unit 430 receives the comparison signal CS from the comparing unit 420 and receives the average slew rate values ASRV from the counter unit 410 . The slew rate adjusting unit 430 adjusts the slew rate of the data signal DS output from each of the first data driving integrated circuits 210 based on the lowest average slew rate value according to the comparison signal CS. A rate value, a slew rate value of the data signal DS output from the second data driving integrated circuit 220, and a slew rate value of the data signal DS output from the third data driving integrated circuit 230 , and the slew rate control signal SRCS for controlling the slew rate value of the data signal DS output from the fourth data driving integrated circuit 240 are output.

The slew rate control signal SRCS is a slew rate value of the data signal DS output from each of the first data driving integrated circuits 210 and the data output from the second data driving integrated circuit 220 The slew rate value of the signal DS, the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and the data signal output from the fourth data driving integrated circuit 240 The slew rate value of the data signal DS output from the first data driving integrated circuit 210 so that the slew rate value of DS is close to the smallest average slew rate value, the second data driving integrated circuit ( 220), the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240 ) adjusts the slew rate value of the data signal DS output from .

When each of the data signals DS rises from a low level to a high level, the slew rate control signal SRCS determines a point at which the data signal DS is X% of the high level as the lowest average slew. A data signal having a rate value (ASRV) may coincide with a point at X% of the high level.

According to an embodiment, the slew rate control signal SRCS may control slew rate values of the data signals DS based on the data signal having the smallest slew rate value. Specifically, the slew rate control signal SRCS may control the slew rate values of each of the data signals DS so that the slew rate values of each of the data signals DS are close to the smallest slew rate value. there is. More specifically, when each of the data signals DS rises from a low level to a high level, the slew rate control signal SRCS determines the point at which the data signal DS is X% of the high level. A data signal having the smallest slew rate value can be matched to a point at X% of the high level.

The slew rate control signal SRCS controls the current biases of the amplifiers included in the buffer unit 350 to obtain a slew rate value of the data signal DS output from the first data driving integrated circuit 210 , the slew rate value of the data signal DS output from the second data driving integrated circuit 220, the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and A slew rate value of the data signal DS output from the fourth data driving integrated circuit 240 may be controlled.

The slew rate adjusting unit 430 adjusts the slew rate value of the data signal DS output from the first data driving integrated circuit 210 during the vertical blank period between frame periods and the second data driving integrated circuit 220 ), the slew rate value of the data signal DS output from the third data driving integrated circuit 230, and the fourth data driving integrated circuit 240 A slew rate value of the data signal DS output from the controller may be controlled.

The data driver 200 outputs the data signal DS to the data line DL in response to the horizontal start signal STH and the second clock signal CLK2 provided from the timing controller 150. do.

The gate signal GS is output to the gate line GL of the display panel 110 (step S160). Specifically, the gate driver 130 generates the gate signal GS in response to the vertical start signal STV and the first clock signal CLK1 provided from the timing controller 150, and generates the gate signal GS. A signal GS is output to the gate line GL.

According to the present exemplary embodiment, a variation in charging rates at which the pixels 120 are charged with the data signals DS output from the data driving integrated circuits 210 , 220 , 230 , and 240 may be reduced. Accordingly, display quality of the display device 100 may be improved.

Example 2

8 is a block diagram illustrating a display device according to an exemplary embodiment.

The display device 500 of FIG. 8 according to this embodiment is substantially the same as the display device 100 of FIG. 1 according to the previous embodiment except for the display panel 510 . Therefore, the same members as those in FIG. 1 are denoted by the same reference numerals, and overlapping detailed descriptions may be omitted.

Referring to FIG. 8 , the display device 500 according to the present embodiment includes the display panel 510, the gate driver 130, the data driver 200, the timing controller 150, and the voltage providing unit. 170 and the slew rate controller 400.

The display panel 510 displays an image by receiving the data signal DS based on the image data DATA provided from the timing controller 150 . The display panel 510 includes a plurality of pixels 520 .

FIG. 9 is a circuit diagram illustrating the pixel 520 of FIG. 8 .

Referring to FIGS. 8 and 9 , the pixel 520 may include a switching transistor 521 , a storage capacitor 523 , a driving transistor 525 , and an organic light emitting diode 527 . Accordingly, the display panel 510 may be an organic light emitting diode (OLED) display panel, and the display device 500 may be an organic light emitting diode (OLED) display device.

The switching transistor 521 is connected to a first electrode connected to the data line DL to receive the data signal DS, a second electrode connected to the storage capacitor 523, and the gate line GL. and a gate electrode receiving the gate signal GS. The switching transistor 521 may transmit the data signal DS provided from the data driver 200 to the storage capacitor 523 in response to the gate signal GS applied from the gate driver 130 . there is.

The storage capacitor 523 may include a first electrode connected to the high power supply voltage ELVDD and a second electrode connected to the gate electrode of the driving transistor 521 . The storage capacitor 523 may store the voltage of the data signal DS transmitted through the switching transistor 521 .

The driving transistor 525 may include a first electrode connected to the high power supply voltage ELVDD, a second electrode connected to the organic light emitting diode 527, and a gate electrode connected to the storage capacitor 523. The driving transistor 525 may be turned on or off according to the data signal DS stored in the storage capacitor 523 .

The organic light emitting diode 527 may have an anode electrode connected to the driving transistor 525 and a cathode electrode connected to the low power supply voltage ELVSS. The organic light emitting diode 527D may emit light based on a current flowing from the high power supply voltage ELVDD to the low power supply voltage ELVSS while the driving transistor 525 is turned on.

According to the present embodiment, the deviation of charging rates at which the pixels 520 are charged with the data signals DS output from the data driving integrated circuits 210 , 220 , 230 , and 240 can be reduced. Accordingly, display quality of the display device 500 may be improved.

The present invention can be applied to all electronic devices having a display device. For example, the present invention relates to televisions, computer monitors, notebooks, digital cameras, mobile phones, smart phones, tablet PCs, smart pads, PDAs, PMPs, MP3 players, navigation systems. , camcorders, portable game machines, and the like.

Although the above has been described with reference to embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand.

100, 500: display device 110, 510: display panel
120, 520: pixel 130: gate driver
150: timing control unit 170: voltage supply unit
200: data driving unit
210, 220, 230, 240: data driving integrated circuit
310: shift register 320: serial/parallel conversion unit
330: latch 340: digital/analog converter
350: buffer unit 360: charge sharing unit
370: switch unit 400: slew rate control unit
410: counter unit 420: comparison unit
430: slew rate adjustment unit

Claims (20)

a gate driver outputting a gate signal to a gate line of the display panel; and
The data signal including a plurality of data driving integrated circuits outputting data signals to data lines of the display panel, the slew rate values of which are adjusted based on the smallest slew rate value among slew rate values of the data signals A display panel driving device including a data driving unit that outputs . The display panel driving device of claim 1 , wherein slew rate values of the data signals are controlled to be close to the smallest slew rate value. According to claim 1,
and a slew rate controller controlling a slew rate value of the data signal. The method of claim 3 , wherein the slew rate control unit comprises:
a counter unit calculating average slew rate values of the data signals output from each of the data driving integrated circuits and outputting the average slew rate values;
a comparator configured to compare the average slew rate values and output a comparison signal; and
and a slew rate controller configured to output a slew rate control signal for controlling slew rate values of the data signals based on the smallest average slew rate value according to the comparison signal. The method of claim 4 , wherein the counter unit calculates an average value of a slew rate value of a data signal output from a first channel and a slew rate value of a data signal output from a last channel among the data signals output from the data driving integrated circuit. and calculating and outputting the average slew rate value. 5 . The display panel driving apparatus of claim 4 , wherein the counter unit calculates an average value of the data signals output from the data driving integrated circuit and outputs the average slew rate value. 5. The display panel driving apparatus of claim 4, wherein the counter unit calculates average slew rate values of the data signals during one frame period. According to claim 4,
Further comprising a timing controller outputting image data and a clock signal to the data driver,
The display panel driving apparatus of claim 1 , wherein the counter unit calculates the average slew rate values using a unit time based on the frequency of the image data and the clock signal. 5. The method of claim 4 , wherein when each of the data signals rises from a low level to a high level, the slew rate controller determines a point where the data signal is X% of the high level having the smallest average slew rate value. A display panel driving device characterized in that the data signal coincides with a point at X% of the high level. 10. The apparatus of claim 9, wherein 'X' decreases when the timing of the gate signal is changed from a first time point to a second time point earlier than the first time point. The method of claim 3 , wherein the slew rate control unit comprises:
a counter unit calculating slew rate values of the data signals output from each of the data driving integrated circuits and outputting the slew rate values;
a comparison unit that compares the slew rate values and outputs a comparison signal; and
and a slew rate controller outputting a slew rate control signal for controlling slew rate values of the data signals based on the smallest slew rate value according to the comparison signal. 12 . The display panel driving device of claim 11 , wherein the counter unit calculates slew rate values of the data signals during one frame period. According to claim 11,
Further comprising a timing controller outputting image data and a clock signal to the data driver,
The display panel driving apparatus of claim 1 , wherein the counter unit calculates the slew rate values using a unit time based on the frequency of the image data and the clock signal. 12. The method of claim 11 , wherein when each of the data signals rises from a low level to a high level, the slew rate controller sets a point at which the data signal is X% of the high level as the data having the smallest slew rate value. A display panel driving device characterized in that a signal coincides with a point at X% of the high level. 15. The apparatus of claim 14, wherein 'X' decreases when the timing of the gate signal is changed from a first time point to a second time point earlier than the first time point. 4 . The display panel driving apparatus of claim 3 , wherein the slew rate controller controls a slew rate value of the data signal during a vertical blank period between frame periods. The method of claim 3, wherein the data driver comprises an amplifier outputting the data signal,
The display panel driving apparatus of claim 1 , wherein the slew rate controller controls a slew rate value of the data signal by controlling a current bias applied to the amplifier. The method of claim 1 , wherein the data driver includes a charge sharing capacitor that is charged as an analog voltage by sharing a current charged in a load capacitor of the display panel,
The display panel driving apparatus of claim 1 , wherein the data driving integrated circuit includes an amplifier outputting a target voltage, and a switch selectively connecting the amplifier and the charge sharing capacitor to the data line of the display panel. receiving data signals output from data driving integrated circuits;
calculating slew rate values of the data signals output from each of the data driving integrated circuits;
comparing the slew rate values and outputting a comparison signal;
outputting a slew rate control signal for controlling a slew rate value of the data signal based on the smallest slew rate value according to the comparison signal;
controlling a slew rate value of the data signal based on the smallest slew rate value according to the slew rate control signal and outputting the data signal to a data line of a display panel; and
and outputting a gate signal to a gate line of the display panel. a display panel that displays an image and includes a gate line and a data line; and
a gate driver outputting a gate signal to the gate line of the display panel, and a plurality of data driving integrated circuits outputting data signals to data lines of the display panel, wherein slew rate values of the data signals are the smallest A display device comprising a display panel driving device including a data driver outputting the data signals of which the slew rate values are adjusted based on the slew rate value.

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