KR20150077183A - Circuit for Controlling a Memory and LCD having the Same - Google Patents

Abstract

The present invention relates to a memory control circuit. According to the present invention, the memory control circuit comprises: a dropdown regulator for outputting a high level voltage to a writing protective terminal of a memory when receiving a first input voltage, and outputting a low level voltage to the reading protective terminal when receiving a second input voltage; and a zener diode for outputting a breakdown voltage to a VCC terminal of the memory when receiving the first input voltage, and outputting the second input voltage to the VCC terminal by receiving the second input voltage.

Description

[0001] The present invention relates to a memory control circuit and a liquid crystal display including the same,

The present invention relates to a memory control circuit and a liquid crystal display including the same.

2. Description of the Related Art Liquid crystal display devices are one of the most widely used flat panel display devices, and include two substrates on which pixel electrodes and common electrodes are formed, and a liquid crystal layer between two substrates. Such a liquid crystal display determines orientation of liquid crystal molecules in a liquid crystal layer according to an electric field generated by a voltage applied to an electrode, and controls the polarization of incident light to display an image. The liquid crystal display device is advantageous for moving picture display and has a high contrast ratio. Therefore, the liquid crystal display device can be replaced with a cathode ray tube (CRT) instead of a display device .

The liquid crystal display device includes an EEPROM capable of reading model information such as resolution and timing at the time of booting the system, and transmitting the read model information to the liquid crystal driving circuit. The EEPROM is a memory capable of reading and writing. However, in the manufacturing process of the liquid crystal display device, the WP (Write Protection) function of the EEPROM is activated in the state of a liquid crystal module (LCM) in which a liquid crystal panel, a drive circuit, The write function is inhibited.

If the data of the EEPROM is changed while the liquid crystal module is manufactured, it is troublesome to remove the cover shield and float the resistor connected to the WP terminal.

* Related Prior Art

Korean Patent Laid-Open No. 10-2012-0108438, entitled: RESET CIRCUIT AND LIQUID CRYSTAL DISPLAY

SUMMARY OF THE INVENTION The present invention provides a memory control circuit and a liquid crystal display device including the memory control circuit.

The memory control circuit according to the present invention outputs a high level voltage to the write protection terminal of the memory when the first input voltage is supplied and a drop down regulator; And a zener diode for outputting a breakdown voltage to the VCC terminal of the memory when the first input voltage is provided and a second input voltage to the VCC terminal when the second input voltage is provided.

The present invention can selectively activate the write protection function of the memory by providing an input voltage of a different voltage level to the memory. Therefore, the present invention can easily change the data of the memory without troublesome work.

1 is a view showing a liquid crystal display device according to the present invention.
Figure 2 shows a memory and memory control circuit according to the present invention.
3 is a peripheral circuit diagram of a ROM-writer for changing data in a memory.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a view showing a liquid crystal display device of the present invention.

1, a liquid crystal display device according to the present invention includes a liquid crystal panel 11, a gate driver 11a, a data driver 11b, a timing controller 23, a memory 25, and a memory control circuit 27 Respectively.

The liquid crystal panel 11 has a matrix of pixel regions in which a plurality of gate lines G and data lines D are arranged in a direction perpendicular to each other and thin film transistors And a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode arranged between the pixel electrode and the liquid crystal. The TFT supplies a data voltage from each data line D to the pixel electrode in response to a scan pulse from each gate line G. [ The liquid crystal capacitor Clc charges the difference voltage between the data voltage supplied to the pixel electrode and the reference common voltage supplied to the common electrode and varies the arrangement of the liquid crystal molecules according to the difference voltage to adjust the light transmittance to express the luminance . The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied.

The timing controller 23 reads the data stored in the memory 25 and outputs an operation signal for operating the DC-DC converter 24 and various control signals for driving the liquid crystal display panel. At this time, the timing controller 23 inputs the input / output control clock CLK to the memory 25 to receive driving information and image data modulation information of the liquid crystal panel 11, and outputs drive information and image data modulation information The gate driver 11a and the data driver 11b.

The DC-DC converter 24 receives the voltage from the system through the connector 22 and outputs the driving voltages Vcc and Vdd and outputs the gate low voltage signal VGL and the gate high voltage signal VGL in accordance with the operation signal of the timing controller 23. [ (VGH).

The gate driver 11a receives the gate high voltage signal VGH and the gate low voltage signal VGL from the DC-DC converter 24 according to the operation signal of the timing controller 23 to generate a scan pulse, Are sequentially supplied to the respective gate lines (G) of the panel (11).

The data driver 11b receives the corrected video signal which is a digital signal from the timing controller 23 and converts the corrected video signal into a corrected data signal which is an analog signal and supplies the corrected data signal to each data line D of the liquid crystal display panel 11 .

The memory 25 stores the size of the liquid crystal panel 11, resolution conversion information, image data conversion information, driving frequency of the timing controller 23, and driving timing information. When the input / output control clock is input, the memory 25 supplies the stored driving information, image data modulation information, and the like to the timing controller 23.

The memory 25 may be an EEPROM (Electrically Erasable Programmable Read Only Memory) or the like. The EEPROM is a memory element in which data is stored even when the power is turned off, and transmits and receives data to and from the timing controller 23 through the serial communication means of the I 2 C bus. I2C is a 2-wire serial communication interface, a method of data communication between an integrated circuit consisting of a serial data line (SDA) and a serial clock line (SCL).

 The memory control circuit 27 activates or deactivates the write protection function of the memory 25 according to the input voltage.

2 is a diagram showing a memory 25 and a memory control circuit 27. Fig. The memory 25 and the memory control circuit 27 will now be described with reference to FIG.

The memory 25 includes a plurality of terminals. A0 terminal (2), A1 terminal (3) and A2 terminal (4) are for EEPROM Address setting for I2C communication. The GND terminal (7) is connected to the ground. The SDA terminal 6 and the SCL terminal 5 receive the clock signal (CLK) and the data signal (DATA) signal for I2C communication.

The WP terminal 1 is a write protection terminal, and when the high level voltage is supplied, the write protection function of the memory 25 is activated to enable the read function of the memory 25 only. The WP terminal 1 does not activate the write protection function when the low level voltage is provided, thereby enabling the read and write functions of the memory 25. In particular, the WP terminal 1 is connected to the output terminal of the drop-down regulator 31 of the memory control circuit 27, and is selectively provided with the output voltage of the drop-down regulator 31 according to the input voltage.

The VCC terminal 8 is supplied with an input voltage as a power source. Particularly, the VCC terminal 8 is connected to the Zener diode ZD of the memory control circuit 27 and is provided with the breakdown voltage of the Zener diode ZD or the second input voltages Vin1 and Vin2.

The memory control circuit 27 includes a drop-down regulator 31, a zener diode ZD and first and second pull-up resistors R1 and R2 and a stabilization resistor Rlimit.

The first pull-up resistor R1 is for maintaining a high level of the serial clock line SCL between the driving power supply Vcc and the serial clock line SCL and the second pull-up resistor R3 is for driving the driving power supply Vcc And for maintaining the serial data line SDA at a high level between the serial data lines SDA. The stabilization resistor (Rlimit) is for stabilizing the circuit by blocking the overcurrent.

The memory control circuit 27 is selectively provided with the first and second input voltages Vin1 and Vin2 through the input voltage line VIN. The first and second input voltages Vin1 and Vin2 have different voltage levels. The first input voltage Vin1 is set to a voltage capable of operating the drop down regulator 31 and the second input voltage is set to a voltage capable of operating the memory 25. [ For example, the first input voltage may be set to a range of 4.5V to 5.5V, and the second input voltage may be set to 1.8V.

The drop down regulator 31 is formed between the input power supply VIN and the WP terminal 1 and outputs the operation voltage only when the input voltage applied through the input power supply VIN is equal to or larger than the operation voltage magnitude do. If the drop-down regulator 31 does not provide an output voltage to the WP terminal 1 if the input voltage is below the operating voltage. That is, the drop-down regulator 31 selectively outputs the operation voltage according to the first and second input voltages Vin1 and Vin2. At this time, the operating voltage is set to a voltage value capable of activating the WP terminal 1 of the memory 25. [ The drop-down regulator 31 may be set to a voltage smaller than the first input voltage Vin1 and higher than the second input voltage Vin2 in order to selectively output the output voltage according to the input voltage. For example, the operating voltage of the drop-down regulator 31 may be set to 3.3V. The drop-down regulator 31 can use an LDO (Low Drop Output).

A zener diode (ZD) is formed between the input power supply (VIN) and the VCC terminal, and the anode electrode is grounded. The Zener diode ZD is supplied with the first and second input voltages Vin1 and Vin2 flowing through the input power supply VIN and passing through the stabilization resistor Rlimit and outputs a specific voltage. The Zener diode (ZD) outputs a breakdown voltage value as an output voltage when a voltage higher than the breakdown voltage is supplied to the input voltage. The Zener diode ZD outputs a voltage of the same magnitude as the input voltage to the output voltage when a voltage in the reverse range of the Zener diode ZD is supplied as an input voltage. That is, the Zener diode ZD outputs a constant current of the breakdown voltage or outputs the input voltage as it is according to the first and second input voltages Vin1 and Vin2. In particular, the Zener diode ZD is reverse-biased in the range of the second input voltage Vin2 to directly transmit the second input voltage Vin2 to the VCC terminal 8 when the second input voltage Vin2 is received. ) Region can be used. For example, the Zener diode ZD can use a breakdown voltage of 3.3V so as to have a reverse region at a voltage of 1.8V.

The operation of the memory control circuit 27 will be described below.

The memory control circuit 27 is supplied with the first input voltage Vin of 5 V or the second input voltages Vin1 and Vin2 of 1.8 V through the input power supply VIN.

When the first input voltage Vin1 is provided, the drop-down regulator 31 and the Zener diode ZD are supplied with the 5V voltage corresponding to the first input voltage Vin1.

Since the breakdown voltage of the Zener diode ZD is 3.3 V, the Zener diode ZD receives a voltage of 5 V as an input voltage and outputs 3.3 V as an output voltage. That is, the Zener diode ZD provides a voltage of 3.3 V to the VCC terminal 8 of the memory 25. [

The drop-down regulator 31 receives the first input voltage Vin1, which is higher than the operation voltage, as the input voltage because the operation voltage is 3.3V, and outputs a voltage of 3.3V corresponding to the operation voltage as the output voltage. In other words, the drop-down regulator 31 provides a voltage of 3.3 V to the WP terminal 1 of the memory 25.

As a result, when the first input voltage Vin1 of 5 V is supplied from the input power supply VIN, the VCC terminal 8 and WP terminal 1 of the memory 25 are supplied with a voltage of 3.3V. Accordingly, the circuit of the memory 25 operates, and the memory 25 operates in the write protection mode, in particular, since the WP terminal 1 is supplied with the high level signal capable of activating the write protection function. That is, the memory 25 is ready for a read operation only.

When the second input voltage Vin2 is provided, the drop-down regulator 31 and the Zener diode ZD are supplied with a 1.8V voltage corresponding to the second input voltage Vin2.

Since the zener diode ZD is a reverse region when the input voltage is 1.8 V, the input voltage value 1.8 V is output as the output voltage. That is, the Zener diode ZD provides a voltage of 1.8 V to the VCC terminal of the memory 25. [

The drop-down regulator 31 outputs a voltage of 0V as an output voltage when the second input voltage Vin2, which is lower than the operation voltage, is applied as the input voltage because the operation voltage is 3.3V. That is, the drop-down regulator 31 provides a voltage of 0 V to the WP terminal 1 of the memory 25. [

The VCC terminal 8 of the memory 25 is supplied with a voltage of 1.8 V and the WP terminal 1 is supplied with a voltage of 0 V ≪ / RTI > The memory 25 starts to operate because it is supplied with a voltage of 1.8V which is the size larger than the driving voltage. Since the WP terminal 1 of the memory 25 receives a low level voltage, the write / press function is not activated. That is, the memory 25 can perform a write operation in addition to the read operation by using a ROM-writer capable of performing the write function of the memory 25. [

3 is a diagram showing an example of the ROM-writer 50 and peripheral circuits.

When the write operation of the memory control circuit 27 is performed, the read operation of the memory 25 can be performed by using a ROM-writer circuit pulled up to 1.8 V as shown in FIG.

Although the present invention is described as an embodiment of a liquid crystal display device, the memory control circuit may be applied to an organic light emitting display (OLED), a plasma display panel (PDP), and an electrophoresis display device EPD) or the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

11: liquid crystal panel 11a: gate driver
11b: Data driver 22: Connector
23: Timing controller 24: DC-DC converter
25: memory 30: memory control circuit

Claims (6)

A drop down regulator for outputting a high level voltage to the write protection terminal when the first input voltage is provided and a low level voltage to the write protection terminal when the second input voltage is provided; And
And a Zener diode for outputting the second input voltage to the VCC terminal upon receiving the second input voltage, and outputting the second input voltage to the VCC terminal when the first input voltage is received, .
The method according to claim 1,
Wherein the drop-down regulator utilizes a low dropout output (LDO) having a voltage that is less than the first input voltage and greater than the second input voltage as an operating voltage.
3. The method of claim 2,
Wherein the operating voltage is a high level voltage that is large enough to activate a write function of the memory.
The method according to claim 1,
And the zener diode is a reverse region in the range of the second input voltage.
The method according to claim 1,
Wherein the second input voltage has a magnitude greater than a drive voltage of the memory.
A memory for storing drive information, image data modulation information, and the like, and supplying the stored drive information and image data modulation information to a timing controller; And
A drop down regulator for outputting a high level voltage to the write protection terminal of the memory when the first input voltage is provided and a low level voltage to the write protection terminal when the second input voltage is provided, And a Zener diode for receiving a second input voltage and outputting the second input voltage to the VCC terminal, and a memory control circuit for outputting a breakdown voltage to the VCC terminal of the memory and receiving the second input voltage and outputting the second input voltage to the VCC terminal.

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