KR20150077169A - Organic light emitting diode device and method of fabricating the same - Google Patents

Abstract

The present invention relates to an organic light emitting diode display device which includes a substrate which includes first to fourth pixels arranged in two rows and two columns, first to fourth emission transistors which are formed on the first to fourth pixels, respectively, a first electrode of a first organic light emitting diode which is formed on the first pixel and is connected to the first emission transistor, a second electrode of a second organic light emitting diode which is formed on the second pixel and is connected to the second emission transistor, a third electrode of a third organic light emitting diode which is formed on the fourth pixel and is connected to the third emission transistor, a fourth electrode of a fourth organic light emitting diode which is formed on the third pixel and is connected to the fourth emission transistor, a first storage capacitor which the first pixel and the second pixel share, and a second storage capacitor which the third pixel and the fourth pixel share. Thereby, the present invention performs the high resolution of the organic light emitting diode display device and secures the capacitance at the same time. Also, image quality is improved by the driving with a dot interlace method.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display device and a method of manufacturing the same.

The present invention relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode having a display panel of high resolution and high definition (ppi) and a method of manufacturing the same.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as organic light emitting diode (OLED) devices have been utilized.

The dual organic light emitting diode display device has advantages of high response speed, excellent luminous efficiency, luminance and viewing angle by using a self-luminous element which emits light by itself.

Such an organic light emitting diode display device has an organic light emitting diode as a self-luminous element. The organic light emitting diode has organic compound layers (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting diode display device arranges the pixels including the organic light emitting diode in a matrix form and controls the brightness of the pixels selected by the gate signal according to the gray level of the video data.

1 is an equivalent circuit diagram for one pixel in an organic light emitting diode display. 1, a pixel of an organic light emitting diode display device includes an organic light emitting diode E, a gate line GL and a data line DL intersecting with each other, a switching transistor ST, a driving transistor DT, (Cst).

The switching transistor ST is turned on in response to a scan signal from the gate line GL to thereby apply the data voltage from the data line DL to the gate electrode of the driving transistor DT. The driving transistor DT controls the amount of current flowing to the organic light emitting diode E according to the difference Vg-s between the gate potential Vg of the gate electrode and the source potential Vs of the source electrode. The storage capacitor Cst maintains the gate potential Vg of the driving transistor DT constant for one frame. The organic light emitting diode E is connected between the drain electrode of the driving transceiver DT and the ground voltage source Vcc.

The current control capability of the driving transistor described above is greatly affected by the threshold voltage of the driving transistor.

In an organic light emitting diode display device that forms a driving transistor by LTPS (Low Temperature Poly Silicon), a threshold voltage deviation of a driving transistor between pixels occurs due to an ELA (Excimer Laser Annealing) process. On the other hand, in an organic light emitting diode display device which forms a driving transistor by a-Si (Amorphous Silicon), deterioration of the driving transistor occurs due to panel driving, and a shift of a threshold voltage occurs.

Therefore, correcting the current drive control deviation of the pixel-by-pixel drive transistor is an important factor in improving the picture quality of the display device. However, in order to accomplish this, a large number of switching elements and capacitors must be formed in one pixel, which results in an increase in the size of the pixel, and therefore, there are many restrictions in manufacturing a high-resolution panel.

Particularly, the size of the pixel is reduced as the display device becomes a high-resolution display, so that the switching element and the capacitor can not be formed in one pixel. Particularly, a capacitor needs to secure a certain electrostatic capacity in order to drive a display device. However, in order to secure a capacitance, a certain area or more is necessarily required.

That is, the conventional organic light emitting diode display device is not suitable for realizing a high-resolution display device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an organic light emitting diode display device capable of securing a capacitance and realizing a high resolution.

In order to achieve the above object, the present invention provides a liquid crystal display comprising: a substrate including first to fourth pixels arranged in two rows and two columns; First to fourth emissive transistors formed in the first to fourth pixels, respectively; A first electrode of a first organic light emitting diode formed in the first pixel and connected to the first emission transistor; A second electrode of a second organic light emitting diode formed on the second pixel and connected to the second emission transistor; A third electrode of the third light emitting diode formed in the fourth pixel and connected to the third emission transistor; A fourth electrode of a fourth light emitting diode formed in the third pixel and connected to the fourth emission transistor; A first storage capacitor shared by the first and second pixels; And a second storage capacitor shared by the third and fourth pixels.

A first switching transistor and a first driving transistor formed in the first pixel; A second switching transistor and a second driving transistor formed in the second pixel; A third switching transistor and a third driving transistor formed in the third pixel; And a fourth switching transistor and a fourth driving transistor formed in the fourth pixel.

Both ends of the first storage capacitor are connected to the first and second driving transistors, respectively, and both ends of the second storage capacitor are connected to the third and fourth driving transistors, respectively.

The first organic light emitting diode may further include a first light emitting layer and a fifth electrode sequentially formed on the first electrode, and the second light emitting diode may include a second light emitting layer sequentially formed on the second electrode, And a sixth electrode, wherein the third light emitting diode further includes a third light emitting layer and a seventh electrode sequentially formed on the third electrode, wherein the fourth light emitting diode includes a fourth electrode Emitting layer and an eighth electrode sequentially formed on the first electrode.

The above-described invention is characterized in that the first and fourth pixels are driven during a first half frame, and the second and third pixels are driven during a second half frame.

In order to achieve the above object, the present invention provides a liquid crystal display comprising: a substrate including first to sixth pixels arranged in three rows and two columns at the top; and seventh to twelfth pixels arranged in two rows in three rows at the bottom; First to twelfth emission transistors formed in the first to twelfth pixels, respectively; A first electrode of a first organic light emitting diode formed in the second pixel and connected to the second emission transistor; A second electrode of a second organic light emitting diode formed in the third pixel and connected to the third emission transistor; A third electrode of the third organic light emitting diode formed in the fifth pixel and connected to the sixth emission transistor; A fourth electrode of a fourth organic light emitting diode formed in the sixth pixel and connected to the fifth emission transistor; A fifth electrode of a fifth organic light emitting diode formed in the seventh pixel and connected to the seventh emission transistor; A sixth electrode of the sixth organic light emitting diode formed in the eighth pixel and connected to the eighth emission transistor; A seventh electrode of the seventh organic light emitting diode formed in the tenth pixel and connected to the eleventh emission transistor; An eighth electrode of an eighth organic light emitting diode formed in the eleventh pixel and connected to the amplification transistor; A first storage capacitor shared by the first and second pixels; A second storage capacitor shared by the fourth and fifth pixels; A third storage capacitor shared by the eighth and ninth pixels; And a fourth storage capacitor shared by the eleventh and twelfth pixels.

A first switching transistor and a first driving transistor formed in the first pixel; A second switching transistor and a second driving transistor formed in the second pixel; A third switching transistor and a third driving transistor formed in the third pixel; A fourth switching transistor and a fourth driving transistor formed in the fourth pixel; A fifth switching transistor and a fifth driving transistor formed in the fifth pixel; A sixth switching transistor and a sixth driving transistor formed in the sixth pixel; A seventh switching transistor and a seventh driving transistor formed in the seventh pixel; An eighth switching transistor and an eighth driving transistor formed in the eighth pixel; An eighth switching transistor and an eighth driving transistor formed in the eighth pixel; A ninth switching transistor and a ninth driving transistor formed in the ninth pixel; A tenth switching transistor and a tenth driving transistor formed in the tenth pixel; An eleventh switching transistor and an eleventh driving transistor formed in the eleventh pixel; And a twelfth switching transistor and a twelfth driving transistor formed in the twelfth pixel.

Wherein both ends of the first storage capacitor are respectively connected to the first and second driving transistors, both ends of the second storage capacitor are respectively connected to the fourth and fifth driving transistors, and both ends of the third storage capacitor are connected to the first and second driving transistors, Respectively, and the both ends of the fourth storage capacitor are connected to the eleventh and twelfth driving transistors, respectively. The first, fourth, ninth, and twelfth pixels are dummy regions.

Wherein the second and sixth pixels, the seventh and eleventh pixels are driven during a first half frame, and the third and fifth pixels, the eighth and tenth pixels are driven during a second half frame. do.

As described above, the organic light emitting diode display device can have a high resolution while securing the electrostatic capacity of the present invention.

In addition, it is driven by the dot interlace method, which has the effect of improving image quality.

1 is a circuit diagram of one pixel of a general organic light emitting device.
FIG. 2 is a circuit diagram of a pixel of an organic light emitting diode display according to an embodiment of the present invention, which is an equivalent circuit diagram for two sub-pixels sharing one capacitor.
3 is a plan view schematically showing an organic light emitting diode display device according to an embodiment of the present invention.
Fig. 4 is a cross-sectional view taken along line III-III in Fig. 3; Fig.
5 is a cross-sectional view taken along line IV-IV in Fig.
6 and 7 are cross-sectional views of a transistor in an organic light emitting diode according to an embodiment of the present invention.
8 is a photograph showing an image output of one frame of the organic light emitting diode display according to the embodiment of the present invention.
9 is a plan view schematically showing an organic light emitting diode display device according to another embodiment of the present invention.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of a pixel of an organic light emitting diode display according to an embodiment of the present invention, which is an equivalent circuit diagram for two sub-pixels sharing one capacitor.

2, the first sub-pixel SP1 includes first to fifth transistors T1, T2, T3, T4 and T5 and a first organic light emitting diode E1, The pixel SP2 includes a sixth transistor to a tenth transistor T6, T7, T8, T9 and T10 and a second organic light emitting diode E. The pixel SP2 includes a first sub-pixel SP1 and a second sub- Are connected to share the storage capacitor Cst. Here, it is assumed that the first to tenth transistors T1 to T10 are P-type transistors. The N-type transistor may be used as the first to tenth transistors T1 to T10. Further, a P-type transistor may be used for a part of the first to tenth transistors T1 to T10 and an N Type transistors can be used.

The gate electrode of the first transistor T1 may be connected to the first scan line SL1 and the source electrode of the first transistor T1 may be coupled to the data line DL. The drain electrode of the first transistor T1 may be connected to the first electrode of the storage capacitor Cst. Here, the contact point between the first transistor T1 and the storage capacitor Cst is referred to as a first node N1.

At this time, the first transistor T1 is turned on or off according to the first scan signal transmitted from the first scan line SL1, and the reference voltage or data applied to the turn- And supplies a signal to the first node N1.

A gate electrode of the second transistor T2 (switching transistor) may be connected to the first power supply line PTL1, and a source electrode thereof may be coupled to the high potential power supply line VDD. The drain electrode of the second transistor T2 may be connected to the first electrode of the storage capacitor Cst.

At this time, the second transistor T2 is turned on or off according to the first power supply control signal transmitted from the first power supply line PTL1, and the second transistor T2 is turned on at the high-potential power supply line VDD And supplies the high potential power to the first node N1.

The gate electrode of the third transistor T3 (switching transistor) may be connected to the first sensing wiring SEN1, and the source electrode thereof may be connected to the second electrode of the storage capacitor Cst. The drain electrode of the third transistor T3 may be connected between the drain electrode of the fourth transistor T4 and the source electrode of the fifth transistor T5. Here, the contact between the third transistor T3 and the storage capacitor Cst is referred to as a second node N2, and the contact between the third transistor T3, the fourth transistor T4, and the fifth transistor T5 3 node (N3).

At this time, the third transistor T3 is turned on or off according to the first threshold voltage detection control signal transmitted from the first sensing wiring SEN1, and the second node N2 and the third The node N3 is connected, and the gate electrode and the drain electrode of the fourth transistor T4 are connected to each other. In other words, the third transistor T3 controls the fourth transistor T4 to have a circuit diode form for detecting the threshold voltage of the fourth transistor T4.

The gate electrode of the fourth transistor T4 (driving transistor) may be connected to the second node N2, and the source electrode thereof may be connected to the high potential power supply line VDD. The drain electrode of the fourth transistor T4 may be connected to the third node N3.

 At this time, the fourth transistor T4 is controlled according to a signal applied to the second node N2, and the fourth transistor T4 is turned off from the high potential power supply line VDD according to the magnitude of the signal applied to the second node N2. Thereby adjusting the amount of the driving current flowing to the wiring VSS.

A gate electrode of the fifth transistor T5 (emission transistor) may be connected to the first emission control line EL1, and a source electrode thereof may be coupled to the third node N3. The drain electrode of the fifth transistor T5 may be connected to the first electrode of the first organic light emitting diode E1.

At this time, the fifth transistor T5 is turned on or off according to the first emission control signal transmitted from the first emission control line EL1, and the third node N3 and the first Thereby electrically connecting the first electrodes of the light emitting diode E1. That is, the fifth transistor T5 transfers the driving current to the first organic light emitting diode E1, which is under the control of the fourth transistor T4.

The first electrode of the first organic light emitting diode E1 may be connected to the source electrode of the fifth transistor T5 and the second electrode may be connected to the low potential power supply line VSS. In this case, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode.

The gate electrode of the sixth transistor T6 (switching transistor) may be connected to the second scan line SL2, and the source electrode thereof may be connected to the data line DL. The drain electrode of the sixth transistor T6 may be connected to the second node N2.

At this time, the sixth transistor T6 is turned on or off according to the second scan signal transmitted from the second scan line SL2, and the reference voltage or data applied to the turn- And supplies a signal to the second node N2.

The gate electrode of the seventh transistor T7 (switching transistor) may be connected to the second power supply line PTL2, and the source electrode thereof may be connected to the high potential power supply line VDD. The drain electrode of the seventh transistor T7 may be connected to the second electrode of the storage capacitor Cst.

At this time, the seventh transistor T7 is turned on or off according to a second power supply control signal transmitted from the second power supply line PTL2, and the seventh transistor T7 is turned on at the high potential power supply line VDD And supplies the high potential power to the second node N2.

The gate electrode of the eighth transistor T8 (switching transistor) may be connected to the second sensing wiring SEN2, and the source electrode thereof may be connected to the first node N1 of the storage capacitor Cst. The drain electrode of the eighth transistor T8 may be connected between the drain electrode of the ninth transistor T9 and the source electrode of the tenth transistor T10. Here, the contact point of the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 is referred to as a fourth node N4.

At this time, the eighth transistor T8 (switching transistor) is turned on or off according to the second threshold voltage detection control signal transmitted from the second sensing wiring SEN2, and the first node N1 is turned on, And the fourth node N4, and the gate electrode and the drain electrode of the ninth transistor T9 are connected to each other. In other words, the eighth transistor T8 controls the ninth transistor T9 to have a circuit diode form for detecting the threshold voltage of the ninth transistor T9.

A gate electrode of the ninth transistor T9 (driving transistor) may be connected to the first node N1, and a source electrode thereof may be connected to the high potential power supply line VDD. And the drain electrode of the ninth transistor T9 may be connected to the fourth node N4.

 At this time, the ninth transistor T9 is controlled according to a signal applied to the first node N1, and the ninth transistor T9 is turned off from the high potential power supply line VDD according to the magnitude of the signal applied to the first node N1. Thereby adjusting the amount of the driving current flowing to the wiring VSS.

The gate electrode of the tenth transistor (T10, emission transistor) may be connected to the second emission control line EL2, and the source electrode may be connected to the fourth node N4. The drain electrode of the tenth transistor T10 may be connected to the first electrode of the second organic light emitting diode E2.

At this time, the tenth transistor T10 is turned on or off according to the emission control signal transmitted from the second emission control line EL2, and the fourth node N4 and the second organic light emitting diode And electrically connects the first electrodes of the second electrode E2. That is, the tenth transistor T10 transmits a drive current, which is under the control of the ninth transistor T9, to the second organic light emitting diode E2.

The first electrode of the second organic light emitting diode E2 may be connected to the source electrode of the tenth transistor T10 and the second electrode may be connected to the low potential power supply line VSS. In this case, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode.

And the storage capacitor Cst may be connected between the first node N1 and the second node N2.

Hereinafter, the functions of the above-described components will be described in detail.

The first power supply control signal is applied through the first power supply line PTL1 during the first time period (e.g., the initialization period) of the first sub-pixel SP1 and the second power supply control signal is applied through the second scan line SL2 A scan signal is applied, and a reference voltage Vref is applied to the data line DL.

The second transistor T2 and the sixth transistor T6 are turned on and the remaining transistors are all turned off and the reference voltage Vref from the data line DL is turned on, T2 to the second node N2. Also, the high potential power from the high potential power supply line VDD is applied to the first node N1 through the second transistor T2 turned on. Accordingly, the reference voltage Vref and the high potential power are applied to both ends of the storage capacitor Cst, respectively, and a voltage corresponding to the difference between the high potential power supply and the reference voltage Vref is stored in the storage capacitor Cst. I.e. initialized.

During a second time period (for example, a sensing period) of the first sub-pixel SP1, a first scan signal is applied through the first scan line SL1, a first scan signal is applied through the first sense line SEN1, A threshold voltage detection control signal is applied and a data signal corresponding to the data voltage Vdata is applied to the data line DL. At this time, the remaining lines are in a logic low state.

Accordingly, the first transistor T1 and the third transistor T are turned on, the fourth transistor T is kept turned on for a while and then turned off, and all the remaining transistors are turned off .

In other words, when the voltage of the first node N1 rises due to the application of the data signal to the first node N1 by the turned-on first transistor T1, by the storage capacitor Cst, The voltage of the second node N2 also rises. Thus, the fourth transistor T4 is turned on and the high potential driving voltage VDD can be applied to the second node N2 through the third transistor T3 and the fourth transistor T4.

Then, when the voltage of the second node N2 begins to rise and becomes the voltage corresponding to the threshold voltage, the fourth transistor T4 is turned off. At this time, a voltage corresponding to the sum of the data signal and the threshold voltage is stored in the storage capacitor Cst.

Therefore, the threshold voltage of the fourth transistor T4 is detected and stored in the storage capacitor Cst.

During the third time period (for example, the light emitting period) of the first sub-pixel SP1, the first power supply control signal is applied through the first power supply line PTl1 and the first light emitting control line EL1 is turned on The first emission control signal is applied. A reference voltage and a data signal necessary for the first sub-pixel SP1 may be applied to the data line DL. At this time, the remaining lines are in a logic low state.

The fifth transistor T5 is turned on and the remaining transistors are turned off and the fifth transistor T5 is turned on and the fifth transistor T5 is turned off. Cst and supplies the generated driving current to the first organic light emitting diode E1 through the fifth transistor T5 which is turned on. Then, the first organic light emitting diode E1 emits light according to the magnitude of the driving current.

On the other hand, during the first to third time periods of the second subpixel SP2, the data voltage and the threshold voltage of the first subpixel SP1 are deleted, and the data voltage and the threshold voltage of the second subpixel SP2 are again . To this end, in the first to third time periods of the second subpixel SP2, the control signals are inverted with respect to the control signals applied in the first to third time periods of the first subpixel SP1 do.

The circuit and the connection structure described above are not particularly limited. For example, if the n-th pixel and the (n + 1) -th pixel share the storage capacitor Cst, other circuits and connection structures may be possible.

Hereinafter, a display panel structure of an organic light emitting diode display device according to the present invention having the sub-pixel structure as described above will be described with reference to the drawings.

3 is a plan view schematically showing an organic light emitting diode display device according to an embodiment of the present invention. Here, for convenience of explanation, only the first electrode of the organic light emitting diode and the drain contact hole exposing the drain electrode of the fifth transistor which contacts the first electrode of the organic light emitting diode are shown.

3, an organic light emitting diode display device according to an embodiment of the present invention includes a substrate 101, a plurality of scan lines (not shown) formed on the substrate 101, and a plurality of data lines And a plurality of pixels PXL1, PXL2, PXL3, PXL4, ..., each of which is composed of a plurality of sub-pixels defined by intersecting a plurality of scan lines (not shown) and a plurality of data lines (not shown) (T 1 to T 10,..., T (n) in FIG. 2) formed in each of the pixels PXL 1, PXL 2, PXL 3, PXL 4, At this time, the planarizing film 109 is formed on the entire surface of the substrate 101 so as to cover a plurality of transistors (T1 to T10, ..., T (n) in FIG. 2).

The first to fifth transistors T1 to T5 having switching and driving functions are formed in the first pixel PXL1. The first to fifth transistors T1 to T5 in FIG. T5 may have a connection structure as shown in FIG. 2. However, the present invention is not limited to the above-described structure. However, for convenience of description, the above-described components will be mainly described, And it can be an emission transistor or a driving transistor depending on the configuration.

A fifth drain contact hole 113 exposing the drain electrode of the fifth transistor (T5 in FIG. 2) is provided in the planarization film 109, and the fifth transistor The first electrode 110 of the first organic light emitting diode (E1 of FIG. 2) connected to the drain electrode of the organic light emitting diode (T5 of FIG. 2) is formed.

The first pixel PXL1 may include red (R), green (G), and blue (B) subpixels. In each subpixel, a transistor and a first electrode of the organic light emitting diode Respectively. Here, the first pixel PXL1 is not limited to a sub-pixel including red (R), green (G), and blue (B) subpixels and may include red (R), green (G), blue (B) W) sub-pixels.

The sixth to tenth transistors (T6 to T10 in Fig. 2) that perform switching and drive functions are formed in the second pixel PXL. The drain electrode of the tenth transistor (T10 of FIG. 2) is exposed through the tenth drain contact hole 117 and the drain electrode of the second organic light emitting diode (E2 of FIG. 2) (Not shown).

The third and fourth transistors PXL3 and PXL4 are formed with transistors (T1 to T10 in FIG. 2) for performing switching and driving functions. The fifth transistor and the tenth transistor (T5, T10 are exposed through the fifth and tenth drain contact holes 123 and 127, respectively.

At this time, the first electrode 120 of the third organic light emitting diode of the third pixel PXL3 is in contact with the drain electrode of the tenth transistor T10 of the fourth pixel PXL4, The first electrode 125 of the fourth organic light emitting diode is brought into contact with the drain electrode of the fifth transistor T5 of the third pixel PXL3.

If the structure of the first pixel PXL1 and the second pixel PXL is repeated so that a display panel is formed, the organic light emitting diode display device having such a structure is formed by sharing a capacitor between two pixels Since only one pixel of the data signal stored in the capacitor can be used, 1, 3, 5, 7,... During the first half frame (first half frame) The odd-numbered columns are driven first in sequence, and then in the second half frame (second half frame), 2, 4, 6, 8, ... Division drive in which even-numbered columns are driven in order.

That is, when the structures of the first pixel PXL1 and the second pixel PXL are repeated to constitute a display panel, a screen is displayed in a line interlace manner. As a result, There is a problem in that image quality degradation may occur.

However, as described above, the first electrode 120 of the third organic light emitting diode of the third pixel PXL3 is in contact with the drain electrode of the tenth transistor T10 of the fourth pixel PXL4, If the first electrode 125 of the fourth organic light emitting diode of the third pixel PXL4 is constituted by a display panel which is in contact with the drain electrode of the fifth transistor T5 of the third pixel PXL3, However, since each pixel is driven by being crossed in dot-by-dot manner by a dot interlace method, it is possible to improve image quality degradation due to a line interlace method.

Fig. 4 is a cross-sectional view taken along line III-III in Fig. 3; Fig. In this case, although only the fifth transistor and the tenth transistor, the capacitor and the organic light emitting diode are shown in the figure for the sake of convenience, the first through fourth and sixth through ninth transistors are the same material in the same process as the fifth transistor and the tenth transistor, Structure.

4, the substrate 101 is made of polysilicon. The central portion of the substrate 101 has a first region 133a and a fourth region 135a in which channels are formed, and a first region 133a and a second region 133b. The first semiconductor layer and the second semiconductor layer including the impurity-doped second region 133b and the third region 133c and the fifth region 135b and the sixth region 135c on both sides of the fourth region 135a, (Actually, the fifth semiconductor layer of the fifth transistor and the tenth semiconductor layer of the tenth transistor) 133 and 135 are formed.

A buffer layer (not shown) made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN _x ) is formed on the entire surface between the first and second semiconductor layers 133 and 135 and the first substrate 101. May be provided.

A first insulating layer 103 is formed on the entire surface of the substrate 101 so as to cover the first and second semiconductor layers 133 and 135. A first semiconductor layer and a second semiconductor layer The first gate electrode and the second gate electrode 140 and 142 corresponding to the first region 133a and the fourth region 135a of the layers 133 and 135 are actually connected to the fifth gate electrode of the fifth transistor and the tenth transistor The tenth gate electrode of the tenth layer is formed. At this time, although not shown in the figure, gate wiring (not shown) extending in one direction is formed on the first insulating film 110.

A second insulating layer 107 is formed on the first gate electrode and the second gate electrodes 140 and 142 and the upper surface of the gate wiring (not shown). At this time, a second region, a third region, a fifth region, a sixth region, and a fourth region located on both sides of the first region 133a and the fourth region 135a are formed in the second insulating film 107 and the first insulating film 103 under the second insulating film 107, First contact holes and second contact holes CH1 and CH2 exposing the regions 133b, 133c, 135b and 135c are formed. At this time, although not shown in the figure, on the upper portion of the second insulating film 107 including the first contact hole and the second contact holes CH1 and CH2, a data wiring (not shown) crossing the gate wiring (Not shown) is formed.

A second region, a third region, a fifth region, a sixth region 133b, 133c, 135b, and 135c exposed above the second insulating film 107 through the first and second contact holes CH and CH2, A first source and first drain electrodes 151 and 153, a second source and a second drain electrode 155 and 157 are formed.

At this time, the first source and first drain electrodes 151 and 153, the first semiconductor layer 133, the first insulating film 103 and the first gate electrode 140 form a fifth transistor T5 The second source and drain electrodes 155 and 157 and the second semiconductor layer 135 and the first insulating layer 103 and the second gate electrode 142 constitute a tenth transistor T10.

6 and 7 (in the organic light-emitting diode device of the present invention, each of the transistors T5 and T10 has a polysilicon semiconductor and is of a top gate type) (Bottom gate type) having a semiconductor layer of amorphous silicon (233 in FIG. 6) or a semiconductor layer made of an oxide semiconductor material (331 in FIG. 7), as shown in FIG. .

6, the gate electrode 240, the gate insulating film 203, and the active layer 233a of pure amorphous silicon are spaced apart from each other and the impurity amorphous silicon A semiconductor layer 233 made of an ohmic contact layer 233b and source and drain electrodes 251 and 253 spaced apart from each other or having a laminated structure of a gate electrode 340, Source and drain electrodes 351 and 353 which are separated from each other on the gate insulating film 303, the oxide semiconductor layer 331, the etch stopper 333 and the etch stopper 333 and are in contact with the oxide semiconductor layer 331, As shown in FIG.

Referring again to FIG. 4, a planarizing film 109 is formed on the entire surface of the substrate 101 over the fifth and tenth transistors T5 and T10. In this case, the fifth drain contact hole 113 exposing the drain electrode 153 of the fifth transistor T5 and the drain electrode 157 of the tenth transistor T10 are exposed in the planarization film 109, Drain contact holes 117 are formed.

The upper part of the planarization film 109 having the fifth and tenth drain contact holes 113 and 117 is in contact with the drain electrode 153 of the fifth transistor T5 through the fifth drain contact hole 113, A first electrode 110 of the organic light emitting diode and a first electrode 115 of the second organic light emitting diode are formed.

The first electrode 110 of the first organic light emitting diode and the first electrode 115 of the second organic light emitting diode may be formed of a transparent conductive material having a relatively large work function value such as indium tin oxide ITO) or indium-zinc-oxide (IZO).

The first electrode 110 of the first organic light emitting diode and the first electrode 115 of the second organic light emitting diode may have a double layer structure. The first electrode 110 of the first organic light emitting diode, An upper layer (not shown) of the first electrode 115 of the second organic light emitting diode serves as an anode electrode, and a lower layer (not shown) serves as a reflective plate. The lower layer (not shown) may be made of a metal material having excellent reflection efficiency, for example, aluminum (Al) or silver (Ag), and may include a first electrode 110 of the first organic light emitting diode, Light emitted from an organic light emitting layer (not shown) formed on the electrode 115 is reflected upward and recycled, thereby improving luminous efficiency.

The first electrode 139 of the storage capacitor Cst is formed between the fifth transistor T5 and the tenth transistor T10 on the first insulating film 103 and the first electrode 139 of the storage capacitor Cst is formed between the fifth transistor T5 and the tenth transistor T10. The second electrode 159 of the storage capacitor Cst is formed on the second insulating film 107 corresponding to the electrode 139. [

Although not shown in the drawing, banks (not shown) are formed at the edges of the first electrode 110 of the first organic light emitting diode and the first electrode 115 of the second organic light emitting diode, An organic light emitting layer (not shown) is formed at a central portion where no organic light emitting layer (not shown) is formed. At this time, the organic light emitting layer (not shown) may be formed of a single layer made of an organic light emitting material, or may have a multi-layer structure to enhance the light emitting efficiency.

When the organic light emitting layer (not shown) has a multilayer structure, a hole injection layer, a hole transporting layer, an emitting material layer (light emitting layer) A hole transporting layer, an emitting material layer, and an electron transporting layer), an electron transporting layer, and an electron injection layer (a five-layer structure) A hole transporting layer, an emitting material layer, and an electron transporting layer, each of which is formed of a single layer, a hole injection layer, and an electron injection layer.

A second electrode (not shown) of the first organic light emitting diode and a second electrode (not shown) of the second organic light emitting diode are formed on the organic light emitting layer (not shown).

Each second electrode (not shown) serves as a cathode electrode and is formed of a metal material having a relatively low work function value such as aluminum (Al), aluminum alloy (AlNd), silver (Ag) (Au), an aluminum magnesium alloy (AlMg), or two or more materials.

5 is a cross-sectional view taken along the line IV-IV in FIG. 3, and the components corresponding to those shown in FIG. 4 are omitted in the description of each component.

A planarizing film 109 is formed on the entire surface of the substrate 101 above the fifth and tenth transistors T5 and T10. In this case, the fifth drain contact hole 127 exposing the drain electrode 153 of the fifth transistor T5 and the drain electrode 157 of the tenth transistor T10 are exposed in the planarization film 109, Drain contact holes 123 are formed.

The upper part of the planarization film 109 having the fifth and tenth drain contact holes 127 and 123 is in contact with the drain electrode 153 of the fifth transistor T5 through the fifth drain contact hole 127, The first electrode 125 of the organic light emitting diode and the drain electrode 157 of the tenth transistor T10 are connected to the tenth drain contact hole 123 and the first electrode 120 of the third organic light emitting diode Respectively.

At this time, as described above, the first electrode 120 of the third organic light emitting diode of the third pixel PXL3 is brought into contact with the drain electrode 157 of the tenth transistor T10 of the fourth pixel PXL4 The first electrode 125 of the fourth organic light emitting diode of the fourth pixel PXL4 is brought into contact with the drain electrode 153 of the fifth transistor T5 of the third pixel PXL3.

8 is a photograph showing an image output of one frame of the organic light emitting diode display according to the embodiment of the present invention.

As shown in FIG. 8, the organic light emitting diode display device according to the embodiment of the present invention includes a first pixel, a fourth pixel, and a second pixel in a first half frame. The second pixel, the third pixel, and the third pixel in the second half frame. It is possible to confirm that the video output is performed. That is, the image output is inverted for each neighboring pixel in the half frame unit, and is driven by the dot interlace method.

As described above, in the organic light emitting diode display device according to the present invention, the first electrodes of the organic light emitting diodes are formed in units of pixels sharing a capacitor in the case of a pixel structure sharing one capacitor, It is possible to drive it in an interlaced manner and thus it is possible to output a high-quality image.

At the same time, since the capacitor is shared, the capacitance of the capacitor can be ensured, the display area of the organic light emitting diode display can be ensured, and high resolution and high definition (ppi) can be realized.

In another embodiment of the present invention, the effect of the capacitor on the signal interference and the like can be minimized by using dummy pixels, which will be described with reference to the drawings.

9 is a plan view schematically showing an organic light emitting diode display device according to another embodiment of the present invention.

9, a dummy region 410 is formed in the first stage 400 and the last stage 490, and the dummy region 410 is formed in the second stage from the pixel P).

A plurality of transistors T1 to T10, ..., T (n) are formed in the dummy region 410 to share a capacitor with adjacent pixels, and a plurality of transistors T1 to T10, The pixel P except for the dummy region 410 has the same components as those of the above-described embodiment, and the manufacturing process is also similar to that of the above embodiment. The dummy area 410 may correspond to the first and third pixels PXL1 and PXL3 of FIG. 3, and sequentially extend to a plurality of pixels (PXL2, PXL4, PXL5, PXL7, ...) can be defined.

That is, in the organic light emitting diode display device according to another embodiment of the present invention, only the organic light emitting diode is not formed in the dummy region 410, but a structure in which one capacitor is shared is maintained. The first electrode of the first organic light emitting diode may be coupled to the second pixel PXL2, the first electrode of the second organic light emitting diode may be coupled to the fifth pixel PXL5, One electrode may be coupled to the fourth pixel PXL4 and the first electrode of the third organic light emitting diode may be coupled to the seventh pixel PXL7.

At this time, the video output is the second pixel, the seventh pixel, and the third pixel in the first half frame. , And the fourth pixel, the fifth pixel, the second pixel in the second half frame, , Will be displayed.

A plurality of other unspecified pixels may be formed up to the last stage 490 in a form corresponding to the second, fourth, fifth, and seventh pixels PXL2, PXL4, PXL5, and PXL7 described above.

The present invention is not limited to the above-described embodiments and modifications, and various modifications may be made without departing from the spirit of the present invention.

CH1, CH2: semiconductor layer contact hole T: transistor
PXL1: first pixel PXL2: second pixel
PXL3: third pixel PXL4: fourth pixel
101: substrate 109: planarization film
110, 115, 120, 125: anode electrode
113, 117, 123, 127: drain contact hole

Claims (10)

A substrate including first to fourth pixels arranged in two rows and two columns;
First to fourth emissive transistors formed in the first to fourth pixels, respectively;
A first electrode of a first organic light emitting diode formed in the first pixel and connected to the first emission transistor;
A second electrode of a second organic light emitting diode formed on the second pixel and connected to the second emission transistor;
A third electrode of the third light emitting diode formed in the fourth pixel and connected to the third emission transistor;
A fourth electrode of a fourth light emitting diode formed in the third pixel and connected to the fourth emission transistor;
A first storage capacitor shared by the first and second pixels;
And a second storage capacitor shared by the third and fourth pixels.
The method according to claim 1,
A first switching transistor and a first driving transistor formed in the first pixel;
A second switching transistor and a second driving transistor formed in the second pixel;
A third switching transistor and a third driving transistor formed in the third pixel;
And a fourth switching transistor and a fourth driving transistor formed in the fourth pixel.
3. The method of claim 2,
Both ends of the first storage capacitor are connected to the first and second driving transistors, respectively,
And both ends of the second storage capacitor are connected to the third and fourth driving transistors, respectively.
The method according to claim 1,
The first organic light emitting diode may further include a first light emitting layer and a fifth electrode sequentially formed on the first electrode,
The second light emitting diode further includes a second light emitting layer and a sixth electrode sequentially formed on the second electrode,
The third light emitting diode may further include a third light emitting layer and a seventh electrode sequentially formed on the third electrode,
Wherein the fourth light emitting diode further comprises a fourth light emitting layer and an eighth electrode sequentially formed on the fourth electrode.
The method according to claim 1,
The first and fourth pixels are driven during the first half frame,
And the second and third pixels are driven during a second half frame.
A substrate including first through sixth pixels arranged in three rows and two columns from the top and seventh through twelfth pixels arranged in two rows in three rows from the bottom;
First to twelfth emission transistors formed in the first to twelfth pixels, respectively;
A first electrode of a first organic light emitting diode formed in the second pixel and connected to the second emission transistor;
A second electrode of a second organic light emitting diode formed in the third pixel and connected to the third emission transistor;
A third electrode of the third organic light emitting diode formed in the fifth pixel and connected to the sixth emission transistor;
A fourth electrode of a fourth organic light emitting diode formed in the sixth pixel and connected to the fifth emission transistor;
A fifth electrode of a fifth organic light emitting diode formed in the seventh pixel and connected to the seventh emission transistor;
A sixth electrode of the sixth organic light emitting diode formed in the eighth pixel and connected to the eighth emission transistor;
A seventh electrode of the seventh organic light emitting diode formed in the tenth pixel and connected to the eleventh emission transistor;
An eighth electrode of an eighth organic light emitting diode formed in the eleventh pixel and connected to the amplification transistor;
A first storage capacitor shared by the first and second pixels;
A second storage capacitor shared by the fourth and fifth pixels;
A third storage capacitor shared by the eighth and ninth pixels;
And a fourth storage capacitor shared by the eleventh and twelfth pixels.
The method according to claim 6,
A first switching transistor and a first driving transistor formed in the first pixel;
A second switching transistor and a second driving transistor formed in the second pixel;
A third switching transistor and a third driving transistor formed in the third pixel;
A fourth switching transistor and a fourth driving transistor formed in the fourth pixel;
A fifth switching transistor and a fifth driving transistor formed in the fifth pixel;
A sixth switching transistor and a sixth driving transistor formed in the sixth pixel;
A seventh switching transistor and a seventh driving transistor formed in the seventh pixel;
An eighth switching transistor and an eighth driving transistor formed in the eighth pixel;
An eighth switching transistor and an eighth driving transistor formed in the eighth pixel;
A ninth switching transistor and a ninth driving transistor formed in the ninth pixel;
A tenth switching transistor and a tenth driving transistor formed in the tenth pixel;
An eleventh switching transistor and an eleventh driving transistor formed in the eleventh pixel;
And a twelfth switching transistor and a twelfth driving transistor formed in the twelfth pixel.
8. The method of claim 7,
Both ends of the first storage capacitor are connected to the first and second driving transistors, respectively,
Both ends of the second storage capacitor are connected to the fourth and fifth driving transistors, respectively,
Both ends of the third storage capacitor are connected to the eighth and ninth driving transistors, respectively,
And both ends of the fourth storage capacitor are connected to the eleventh and twelfth driving transistors, respectively.
The method according to claim 6,
Wherein the first, fourth, ninth, and twelfth pixels are dummy regions.
The method according to claim 6,
The second and sixth pixels, the seventh and eleventh pixels are driven during the first half frame,
And the third and fifth pixels, the eighth and tenth pixels are driven during the second half frame.

Images