KR20150031983A - Apparatus for pvt variation calibration of ring osc based on injection locking system and the method thereof - Google Patents

Abstract

Disclosed are a device and a method for the PVT variation calibration of an injection-locking-based ring oscillator. The present invention is formed by including an injection pulse generator generating an injection pulse by receiving a reference clock generated in a reference clock generating part; a first ring-shaped VCOs outputting a predetermined frequency by receiving the injection pulse of the injection pulse generator; and a feedback circuit receiving the reference clock and an output frequency (Fvco) of a second ring-shaped VCO, generated in the reference clock generating part and the second ring-shaped VCO, and performing digital calibration for the clock and the frequency in order to input the clock and the frequency as control voltages of the first and second VCOs. Thus, a stable multiplied frequency against PVT variation is generated.

Description

FIELD OF THE INVENTION [0001] The present invention relates to an apparatus and a method for correcting a change of a polarization of a ring oscillator based on injection locking,

More particularly, the present invention relates to a frequency multiplier, and more particularly to a frequency multiplier that inputs an output signal of an injection block to a ring VCO1 so that a frequency N-multiplied by a reference clock of the VCO1 is output as a first output signal, A device for correcting the change of the PV of the ring oscillator based on injection locking to solve the PVT change problem by inputting the control voltage of the analog value to the error through the digital correction of the output signal as the control voltage of VCO1 and VCO2 ≪ / RTI >

BACKGROUND ART Generally, a voltage control oscillator (VCO) is a device for controlling an oscillation frequency by controlling a voltage, and is a device that is essentially used for up-conversion or down-conversion of a predetermined frequency. to be.

Such a voltage-controlled oscillator can be divided into a ring oscillator, an LC oscillator, and a crystal oscillator. Among them, the ring oscillator is widely used in a clock / data recovery circuit and a frequency synthesizer because of its simple structure.

Conventionally, a ring oscillator is used to generate a clock signal having a constant frequency. The ring oscillator is constituted by connecting three or more odd number of inverters in a ring form or connecting a predetermined number of differential amplifiers in a ring form.

A technique for such a conventional ring oscillator is disclosed in Japanese Patent Application Laid-Open No. 10-2010-0073948 (a ring oscillator having a broadband output frequency).

However, since the conventional ring oscillator has a limitation in reducing the delay time of the inverters constituting the ring form, there is a problem that it is impossible to generate a clock signal having a high frequency exceeding a certain frequency.

FIG. 1 shows the connection of each node of the conventional ring oscillator and the number of input / output signals of each node, and shows a case where clock signals are generated through three nodes A, B, and C, respectively.

In FIG. 1, three nodes A, B and C are connected in a ring form, and each of the nodes A, B and C inputs one input signal and generates one output signal. (1, 1), the former 1 means the number of input signals and the latter 1 means the number of output signals.

That is, when a conventional ring oscillator is configured to generate a clock signal through three or more odd number of nodes, each of the nodes is configured to input one input signal and generate one output signal.

 Fig. 2 shows the configuration of one embodiment of the ring oscillator according to Fig. 1, which is composed of inverters I1 to I3. Each of the nodes A, B, and C between the inverters I1 to I3 corresponds to the nodes A, B, and C in Fig.

In FIG. 2, each of the inverters I1, I2, and I3 inputs one input signal to generate one output signal. In other words, the inverter I1 inverts the clock signal of the node C to generate the inverted clock signal to the node A, and the inverter I2 inverts the clock signal of the node A to the node B Generates an inverted clock signal, and inverter I3 inverts the clock signal of node B to generate an inverted clock signal at node C

Fig. 3 shows the configuration of another embodiment of the ring oscillator according to Fig. 1, which is composed of differential amplifiers DA1 to DA3. The nodes AB, BB, and CB correspond to the nodes A, B, and C of FIG. 1 and the nodes A, B, and C correspond to the nodes A, B, and C of the differential amplifiers DA1 to DA3. A, B, and C, respectively.

3, the differential amplifier DA1 amplifies the signal difference of the nodes C and CB to generate an amplified signal to the nodes A and AB, and the differential amplifier DA2 amplifies the signals A and AB ) To generate amplified signals to the nodes B and BB. The differential amplifier DA3 amplifies the signal difference between the nodes B and BB and generates a signal amplified by the nodes C and CB.

Fig. 4 is a timing diagram of clock signals generated at the respective nodes of the ring oscillator shown in Fig. 2 or Fig. 3, and is a timing chart showing the operation of the inverters I1, I2, I3 or the differential amplifiers DA1, DA2 , And DA3 are assumed to be tD, respectively.

The clock signal of the node A is delayed by the delay time tD and inverted to generate the clock signal at the node B and the clock signal of the node B is delayed by the delay time tD, And a clock signal is generated at the node (C). Then, the clock signal of the node C is delayed and inverted by the delay time tD, and the clock signal of the node A is generated. As a result, the pulse width of the clock signal generated in each of the nodes A, B, and C has a time of 3tD, the period of the clock signal becomes 6tD, and the frequency becomes 1 / 6tD.

Conventional ring oscillators reduce the delay time of the inverters constituting the ring oscillator, thereby reducing the period of the clock signal, thereby increasing the frequency of the clock signal. Thus, a ring oscillator comprising three inverters or differential amplifiers can generate the clock signal of the highest frequency.

As described above, when the delay reference clock is generated using the delay circuit, the delay value of the delay circuit is changed according to Variation of the process, external supply voltage and temperature (Process / Voltage / Temperature, hereinafter referred to as 'PVT') The delay of the delay reference clock CLK_DEL varies depending on the interval. For example, the delay value of the delay circuit decreases when the external supply voltage rises or when the temperature decreases. Accordingly, the duration of the phase is also different.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide an apparatus and method for calibrating the variation of a frequency of an injection locking based ring oscillator which can operate as a stable frequency synthesizer such as a PLL by using a digital feedback circuit.

It is another object of the present invention to provide an apparatus and a method for correcting the change of PVT of a ring oscillator based on injection locking that is stable against changes in PVT.

In order to accomplish the above object, there is provided an apparatus for calibrating a change in frequency of an injection locking ring oscillator according to the present invention. The apparatus includes a first inverter for receiving a reference clock F _ref and outputting a multiplied frequency f _out , A VCO (Voltage Controlled Ring Oscillator) of a ring shape, a VCO (Voltage Controlled Ring Oscillator) of a second ring form, and an output signal (Fvco) of the VCO of the second ring form, And a feedback circuit for inputting the VCO control voltage of the VCO control voltage.

Further, receiving the reference clock (F _ref) the reference clock generating unit, and the reference clock (F _ref) generated by the reference clock generating section for generating generates the injection pulse synchronized to the reference clock to the VCO of the first It is possible to configure the first VCO to generate a signal which is preferably synchronized with the multiplication frequency of the reference clock F _ref .

The feedback circuit receives the reference clock F _ref generated by the reference clock generation unit and the frequency division frequency F _vco / N of the frequency division unit and _performs digital calibration to input the first and second VCO control voltages .

The feedback circuit includes a window generator for generating an EN (F _ref / k / 2) signal obtained by dividing the reference clock generated by the reference clock generator and generating a window of the 'High' state of the EN signal as a window, A counter for counting a frequency (Fvco / N) obtained by dividing the output frequency (Fvco) of the second VCO by receiving a window output from the window generator, and a counter for counting a frequency (Fvco / N) A), and controlling the first and second VCOs to have different control voltages according to a result value of the comparator.

The feedback circuit includes a register for storing the output value of the comparator in the previous stage as a binary code, an adder for adding the output signal of the comparator to the output signal of the register according to the comparison result of the comparator, And a control voltage corresponding to the analog signal of the DA converter is generated and input to the first and second VCO control voltages so as to repeat the calibration, thereby obtaining a frequency doubled stable in PVT variation .

The completion of such calibration is configured so as to satisfy the condition of the following equation.

On the other hand, the feedback circuit configures the frequency control word (FCW) as a calibration reference value through a second step in the comparator by setting different constants over two steps.

K = k + n (n = 1, 2, 3, 4, 5, 6, 7, Constant) ', subtracting it from the comparator again, and when the condition of completion of the calibration is satisfied as a result of the subtraction, the calibration operation is stopped, and' k = arbitrary constant 'is set and subtracted from the comparator, If not, the adder adds the output signal of the comparator and the binary code value, which is the output value of the comparator of the preceding stage, to the DA converter.

If the result of the subtraction in the comparator is not satisfied, the output signal of the comparator and the binary code value, which is the output value of the comparator of the preceding stage, are added by the adder, .

The present invention also provides a method for calibrating a change in the frequency of an injection locking based ring oscillator that includes a first VCO and a second VCO and outputs a frequency multiplied by a predetermined multiple, comprising the steps of: (a) (B) applying a control voltage to the first and second VCOs; and (c) applying a signal obtained by calibrating the second VCO output signal to the feedback circuit to the first and second To the VCO control voltage of the VCO.

(c) a step (c-1) of performing digital calibration by receiving the reference clock F _ref generated by the reference clock generator and the frequency division frequency F _vco / N of the frequency divider, -2) inputting the output signal of the step (c-1) as the first and second VCO control voltages.

The step (c-1) further includes the steps of (c-1-1) generating a window F _ref / k from an EN (F _ref / k / 2) signal obtained by dividing the reference clock generated by the reference clock generator (Fvco / N) obtained by dividing the output frequency (Fvco) of the second VCO by receiving the window (F _ref / k) output from the window generation step (c-1-2) (C-1-3) a step of subtracting the output value (A) of the count from a calibration reference value FCW (Frequency Control Word) in the comparator, (c-1-4) And controlling the first and second VCOs to have different control voltages according to a result of the step (1) - (3).

Therefore, according to the apparatus and method for calibrating the variation of the frequency of an injection locking-based ring oscillator of the present invention, it is possible to generate a clock signal having a stable phase with respect to a change in PVT and an oscillator Can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a reference drawing showing the connection of each node of a conventional ring oscillator and the number of input / output signals of each node,
2 is a diagram showing the configuration of one embodiment of the ring oscillator according to FIG. 1,
3 is a diagram showing a configuration of another embodiment of the ring oscillator according to FIG. 1,
FIG. 4 is a timing diagram of clock signals generated at each node of the ring oscillator shown in FIG. 2 or FIG. 3;
FIG. 5 is a block diagram of an apparatus for varying the frequency of an injection locking based ring oscillator according to an embodiment of the present invention. FIG.
6 is an input / output signal of the frequency division unit of the present invention,
7 is a diagram for explaining the function of the counter of the present invention,
FIG. 8 is a flow chart for explaining a method for varying the variation of a frequency of an injection locking-based ring oscillator according to an embodiment of the present invention;
And,
9 is a flowchart for explaining the digital calibration method of the present invention.

It is to be understood that the words or words used in the present specification and claims are not to be construed in a conventional or dictionary sense and that the inventor can properly define the concept of a term in order to describe its invention in the best possible way And should be construed in light of the meanings and concepts consistent with the technical idea of the present invention.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise. It should be noted that the terms such as " part, "" module, " .

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a block diagram of an apparatus for correcting the variation of a frequency of an injection locking ring oscillator according to an embodiment of the present invention, FIG. 6 is an input / output signal diagram of the frequency division unit of the present invention, Fig. 8 is a diagram for explaining the function of the counter of Fig.

As shown in the figure, an apparatus for changing the frequency of an injection locking ring oscillator according to an embodiment of the present invention includes a VCO having a frequency (N · Fref) multiplied by a reference frequency (Fref) (Hereinafter, referred to as a first VCO and a second VCO), and a first VCO (Voltage Controlled Ring Oscillator) is generated by an injection pulse generator 120 And generates and outputs a signal f _out = N * F _ref synchronized with the multiplication frequency of the reference clock, divides the frequency output from the second VCO, which is the same as the first VCO, F _ref ) is input to the first VCO and the second VCO so as to generate a stable high frequency and a stable clock in PVT (Process / Voltage / Temperature).

The apparatus includes a reference clock generating unit 110 for generating a reference clock, a reference clock generating unit 110 for generating a reference clock F _ref generated by the reference clock generating unit 110, A first ring-shaped VCO 161 for receiving an injection pulse of the injection pulse generator 120 and outputting a predetermined frequency, a second ring-shaped VCO 161 for receiving a pulse of the implantation pulse generator 120, A frequency divider 130 for dividing the output signal of the second ring type VCO 162 and a reference clock F _ref generated in the reference clock generator 110 and a frequency divider 130 And a feedback circuit 140 for receiving the frequency division frequency F _vco / N of the first and second VCO control voltages and performing digital correction and inputting the digital control voltage to the first and second VCO control voltages.

The reference clock generating unit 110 operates as a device for generating a reference clock signal F _ref necessary for the system.

The injection pulse generator 120 includes an injection locking oscillation means for injecting an internal clock signal synchronized with the reference clock signal F _ref of the reference clock generator 110. [

Since such an injection locking oscillating means is a general one, a detailed description thereof will be omitted.

The first and second VCOs (Voltage Controlled Oscillators) 151 and 152 are constituted by a Ring Oscillator of the same standard. A plurality of delay cells for inverting and delaying the input signal are connected in a loop form, , And is configured to generate a frequency proportional to the control voltage.

In the present invention, two VCOs of the same standard are used. However, since such a ring oscillator is also a general configuration, a detailed description thereof will be omitted.

The frequency divider 130 divides the frequency (F _vco ) output from the second VCO 152 and outputs a frequency of 'F _vco / N' times.

6, when the frequency F _vco output from the second VCO 152 passes through the frequency divider 130, the frequency divided by the frequency divider 130 is divided by 1 / N And is output as the frequency 'F _vco / N'.

The constant 'N' at this time is defined as a constant of a multiple to be multiplied with respect to the reference frequency.

The feedback circuit 140 receives the reference clock F _ref of the reference clock generating unit 110 and the output frequency F _vco of the second VCO 162 to perform a correction function for the PVT change, .

A window generator 141 for receiving a reference clock F _ref generated by the reference clock generator 110 and dividing a reference clock F _ref to generate a window signal, A counter 142 for counting a frequency obtained by dividing the output frequency Fvco of the second VCO 162 by a window signal of the first VCO 162 and a window signal of the second VCO 162, An adder 144 which combines the output signal of the comparator 143 and the output signal of the register 145, a DA converter 146 which converts the output signal of the adder 144 into an oscillator control voltage, The output signal of the converter 146 is input to the first and second VCO control voltages.

Through this configuration, when the second VCO 162 generates a frequency that is out of the error range from the frequency (N · Fref) that the second VCO 162 has aimed at by the PVT change, the feedback circuit 140 continuously repeats the loop F _vco can be calibrated to output a frequency within the target frequency error range.

More specifically, the feedback circuit 140 receives the reference clock signal F _ref from the reference clock generation unit 110 and the frequency-divided signal F from the second VCO 162 via the frequency division unit 130, receiving the _vco / N) until the busy signal (F _vco / N) and the reference clock signal (F _ref) equal within a margin of error _{(F ref = F vco / N} ) and continues around the loop proceeding to calibration The output frequency F _vco of the second VCO 162 has a value of N · F _ref within an error range. That is, when to make a busy value F _vco and F _ref is equal to the result F _vco is given the value N times multiplication.

Therefore, the output frequency F _vco of the second VCO 162 is divided by 1 / N while passing through the frequency divider 130.

The window generator 141 is a reference signal of the counter 142 that generates a reference clock signal (F _ref), the internal clock signal (EN), a synchronized and dividing the reference clock signal (F _ref) to and create a window, and then later Respectively.

This window performs the same function as the EN used in the registers, and the division at this time is divided into the following equations.

Here, k is set to an arbitrary constant.

The EN of the above equation is a signal through a frequency divider, and the window generator 141 generates a window of Equation (2) corresponding to a half period in the pulse width when the window is 'EN = 1'.

The counter 142 _counts the frequency of the frequency F _vco / N that is _obtained by dividing the output frequency F _vco of the second VCO 162 based on the window F _ref / k generated by the window generator 141. Count the number of clocks.

That is, the rising edge of (F _vco / N) is counted in the 'High' period F _ref / k of the signal generated by the window generator 141.

7, the rising edge of the frequency (F _vco / N) within one pulse of the signal (F _ref / k) generated by the window generator 141 the number of rising edges is counted.

Referring to the drawing, the period between the rising edges of the frequency F _vco / N is represented by '(1 / F _vco ) * N _sec ', and the number of rising edges existing in one pulse of (F _vco / N) .

The number of rising edges A counted in the count 142 can be expressed by the following equation (3) as follows.

Here, N means a frequency division number divided by the frequency division unit 130, and k is an arbitrary constant.

The signal passing through the window generator 141 is a signal having a frequency of F _ref / k / 2. Since the duty cycle is 50%, a pulsed wave in which a high state lasts for (k / F _ref ) . The counter 142 then counts the rising edges within the window.

This means that the length of the window F _ref / k is equal to several times the period N / Fvco of the input signal. Referring to Equation 3, this is the result of the counter within the error range.

'Within the error range' is because the counter has an inevitable error while counting the rising edge of the input signal during the 'High' time of the window.

Referring to Table 1 below, the drawings are described in more detail as follows.

Assuming that the output value of the count is '3', for example, when the counter 142 counts the input signal Fvco / N of the frequency divider 130, N and (2) Fvco '' / N. In this case, the second VCO 162 will output a different frequency when it is definitely (1) and (2). However, since the counter reflects only the rising edges in the window as output results, it is 2.01 (≒ 2) and 3.99 (≒ 4) when counted according to the above-described method (window length / Is '3' and outputs the same value. That is, even if the counter outputs '3', the corresponding oscillator frequency Fvco may be higher or lower than the target frequency N · Fref. The error range is expressed by the formula ΔFvco in the above figure.

As described above, when the conventional counter is used, the output value of the counter becomes '3', and the range of the 'window time / input signal period' that can be recognized as the output value is 2.0000001 to 3.9999999 2).

However, in the improved counter, even if the output value of the counter becomes '3', the range of the 'window time / input signal period' that can be recognized as the output value is 2.4999999 to 3.4999999 (≒ 1) (Rounded effect).

로 표현되고, 각 오차범위는 표 2와 같이 표시된다.The output value of the improved counter is expressed as shown in FIG. 7,

, And each error range is expressed as shown in Table 2. [

In the above equation, 'rounded off' means rounding off.

Referring to Table 2, the error range varies depending on the value of k. As k increases, the error range decreases. That is, as the frequency of the oscillator corresponding to the counter output value becomes larger, the value becomes closer to the target value.

The value of k is used to determine how many times the reference clock should be divided when the window generator 141 generates a window from the reference generator 110. [

In the present invention, the k value is initially set to a relatively small constant so that it is not precise, but after a rough calibration operation is performed in a short time, the calibration is performed slowly but with k = k + n '(n = constant) .

If FCW-A = 0, it is converted to k = k + n. If FCW-A = 0 then Fvco is changed by environmental change. The feedback circuit 140, which is a calibration loop, does not change the loop any longer unless it changes.

The contents of expressing the error range of Fvco according to the state of each k are shown in steps S261 and S264 in Fig.

In step S261, Rough & Fast Calibration is performed although 'k = arbitrary constant' is not accurate, and step S264 is a slow but detailed calibration.

The number (A) of rising edges counted by the counter unit 142 and the frequency control word (FCW) are input to the comparator 143 to calculate the frequency difference (phase difference) between the input frequencies.

The FCW (Frequency Control Word) functions as a comparison reference point in the feedback circuit 140, which is a digital calibration loop, as a frequency control word calculated by a digital filter.

Referring to FIG. 5, the output value A of the counter 142 can be expressed by Equation (4).

Here, 'rounded off' means rounding off.

In order to match the condition of equation (4) and the condition of 'Fvco = N * Fref (within the error range)' which is the purpose of the digital calibration loop of the feedback circuit, FCW must be k = k.

That is, it can be seen that the FCW satisfying the following condition (5) is k.

Here, 'error by window' is an error that occurs because the counter counts only the rising edge, which is an error reflecting the rounding effect.

The value of the digital calibration loop in feedback circuit 140 varies depending on the value of the k constant.

Preferably, FCW may be a value expressed as a binary code of k.

For example, when k = 4, the binary code is 2 ⁴ = 00010000, and when k = 7, 2 ⁷ = 10000000.

The reason why the value of the constant k is determined to be 'arbitrary constant' and 'k = k + n (n is a constant)' is that the most optimal condition to overcome the PVT change is selected I will reveal.

The signal (FCW-A) subtracted by the comparator 143 is input to the adder 144. [

An adder 144 is configured to determine a binary code value to apply to the DA converter 146 in accordance with the result of the signal FCW-A subtracted in the comparator 143. [

That is, the adder 144 determines that there is no frequency variation due to the PVT when the signal subtracted by the comparator 143 satisfies the condition of 'FCW-A = 0', and the adder 144 subtracts the subtracted signal from the comparator 143 The FCW-A value is added to the binary code value to be applied to the previous DA converter 146 and the value of 'FCW-A' is added to DA Converter 146 as shown in Fig.

To this end, the adder 144 is configured to configure a register 145 for storing a previous binary code value to be applied to the DA converter 146 in parallel, and to sum up previous binary code values according to the corresponding condition.

The binary code value output from the adder 144 is input to the DA converter 146 to output a control voltage to be applied to the first and second VCOs 151 and 152 as an analog signal. The first and second VCOs 151 and 152 generate and output a corresponding frequency signal according to the input control signal value.

As described above, according to the apparatus for correcting the variation of the frequency of an injection locking-based ring oscillator of the present invention, it is possible to generate a high frequency multiplication frequency and a stable frequency signal in PVT.

That is, the first VCO can generate a stable frequency for the PVT change by the feedback circuit.

When the calibration process is completed by the feedback circuit 140, the second VCO 162 outputs a frequency close to the target frequency N · Fref within the error range.

However, the first VCO 161 can output the target frequency itself, which has the error range removed by the help of the injection pulse generator 120. [ That is, when the calibration process is completed, both the first VCO 161 and the second VCO 162 output the frequency multiplied by the reference clock, but the first VCO 161 outputs 'N Fref' 2 VCO 162 outputs the frequency in the vicinity of N · Fref with an error of ΔFvco as described above.

As a result, the first VCO 161 can generate a stable frequency for the PVT change by the feedback circuit 140.

A description will now be made of a method for correcting the change of the frequency of an injection locking based ring oscillator according to an embodiment of the present invention using such a configuration.

8 is a flow chart for explaining a method for correcting the variation of the P-type of the ring oscillator based on the injection locking according to an embodiment of the present invention. As shown in FIG. 8, The control voltage of the DA converter 146 corresponding to the binary code value of the adder 144 is supplied to the first and second VCOs 161 and 162 in a state in which the first and second VCOs 161 and 162 are initialized (S210) 161 and 162 (S220).

The second VCO 162 outputs Fvco according to the control value of the DA converter 146 at step S230 and the frequency divider 130 divides Fvco into N (arbitrary constant) 140 (S240).

Thereafter, the feedback circuit 140 counts the frequency Fvco / N divided by the frequency divider 130 based on the window output from the window generator 141 and performs binary coding on the frequency Fvco / N (S250). In step S250, The FCW-A is compared with the FCW in the comparator 143 in step S260. In step S270, the loop is repeated until Fvco = N * Fref. If the condition is Fvco ≠ N * Fref, To the previous binary code value of the DA converter 146 and outputs the corresponding analog control value. If it is determined in step S270 that the condition of 'Fvco = N * Fref' is satisfied, This is applied to the control voltage of the VCO and the calibration operation is stopped (S280).

Hereinafter, the digital calibration operation of such a feedback circuit will be described in more detail with reference to the drawings.

9 is a flowchart for explaining the digital calibration method of the present invention in detail. As shown in FIG. 9, when the divided frequency Fvco / N is inputted to the counter 142 in the frequency divider 130 (S251) The controller 142 counts the frequency Fvco / N inputted in step S251 on the basis of the window Fref / k generated by the window generator 141. [

At this time, the correction operation is repeated by setting the value of k to an arbitrary constant or 'k = k + n (n is a constant)' as described above.

That is, in the present invention, if k = arbitrary constant, it is not precise but the fast and fast calibration is performed first. If the calibration result is met, k = k + n (N = Constant) '.

First, in step S252, 'k = arbitrary constant' is set for fast and fast calibration, and the value of 'FCW-A' is calculated in the comparator 143 (S261) .

Specifically, the comparator 143 calculates 'FCW-A' as shown in Equation (5).

If the condition of 'FCW-A = 0' is satisfied as a result of subtraction in step S261, the process proceeds to step S262 for more precise calibration. If the condition of step S261 is not satisfied, it is determined that the calibration result is out of error, The value of the binary code corresponding to the subtraction result of step S261 and the binary code value of the previous DA converter 146 stored in the register 145 are summed by the adder 144 and transferred to the input value of the DA converter 146 (S280).

If the condition of 'FCW-A = 0' is satisfied at step S262, 'k = k + n (n = constant)' is set for more accurate calibration and the calibration is repeated again.

That is, in step S263, 'k = k + n (n = constant)' is set. In step S264, the comparator 143 calculates 'FCW-A' as shown in equation (7) (S265).

If it is determined in step S265 that the subtraction result is 'FCW-A? 0', the binary code value corresponding to the subtraction result in step S264 and the binary code value of the previous DA converter 146 stored in the register 145 are supplied to the adder 144) to be transmitted as an input value of the DA converter 146 (S280).

If it is determined in step S265 that FCW-A = 0, it is determined that the calibration is completed, and step S230 is repeated.

As described above, according to the apparatus and method for calibrating the change of the frequency of an injection locking-based ring oscillator of the present invention, the first VCO performs a digital calibration through a feedback circuit to generate a stable and multiplied frequency in PVT variation I can do it.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

110: reference clock generation unit 120: injection pulse generator
130: frequency divider 140: feedback circuit
141: window generator 142: counter
143: comparator 144: adder
145: Register 146: DA converter
161: first VCO 162: second VCO

Claims (19)

A first ring-shaped VCO (Voltage Controlled Ring Oscillator) receiving the reference clock F _ref and outputting a multiplied frequency f _out multiplied by a predetermined multiple;
A second ring-shaped Voltage Controlled Ring Oscillator (VCO)
A feedback circuit for calibrating the output signal (Fvco) of the second ring-shaped VCO and inputting it as the first and second VCO control voltages;
And an apparatus for calibration of a P-Vyt change of an injection locking-based ring oscillator.
The method according to claim 1,
A reference clock generator for generating a reference clock F _ref ;
An injection pulse generator for receiving the reference clock signal (F _ref ) generated by the reference clock signal generator and generating an injection pulse synchronized with the reference clock signal and inputting the pulse signal to the first VCO;
And an apparatus for calibration of a P-Vyt change of an injection locking-based ring oscillator.
3. The method of claim 2,
A frequency divider dividing an output signal of the second ring-shaped VCO;
Further comprising:
The feedback circuit
_Wherein the reference clock F _ref generated by the reference clock generator and the frequency division frequency F _vco / N of the frequency divider are subjected to digital calibration to input the first and second VCO control voltages, Based ring oscillator.
3. The method of claim 2,
The feedback circuit
A window generator for generating a window F _ref / k by dividing the reference clock generated by the reference clock generator;
A counter receiving a window F _ref / k output from the window generator and counting a frequency Fvco / N obtained by dividing an output frequency Fvco of the second VCO;
A comparator for subtracting the output value (A) of the count in a frequency control word (FCW) as a calibration reference value;
And for controlling the first and second VCOs to have different control voltages according to a result of the comparator, the apparatus for calibration of the P-type change of the ring oscillator based on injection locking.
5. The method of claim 4,
A register for storing the output value of the comparator in the previous stage as a binary code;
An adder for adding the output signal of the comparator and the output signal of the register according to the comparison result of the comparator;
A DA converter for converting an output signal of the adder into an oscillator control voltage;
And an output signal of the DA converter is input to the first and second VCO control voltages to repeat the calibration.
6. The method of claim 5,
Completion of calibration
An apparatus for calibration of a PbTy change in an injection locking based ring oscillator satisfying the conditions of the following equation:

Here, FCW is a calibration reference value, k is a constant for determining how many times the reference clock is divided when the window is generated through the window generator, Fref is a reference frequency generated by the reference clock generator, Fvco is a second And N is a constant representing a frequency multiple to be multiplied, and the 'error by the window' means an error by the rounding.
The method according to claim 6,
The feedback circuit
A device for calibration of P-Vyt change of an injection locking based oscillator in the comparator by setting different values of the frequency reference word FCW (Frequency Control Word) in two stages.
8. The method of claim 7,
The FCW (Frequency Control Word)
the correction of the P-type change of the injection locking-based ring oscillator, which is expressed by 'k', is first set to 'k = arbitrary constant' and subtracted by the comparator, and the calibration operation is stopped when the result of the subtraction is satisfied. .
9. The method of claim 8,
If the result of the subtraction in the comparator is not satisfied, the output signal of the comparator and the binary code value, which is the output value of the comparator of the preceding stage, are added by the adder and output to the DA converter A device for calibrating the variation of a pump oscillator based on an injection locking.
A method for changing a frequency of an injection locking-based ring oscillator, comprising: forming a pair of first and second VCOs to output a frequency multiplied by a predetermined multiple,
(a) initializing the first and second VCOs;
(b) applying a control voltage to the first and second VCOs; and
(c) inputting a signal obtained by calibrating the second VCO output signal in a feedback circuit as the first and second VCO control voltages;
/ RTI > A method for calibrating a P-Vty change in an injection locking based ring oscillator comprising:
11. The method of claim 10,
The step (b)
The injection pulse generator includes: an injection pulse input step of generating an injection pulse synchronized with the reference clock by receiving the reference clock F _ref generated by the reference clock generator and inputting the injection pulse to the first VCO;
/ RTI > A method of calibrating a pump oscillator based on an injection locking.
11. The method of claim 10,
The step (c)
And a signal (F _vco / N) _obtained by dividing the second VCO output signal (F _vco ) by a multiple of a multiple in the frequency division unit is input as a feedback signal.
12. The method of claim 11,
The step (c)
(c-1) receiving the reference clock (F _ref ) generated by the reference clock generator and the frequency division frequency (F _vco / N) of the frequency divider to perform digital calibration; and
(c-2) inputting the output signal of the step (c-1) as the first and second VCO control voltages;
/ RTI > A method of calibrating a pump oscillator based on an injection locking.
14. The method of claim 13,
The step (c-1)
(c-1-1) generating a window (F _ref / k) signal by dividing the reference clock generated by the reference clock generator;
(c-1-2) A counter (Fvco / N), which receives the window (F _ref / k) output from the window generation step and divides the output frequency (Fvco) of the second VCO, is counted by the counter step;
(c-1-3) subtracting an output value (A) of the count from a frequency reference word (FCW) as a calibration reference value in a comparator;
(c-1-4) controlling the first and second VCOs to have different control voltages according to the result of the step (c-1-3);
/ RTI > A method of calibrating a pump oscillator based on an injection locking.
15. The method of claim 14,
The step (c-1-4)
And adding the output signal of the comparator and the output value of the previous stage of the comparator according to the comparison result of the comparator in the adder.
11. The method of claim 10,
The step (c)
Wherein the calibration is repeated in the feedback circuit until the condition of the following equation is satisfied.

Here, FCW is a calibration reference value, k is a constant for determining how many times the reference clock is divided when the window is generated through the window generator, Fref is a reference frequency generated by the reference clock generator, Fvco is a second N is a constant representing a frequency multiple to be multiplied, and an error by a window means an error by a rounding.
17. The method of claim 16,
The FCW (Frequency Control Word)
a correction method of a change in the frequency of a ring oscillator based on an injection locking, which is expressed by 'k' and is first set to 'k = arbitrary constant' and subtracted from the comparator, .
18. The method of claim 17,
If the condition for completion of the calibration is not satisfied as a result of subtraction in the comparator by setting k = arbitrary constant, the output signal of the comparator and the binary code value, which is the output value of the comparator of the preceding stage, are added by the adder, 2 A method of calibrating the change of the frequency of a ring oscillator based on an injection locking signal output from a control voltage of a VCO.
19. The method of claim 18,
The binary coded output signal of the adder
DA converter to an analog control signal, and the converted analog control signal is converted from a regulator to a control voltage and applied to a control voltage of the first and second VCOs.

Images