KR101724365B1 - Injection locked clock multiplication apparatus and method using a replica delay cell - Google Patents

Injection locked clock multiplication apparatus and method using a replica delay cell Download PDF

Info

Publication number
KR101724365B1
KR101724365B1 KR1020160017772A KR20160017772A KR101724365B1 KR 101724365 B1 KR101724365 B1 KR 101724365B1 KR 1020160017772 A KR1020160017772 A KR 1020160017772A KR 20160017772 A KR20160017772 A KR 20160017772A KR 101724365 B1 KR101724365 B1 KR 101724365B1
Authority
KR
South Korea
Prior art keywords
delay cell
output
vco
inj
receiving
Prior art date
Application number
KR1020160017772A
Other languages
Korean (ko)
Inventor
최재혁
최서진
유세연
Original Assignee
울산과학기술원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 울산과학기술원 filed Critical 울산과학기술원
Priority to KR1020160017772A priority Critical patent/KR101724365B1/en
Application granted granted Critical
Publication of KR101724365B1 publication Critical patent/KR101724365B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

An injection locking clock multiplication apparatus and method using a replication delay cell in which jitter is not sensitive to PVT changes are disclosed.
The present invention can be expected to reduce power consumption and reduce silicon use area compared to a simple frequency tracking loop because the phase difference is corrected by including a replica delay cell in a voltage controlled oscillator.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an injection locking clock multiplication apparatus and method using a replication delay cell,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an injection locking clock multiplication apparatus, and more particularly, to an injection locking clock multiplication apparatus that includes a replica delay cell in a voltage controlled oscillator (VCO) A VCO capable of being implemented with a small silicon area, comprising: a phase comparator for detecting a phase difference caused by an input and an output between at least one delay cell and outputting a replica delay indicating an excellent jitter performance against PVT variation And more particularly, to an injection locking clock multiplication apparatus and method using a cell.

Injection locking clock multipliers are being considered as a promising solution for generating low jitter and high frequency clocks using a limited budget in terms of silicon area and power consumption.

However, there is a problem in that the injection locking clock multiplication device is sensitive enough to deteriorate jitter performance due to process, voltage and temperature (hereinafter referred to as 'PVT').

In order to solve this problem, a general injection locking clock multiplication device has various kinds of PVT calibrators which mitigate the sensitivity of jitter caused by PVT.

The phase locked loop is one of these PVT calibrators. It has the advantage of accurately making the deviation of the fixed frequency of the VCO caused by the process change, but it does not prevent the real time frequency drift caused by the change of voltage or temperature have.

Recently, a lot of efforts have been made to develop a new PVT calibrator capable of continuous frequency tracking, and devices have been developed to detect frequency drift using a replica VCO or a delay locked loop using a delay cell such as a VCO .

These devices have the problem that each calibrator must consume the same power as the power consumed by the VCO and there is a problem of inconsistency between limiting the calibration accuracy of the delay cell and the additional calibration steps.

Various methods have been proposed for a frequency tracking loop to detect the output phase variation of the VCO when a reference pulse is injected to solve additional problems.

Of the various methods proposed, there is a device for detecting a phase change using a time digital converter. However, this requires a lot of digital circuits, which requires a lot of silicon area and consumes a large amount of power.

In addition, there is a problem that a frequency tracking loop using a timing-adjusted phase detector generates phase noise in a wide band by a charge pump switch repeated every period.

Korean Patent Registration No. 10-1548256 discloses an apparatus and a method for correcting a P-type difference of an injection locking-based ring oscillator.

Such a calibration apparatus requires a plurality of VCOs, so there is a problem that the power consumption is large for correcting the difference due to PVT, and there is a problem that it occupies a large silicon area.

Also, there is a problem that discrepancies between delay cells limit the accuracy of the calibration or require additional calibration steps.

Korean Patent Registration No. 10-1548256

Therefore, it is a first object of the present invention to solve such a problem by adding a replication delay cell inside a VCO to reduce power consumption and silicon area, and to stabilize the jitter performance of the VCO with respect to PVT changes It is an object of the present invention to provide an injection locking clock multiplication apparatus using a replication delay cell capable of forming a continuous frequency tracking loop.

The second objective is to add a replication delay cell inside the VCO to reduce the power consumption and silicon area and to create a continuous frequency tracking loop that allows the jitter performance of the VCO to operate stably for PVT changes And an injection locking clock multiplication method using a replication delay cell.

According to an aspect of the present invention, there is provided a ring oscillator including a voltage controlled oscillator (VCO) including at least one delay cell and a replica delay cell, A free running frequency (hereinafter referred to as 'f VCO ') of the VCO is compared with a target frequency, and a 4-bit digital code COAR is generated and transmitted to the VCO to control the current of the VCO (Coarse Frequency Selector (CFS)). And a pulse generator (hereinafter, referred to as 'PG') that receives a first enable signal EN FINE from the CFS and generates a reference pulse and injects the reference pulse to the VCO, f REF ) and a multiplication factor M, that is, M * f REF , and the multiplication factor is an arbitrary constant. The present invention provides an injection locking clock multiplication apparatus using a replication delay cell.

By cloning the injection locking clock multiplier device using the delay cell is supplied to the capacitor to charge to a (C L) or the capacitor by receiving electric charge from the supply (C L), adjusting the control voltage (V FINE) in real time, the f VCO And a charge pump (hereinafter referred to as 'CP') that maintains the value of M * f REF .

The injection locking clock multiplication apparatus using the replication delay cell may include an input of the fifth delay cell and an input of the replica delay cell is an output of the fourth delay cell.

The injection locking clock multiplication apparatus using the replication delay cell may inject the reference pulse generated by the PG into the fifth delay cell so that the phase of the fifth delay cell may be corrected.

The injection locking clock multiplication apparatus using the replication delay cell receives the output of the fifth delay cell and the output of the replication delay cell and receives the second enable signal EN PD from the PG to obtain the phase difference of the VCO (Dual Edge Phase Detector < RTI ID = 0.0 > (DEPD)) < / RTI >

The DEPD may include a first phase detector (first PD ') and a second phase detector (hereinafter referred to as' second PD'), and the output of the replica delay cell may include a first the output (the 'V O, FR +') and second output (the 'V O, FR -') the output of said fifth delay cell number, and comprise a third output (the 'V O as a differential output , INJ + ') and the fourth output (the' V O, INJ - may comprise a ').

Wherein 1 PD is the V O, INJ + and the V O, the time which is located receives the FR + as the input to said second enable signal (EN PD) is the V O, the rising edge of the INJ + V O , INJ + and the phase difference between V O and FR + can be detected.

The second PD is the V O, INJ - and the V O, FR - for receiving as input the second enable signal (EN PD) the V O, INJ - when positioned on the rising edge the V O , INJ - and the phase difference of V O, FR- .

According to another aspect of the present invention, there is provided a method of controlling a frequency of a frequency-controlled oscillator (VCO) VCO ') with a target frequency, the CFS generating and transmitting a 4-bit digital code (COAR) to the VCO to adjust the current of the VCO, a pulse generator a first delay cell receiving a first enable signal EN FINE from the CFS, a fifth delay cell receiving an output of a fourth delay cell as an input, the PG receiving a reference pulse, And injecting the generated signal to the VCO.

The step of generating the reference pulse by the PG and injecting the reference pulse into the VCO may include injecting the reference pulse generated by the PG into the fifth delay cell to correct the phase of the fifth delay cell have.

The receiving of the output of the fourth delay cell by the fifth delay cell may include receiving an output of the fourth delay cell by a replica delay cell.

An injection locking clock multiplication method using a replica delay cell includes the steps of receiving an output of the fifth delay cell and an output of the replica delay cell using a dual edge phase detector (hereinafter, referred to as 'DEPD'), supplying a charge to the second enable signal receiving pass (EN PD), the method comprising the DEPD detects the phase difference between the VCO, charge pump (charge pump hereinafter 'CP') a capacitor (C L) or the capacitor And receiving charge from the capacitor C L.

The step of the DEPD detecting the phase difference of the VCO includes a step of receiving a first output (hereinafter referred to as' V o, FR + ') of the replica delay cell by a first phase detector (first PD' , The first PD receiving the third output (V O, INJ + ') of the fifth delay cell, the second enable signal (EN PD ) being applied to the rising edge of V O, INJ + And detecting the phase difference of V O, INJ + and V O, FR + when the first PD is located.

The step of detecting the phase difference of the VCO by the DEPD includes the step of receiving a second output (hereinafter referred to as' V O ' , FR- ') of the duplicate delay cell by a second phase detector , The second PD receiving a fourth output (V O, INJ- ') of the fifth delay cell, the second enable signal (EN PD ) receiving a rising edge of V O, INJ - And detecting the phase difference of the V O, INJ - and the V O, FR - when the first PD is located in the first PD.

A charge pump (Charge Pump hereinafter 'CP') is a capacitor stage that receives the charge in (C L) or to supply the electric charge from the capacitor (C L) by the CP regulates the control voltage (V FINE) in real time, the f VCO And the target frequency may be a product of the reference frequency f REF and the multiplication factor M, that is, M * f REF , and the multiplication factor may be arbitrary Lt; / RTI >

According to the injection locking clock multiplication apparatus and method using the duplication delay cell of the present invention described above and the injection locking clock multiplication apparatus and method using the duplication delay cell, the phase difference can be confirmed by the replication delay cell inside the VCO Since there is no need to add a separate VCO, power consumption is reduced and silicon area is reduced. It also has excellent jitter performance for PVT.

FIG. 1 is a reference diagram of a calibrating device which has a stable phase with respect to conventional PVT changes.
2 is a block diagram of an injection locking clock multiplication apparatus using a duplicate delay cell according to an embodiment of the present invention.
3 is a timing diagram illustrating an operation of an injection locking clock multiplication apparatus using a duplicate delay cell according to an embodiment of the present invention.
FIG. 4 is a configuration diagram of a part of an injection locking clock multiplication apparatus using a replication delay cell, which is an embodiment of the present invention.
5 is a timing diagram for the operation of the phase detector.
6 is a configuration diagram illustrating a relationship between a charge pump and a capacitor of an injection locking clock multiplication apparatus using a cloning delay cell according to an embodiment of the present invention.
7 is a flowchart of an injection locking clock multiplication method using a replication delay cell, which is an embodiment of the present invention.
FIG. 8 is a graph illustrating a jitter according to a temperature change of a calibration apparatus according to an embodiment of the present invention.
9 is a graph showing jitter according to a voltage change of a calibration apparatus according to an embodiment of the present invention.

It is to be understood that the words or words used in the present specification and claims are not to be construed in a conventional or dictionary sense and that the inventor can properly define the concept of a term in order to best describe the user's invention And should be construed in light of the meanings and concepts consistent with the technical idea of the present invention.

Throughout the specification, when a section includes a constituent element, it is understood that it can include other constituent elements, not excluding other constituent elements unless specifically stated otherwise.

Throughout the specification, when a section includes a constituent element, it is understood that it can include other constituent elements, not excluding other constituent elements unless specifically stated otherwise. It should be noted that the terms such as " part, "" module, " .

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In addition, when referring to the drawings throughout the specification, the estimated frequency selector is shown as five delay cells and one replica delay cell, but this is for convenience of description and does not limit the present invention.

FIG. 1 is a reference diagram of a calibrating device which has a stable phase with respect to conventional PVT changes.

1, in a conventional calibration apparatus, a first VCO (Voltage Controlled Ring Oscillator) receives an injection pulse generated by an injection pulse generator 120 and receives a signal fout = N * synchronized with a multiplication frequency of a reference clock, Fref) and divides the frequency output from the second VCO, which is the same as the first VCO, to receive the reference clock Fref and perform digital correction. Then, the control voltage of the first VCO and the second VCO So that a stable clock is generated in the multiplied high frequency and PVT (Process / Voltage / Temperature).

That is, in the case of the conventional calibrating apparatus, a second VCO equal to the first VCO and the first VCO is added to generate a stable clock in the PVT. As described above, there is a problem that the power consumption is large, , Mismatches between delay cells have the problem of limiting the correcting accuracy and requiring additional correction steps.

2 is a block diagram of an injection locking clock multiplication apparatus using a duplicate delay cell according to an embodiment of the present invention.

2, an injection locking clock multiplication apparatus using a replica delay cell according to an embodiment of the present invention includes an estimated frequency selector 100, a voltage controlled oscillator 200, a double edge phase detector 310, a charge pump 320, A capacitor 330, and a pulse generator 400.

More specifically, a ring-shaped voltage controlled oscillator (VCO) 200 includes at least one delay cell and a replica delay cell 260.

The input of the fifth delay cell 250 and the input of the replica delay cell 260 may be the output of the fourth delay cell 240.

More specifically, the input of the first delay cell 210 may be the output of the fifth delay cell 250. Here, the output of the fifth delay cell 250 is an output after the injection of the pulse generator 400, which will be described later.

The input of the second delay cell 220 is the output of the first delay cell 210 and the input of the third delay cell 230 is the output of the second delay cell 220, The input may be the output of the third delay cell 230.

The Coarse Frequency Selector (CFS ') 100 compares the free running frequency' f VCO 'of the voltage controlled oscillator 200 with a target frequency, Generates a digital code (COAR) and transmits the digital code (COAR) to the voltage-controlled oscillator 200 to adjust the current of the voltage-controlled oscillator 200.

Here, the target frequency is a product of the reference frequency f REF and the multiplication factor M, that is, M * f REF , and the multiplication factor M is an arbitrary constant.

A pulse generator (PG ') 400 receives the first enable signal EN FINE from the estimated frequency selector 100, generates a reference pulse, and injects the reference pulse into the voltage controlled oscillator 200 .

Up by the pump (Charge Pump 'CP') ( 320) is receiving supply a charge or supply the charge from the capacitor (C L) (330) to the capacitor (C L) (330), in real time, a control voltage (V FINE) Adjust the frequency of the voltage-controlled oscillator (f VCO ) Can be maintained at the multiplication factor M * reference frequency f REF .

The switch may be moved by the first enable signal EN FINE to connect the charge pump 320 or the initial voltage source V INIT to the capacitor C L 330.

More specifically, when the estimated frequency selector 100 frequently compares the frequency to the target frequency, the switch may be connected to the initial voltage V INIT so that the capacitor 330 can be charged by the initial voltage V INIT .

After the capacitor 330 is charged by the initial voltage V INIT , the estimated frequency selector 100 generates and transmits a 4-bit digital code COAR to the voltage controlled oscillator 200, (200).

Estimated frequency selector 100 is 4 bits after passing into a digital code (COAR) a voltage controlled oscillator 200 to generate the (bit), the first enable signal (EN FINE) is switched by moving the capacitor 330 by the The charge pump 320 can be connected.

The capacitor 330 and the charge pump 320 are connected to each other so that the control voltage V FINE can be increased or decreased by a V UP signal and a V DN signal to be described later.

The phase of the fifth delay cell 250 can be corrected when the pulse generator 400 injects the reference pulse into the fifth delay cell 250. [

A dual edge phase detector (DEPD ') 310 receives the output of the fifth delay cell 250 and the output of the duplicate delay cell 260.

The double edge phase detector 310 receives the second enable signal EN PD from the pulse generator 400 and detects the phase difference of the voltage controlled oscillator 200.

The output of the replica delay cell 260 may include a first output ('V 0, FR + ') and a second output ('V 0, FR- ') as a differential output, ('V O, INJ + ') and a fourth output ('V O, INJ - ') as the differential outputs.

3 is a timing diagram illustrating an operation of an injection locking clock multiplication apparatus using a duplicate delay cell according to an embodiment of the present invention.

More specifically, referring to FIG. 3, a reference pulse is injected into the voltage-controlled oscillator 200, thereby explaining how the phase difference is corrected.

In the case of a delay cell, since it is a commonly used device, a detailed description is omitted.

The input of the fifth delay cell 250 may be the output of the fourth delay cell 240 and the input of the replica delay cell 260 may also be the output of the fourth delay cell 240.

The output of the fourth delay cell 240 is a state in which a certain partial phase is changed by the delay through the first delay cell 210, the second delay cell 220 and the third delay cell 230.

However, since the fifth delay cell 250 receives the reference pulse from the pulse generator 400, the input received from the fourth delay cell 240 disappears.

Unlike the fifth delay cell 250, since the reference pulse is not injected from the pulse generator 400 in the case of the replica delay cell 260, the input received from the fourth delay cell 240 is maintained.

That is, referring to FIG. 3, it can be seen that the phase is different from the first in the case of V O, FR + , which is the first output of the duplication delay cell 260.

However , in the case of V O, INJ + which is the third output of the fifth delay cell 250, the reference pulse is injected from the pulse generator 400, so that it can be seen that there is no phase change.

Therefore, by comparing the first outputs V O, FR + of the replica delay cell 260 with the third outputs V O, INJ + of the fifth delay cell 250, it is possible to easily detect a phase change.

The charge pump 320 supplies the charge to the capacitor 330 or receives the charge from the capacitor 330 to adjust the control voltage V FINE in real time so that the frequency of the frequency control oscillator f VCO ) Can be maintained at the multiplication factor M * reference frequency f REF .

FIG. 4 is a configuration diagram of a part of an injection locking clock multiplication apparatus using a replication delay cell, which is an embodiment of the present invention.

5 is a timing diagram for the operation of the phase detector.

6 is a configuration diagram illustrating a relationship between a charge pump and a capacitor of an injection locking clock multiplication apparatus using a cloning delay cell according to an embodiment of the present invention.

4 to 6, the pulse generator 400 may receive the reference frequency f REF and the first enable signal EN FINE as inputs.

More specifically, when the pulse generator 400 receives the first enable signal EN FINE as an input, the switch is short-circuited to receive the reference frequency f REF as an input.

The reference frequency f REF may be input to the first buffer 410 and the first AND gate 440.

The output of the first buffer 410 may be input to the first inverter 420 and the second AND gate 450.

The output of the first inverter 420 may be input to the second buffer 430 and the second AND gate 450.

The output of the second buffer 430 may be input to a first AND gate 440.

The output of the first AND gate 440 may be input to the double edge phase detector 310 as a second enable signal EN PD .

The output of the second AND gate 450 may be input to the second inverter 460 and the pass gate 470.

The pass gate 470 can delay the output and input the same to the fifth delay cell 250 at the same time as the delay generated in the process of inverting and outputting the input of the second inverter 460.

That is, the pass gate 470 plays a role of delaying the input as a buffer and outputting it.

The dual edge phase detector 310 may include a first phase detector (first PD ') 311 and a second phase detector (second PD') 312.

The first phase detector 311 receives the first output (V O, FR + ) and the third output (V O, INJ + ) as inputs.

The first phase detector 311 receives the second enable signal EN PD from the pulse generator 400.

The first phase detector 311 detects the first output (V O, FR + ) and the third output (V O, IN + ) when the second enable signal EN PD is located at the rising edge of the third output V O, INJ + ) can be detected.

This can be confirmed through FIG. 5 (a).

The second phase detector 312 receives as inputs the second output (V O, FR - ) and the fourth output (V O, INJ - ).

The second phase detector 312 receives the second enable signal EN PD from the pulse generator 400.

A second phase detector (312) is a second enable signal (EN PD) has a fourth output (V O, INJ -) the second output (V O, FR -) when positioned on the rising edge of and a fourth output ( V O, INJ - ) can be detected.

This can be confirmed from FIG. 5 (b).

A first phase detector 311 has a first output (V O, FR +), a third output (V O, INJ +) and the second to the first UP signal when received the enable signal (EN PD) first To the OR gate 313.

In addition, the first phase detector 311 is a first DOWN signal when the input to the first output (V O, FR +), a third output (V O, INJ +) and the second enable signal (EN PD) To the second OR gate 314.

A second phase detector 312 is a second output (V O, FR -), the fourth output (V O, INJ -) and the second the second UP signal when received the enable signal (EN PD) first To the OR gate 313.

A second DOWN signal when transmitted to and the second enable signal (EN PD) In addition, the second phase detector 312 is a second output (V O, FR - -), the fourth output (V O, INJ) To the second OR gate 314.

The first OR gate 313 may deliver the V up signal to the charge pump 320 when it receives the first UP signal and the second UP signal.

In addition, the second OR gate 314 may deliver the V DN signal to the charge pump 320 upon receipt of the first DOWN signal and the second DOWN signal.

Referring to FIG. 6, when the V up signal is transferred to the charge pump 320, the first switch 322 may be SHORTed.

Accordingly, when the first switch 322 is SHORTed, the first current source 321 and the capacitor 330 are connected to each other so that the charge pump 320 can supply charge to the capacitor 330.

When charge is supplied to the capacitor 330 by the charge pump 320, the control voltage V FINE may increase.

The control voltage V FINE can be increased by the following equation (1).

Figure 112016015224791-pat00001

Also, V DN When the signal is transferred to the charge pump 320, the second switch 323 may be shorted.

Therefore, when the second switch 323 is shorted, the second current source 324 and the capacitor 330 are connected to each other so that the charge pump 320 can receive the charge from the capacitor 330. [

When charge is supplied to the charge pump 320 by the capacitor 330, the control voltage V FINE may decrease.

The control voltage V FINE can be reduced by the following equation (2).

Figure 112016015224791-pat00002

V up signal and V DN When the signal is simultaneously transferred to the charge pump 320, the first switch 322 and the second switch 323 can be simultaneously short-circuited.

At this time, the current of the first current source 321 flows to the second current source 324, and the control voltage V FINE will not change.

7 is a flowchart of an injection locking clock multiplication method using a replication delay cell, which is an embodiment of the present invention.

Referring to FIG. 7, a Coarse Frequency Selector (CFS ') 100 receives a free running frequency' f VCO 'of a voltage controlled oscillator ( VCO ) Is compared with a target frequency (S730)

Thereafter, the estimated frequency selector 100 generates a 4-bit digital code COAR and transmits it to the voltage controlled oscillator 200 to adjust the current of the voltage controlled oscillator 200. In operation S731,

More specifically, the estimated frequency selector 100 is capable of inputting a 4-bit digital code (COAR) to a switch that can control the current of the voltage-controlled oscillator 200.

The estimated frequency selector 100 can adjust the current of the voltage controlled oscillator 200 by inputting a 4-bit digital code (COAR) to a switch that can control the current of the voltage controlled oscillator 200.

The pulse generator 400 may receive the first enable signal EN FINE from the estimated frequency selector 100. In operation S732,

The fifth delay cell 250 may receive the output of the fourth delay cell 240 as an input (S733)

The replica delay cell 260 may receive the output of the fourth delay cell 240 as an input.

Thereafter, the pulse generator 400 generates a reference pulse and injects it into the voltage-controlled oscillator 200. (S734)

More specifically, the pulse generator 400 may generate a reference pulse and the pulse generator 400 may inject the generated reference pulse into the fifth delay cell 250 of the voltage-controlled oscillator 200.

When the reference pulse is injected into the fifth delay cell 250, the output of the fifth delay cell 250 according to the input received from the fourth delay cell 240 disappears and the phase can be corrected to the output of the reference pulse .

The dual edge phase detector 310 may receive the output of the fifth delay cell 250 and the output of the duplicate delay cell 260 calibrated by the reference pulse.

In addition, the double edge phase detector 310 may receive the second enable signal EN PD from the pulse generator 400.

Then, the double edge phase detector 310 can detect the phase difference of the voltage controlled oscillator 200 (S735)

More specifically, a first phase detector (first PD ') 311 may receive the first output (V O, FR + ) of the replica delay cell 260 and a first phase detector Detector 'first PD') 311 may receive the third output ('V O, INJ + ') of the fifth delay cell 250.

Reference pulse by a third output ( 'V O, INJ +' ) of the time which is located on the rising edge the first output (V O, FR +) and the third output of the phase difference between the first of the ( 'V O, INJ +' ) The phase detector 311 can detect it.

Also, a second phase detector (second PD ') 312 may receive the second output (' V O, FR - ') of the replica delay cell 260 and a second phase detector Detector 'second PD') 312 may receive the fourth output ('V O, INJ - ') of the fifth delay cell 20.

The phase difference of - ( 'V O, INJ' ) - based on the fourth output pulse ( 'V O, INJ') the rising time which is located on the edge the second output ( 'V O, FR-') and the fourth output of the Can be detected by the second phase detector 312.

The charge pump 320 can adjust the control voltage V FINE in real time so that the frequent frequency f VCO can be maintained to match the target frequency (S736)

The target frequency may be a product of the reference frequency (f REF ) and the multiplication factor (M), i.e., M * f REF , where the multiplication factor may be any constant.

FIG. 8 is a graph illustrating a jitter according to a temperature change of a calibration apparatus according to an embodiment of the present invention.

Referring to FIG. 8, when a calibrator according to an exemplary embodiment of the present invention is turned on and off, a jitter change amount DELTA Jitter with respect to a temperature change Show.

According to FIG. 8, when the calibrator is not operated (off), it can be seen that the amount of jitter variation increases as the temperature increases. On the other hand, when the calibrator is turned on, It can be seen that the jitter variation is constant.

Therefore, according to an embodiment of the present invention, it can be seen that the amount of change in jitter is constant despite the temperature change.

9 is a graph showing jitter according to a voltage change of a calibration apparatus according to an embodiment of the present invention.

9, when the calibrator according to the embodiment of the present invention is turned on and off, the amount of change in jitter with respect to the change in the supply voltage ).

According to FIG. 9, when the calibrator is not operated (OFF), when the supply voltage is higher than 1.08 V and less than 1.11 V, the jitter variation is constant, but when the voltage is lower than 1.08 V and 1.11 V, .

However, when the calibrator is turned on, it can be seen that the jitter variation is constant regardless of the range of the supply voltage.

Therefore, it can be seen that, according to an embodiment of the present invention, the amount of change in jitter is constant despite the change in the supply voltage.

As described above, the configuration and operation of the injection locking clock multiplication apparatus and method using the replication delay cell according to the embodiment of the present invention can be performed. While the embodiments of the present invention have been described with reference to specific embodiments, And can be practiced without departing from the scope of the invention.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various modifications and changes may be made by those skilled in the art.

100: Estimated frequency selector 200: Voltage controlled oscillator
210: first delay cell 220: second delay cell
230: third delay cell 240: fourth delay cell
250: fifth delay cell 260: replication delay cell
300: frequency tracking loop 310: dual edge phase detector
311: first phase detector 312: second phase detector
320: charge pump 330: capacitor
400: Pulse generator

Claims (15)


A Voltage Controlled Oscillator (VCO) having at least one delay cell and a replica delay cell;
Compares a free running frequency 'f VCO ' of the VCO with a target frequency, generates a 4-bit digital code (COAR), and transmits the generated digital code to the VCO, A Coarse Frequency Selector (CFS);
A pulse generator (hereinafter referred to as 'PG') that receives the first enable signal EN FINE from the CFS and generates a reference pulse and injects the reference pulse into the VCO;
A fifth delay output, and receiving transmit an output of the replica delay cell in the cell, delivering the second enable signal (EN PD) from the PG receive dual edge phase detector for detecting a phase difference between the VCO (Dual Edge Phase Detector below 'DEPD');
/ RTI >
The target frequency is
Is made up of the product of the reference frequency f REF and the multiplication factor M, that is, M * f REF ,
Wherein the multiplication factor is an arbitrary constant. ≪ RTI ID = 0.0 > 16. < / RTI >

The method according to claim 1,
Capacitor by receiving supply of electric charge to (C L) or to supply the electric charge from the capacitor (C L), to adjust a control voltage (V FINE) in real time, the f VCO And a charge pump (hereinafter, referred to as 'CP') for maintaining the value of M * f REF at the value of M * f REF .

The method according to claim 1,
And the input of the fifth delay cell and the input of the replica delay cell are the outputs of the fourth delay cell.

The method according to claim 1,
Wherein the reference pulse generated by the PG is injected into the fifth delay cell to correct the phase of the fifth delay cell.

The method according to claim 1,
The DEPD
A first phase detector (hereinafter, referred to as a 'first PD') and a second phase detector (hereinafter referred to as a 'second PD'),
The output of the replica delay cell includes a first output (hereinafter referred to as' V 0 ' , FR + ') and a second output (hereinafter referred to as' V 0, FR- ') as a differential output,
Wherein the output of the fifth delay cell includes a third output (hereinafter , referred to as 'V o, INJ + ') and a fourth output (hereinafter referred to as 'V o, INJ- ') as a differential output. Locking clock multiplication device.

6. The method of claim 5,
Wherein 1 PD is the V O, INJ + and the V O, receives the FR + to enter the second enable signal (EN PD) is the V O, when positioned in the V O, the rising edge of the INJ +, INJ + and And detects the phase difference of V O and FR + .

6. The method of claim 5,
The second PD is the V O, V O and the INJ-, receiving as input the FR- the second enable signal (EN PD) is the time V O which is located in the V O, the rising edge of INJ- , INJ-, and V O, FR- are detected based on the detected phase difference.

The coarse frequency selector (CFS) compares the free running frequency (f VCO ) of the voltage controlled oscillator ( VCO ) with the target frequency ;
Adjusting the current of the VCO by generating a 4-bit digital code (COAR) by the CFS and transferring the COAR to the VCO;
Receiving a first enable signal (EN FINE ) from the CFS by a pulse generator (PG);
The fifth delay cell receiving the output of the fourth delay cell as an input;
Generating a reference pulse by the PG and injecting the reference pulse into the VCO;
A dual edge phase detector (DEPD ') receiving an output of the fifth delay cell and an output of a replica delay cell;
Receiving from the PG the DEPD a second enable signal (EN PD );
The DEPD detecting a phase difference of the VCO;
A charge pump receiving the supply of charge to the capacitor (C L) (Charge Pump hereinafter 'CP') or to supply the electric charge from the capacitor (C L);
, ≪ / RTI &
The step of the PG generating and injecting a reference pulse into the VCO
The reference pulse generated by the PG is injected into the fifth delay cell to correct the phase of the fifth delay cell;
Lt; / RTI >
And the fifth delay cell receiving the output of the fourth delay cell as an input
The replica delay cell receiving an output of the fourth delay cell as an input;
And a replica delay cell including the replica delay cell.

9. The method of claim 8,
The step of the DEPD detecting the phase difference of the VCO
A first phase detector (hereinafter referred to as a first PD) receives a first output (hereinafter , referred to as 'V 0 ' and ' FR + ') of the replication delay cell;
The first PD receiving the third output of the fifth delay cell (hereinafter, 'V O, INJ + '), and
The first step of the V O, INJ + and the V O, wherein the 1 PD of the phase difference between FR + is detected when positioned in the second enable signal (EN PD) is the V O, the rising edge of the INJ +;
And a replica delay cell including the replica delay cell.

9. The method of claim 8,
The step of the DEPD detecting the phase difference of the VCO
A second phase detector (hereinafter, referred to as 'second PD') receives a second output (hereinafter referred to as 'V 0 ' and ' FR- ') of the replication delay cell;
The second PD receiving a fourth output of the fifth delay cell (hereinafter referred to as 'V O, INJ- ');
Detecting the phase difference between V O, INJ- and V O, FR- when the second enable signal EN PD is located at the rising edge of V O, INJ- ;
And a replica delay cell including the replica delay cell.

9. The method of claim 8,
A charge pump receiving the supply of charge to the capacitor (C L) (Charge Pump hereinafter 'CP') or to supply the electric charge from the capacitor (C L) is
Controlling the control voltage (V FINE ) in real time so that the f VCO coincides with the target frequency;
/ RTI >
The target frequency is
Is made up of the product of the reference frequency f REF and the multiplication factor M, that is, M * f REF ,
Wherein the multiplication factor is an arbitrary constant. 2. The injection locking clock multiplication method according to claim 1, wherein the multiplication factor is an arbitrary constant. delete delete delete delete
KR1020160017772A 2016-02-16 2016-02-16 Injection locked clock multiplication apparatus and method using a replica delay cell KR101724365B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020160017772A KR101724365B1 (en) 2016-02-16 2016-02-16 Injection locked clock multiplication apparatus and method using a replica delay cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160017772A KR101724365B1 (en) 2016-02-16 2016-02-16 Injection locked clock multiplication apparatus and method using a replica delay cell

Publications (1)

Publication Number Publication Date
KR101724365B1 true KR101724365B1 (en) 2017-04-07

Family

ID=58583570

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160017772A KR101724365B1 (en) 2016-02-16 2016-02-16 Injection locked clock multiplication apparatus and method using a replica delay cell

Country Status (1)

Country Link
KR (1) KR101724365B1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004235842A (en) * 2003-01-29 2004-08-19 Renesas Technology Corp Phase locked loop circuit
KR100825800B1 (en) * 2007-02-12 2008-04-29 삼성전자주식회사 Wide range multi-phase delay locked loop circuit including delay matrix
KR20080088250A (en) * 2007-03-29 2008-10-02 고려대학교 산학협력단 Apparatus and method for dll-based frequency multiplier with self-calibration
KR20120044061A (en) * 2010-10-27 2012-05-07 에스케이하이닉스 주식회사 Delay locked loop and integrated circuit including the same
KR101548256B1 (en) 2013-09-17 2015-08-28 국립대학법인 울산과학기술대학교 산학협력단 Apparatus for pvt variation calibration of ring osc based on injection locking system and the method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004235842A (en) * 2003-01-29 2004-08-19 Renesas Technology Corp Phase locked loop circuit
KR100825800B1 (en) * 2007-02-12 2008-04-29 삼성전자주식회사 Wide range multi-phase delay locked loop circuit including delay matrix
KR20080088250A (en) * 2007-03-29 2008-10-02 고려대학교 산학협력단 Apparatus and method for dll-based frequency multiplier with self-calibration
KR20120044061A (en) * 2010-10-27 2012-05-07 에스케이하이닉스 주식회사 Delay locked loop and integrated circuit including the same
KR101548256B1 (en) 2013-09-17 2015-08-28 국립대학법인 울산과학기술대학교 산학협력단 Apparatus for pvt variation calibration of ring osc based on injection locking system and the method thereof

Similar Documents

Publication Publication Date Title
US9628094B2 (en) Apparatus and method for fast phase locking for digital phase locked loop
US9722618B1 (en) Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features
US8901976B2 (en) Synchronizing circuit and clock data recovery circuit including the same
Choi et al. 10.7 A 185fsrms-integrated-jitter and− 245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector
US7920000B2 (en) PLL circuit and method of controlling the same
TWI684327B (en) Device and method for adjusting duty cycle in clock signals
US8686768B2 (en) Phase locked loop
US6859079B2 (en) Semiconductor device capable of accurately producing internal multi-phase clock signal
US7501900B2 (en) Phase-locked loop bandwidth calibration
US20040251970A1 (en) Method for clock generator lock-time reduction during speedstep transition
US9432028B2 (en) Clock data recovery circuit and a method of operating the same
US7489168B2 (en) Clock synchronization apparatus
KR20100052079A (en) Duty cycle correction circuit and delay locked loop circuit including the same
KR20080011527A (en) Clock and data recovery circuit and controlling method of the same
KR101724365B1 (en) Injection locked clock multiplication apparatus and method using a replica delay cell
KR20150044617A (en) Apparatus for pvt varactor calibration of frequency multiplier based on injection locking system and the method thereof
US20090189650A1 (en) PLL circuit including voltage controlled oscillator having voltage-current conversion circuit
US10014866B2 (en) Clock alignment scheme for data macros of DDR PHY
KR20140090455A (en) Phase locked loop circuit
TWI500269B (en) Phase locked loop with current compensationmechanism and method thereof
JP4534140B2 (en) PLL circuit
Gimeno et al. Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI
CN106941352B (en) Calibration method and circuit for oscillator output frequency signal
JP6469474B2 (en) PLL circuit and control method thereof
US20070285180A1 (en) Wide tuning range and low jitter voltage controlled oscillator

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant