KR20150030087A - Liquid Crystal Display Device And Method Of Driving The Same - Google Patents
Liquid Crystal Display Device And Method Of Driving The Same Download PDFInfo
- Publication number
- KR20150030087A KR20150030087A KR20130109319A KR20130109319A KR20150030087A KR 20150030087 A KR20150030087 A KR 20150030087A KR 20130109319 A KR20130109319 A KR 20130109319A KR 20130109319 A KR20130109319 A KR 20130109319A KR 20150030087 A KR20150030087 A KR 20150030087A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- signal
- liquid crystal
- data
- voltage
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
Landscapes
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
Description
The present invention relates to a liquid crystal display device, and more particularly, to a method of driving a liquid crystal display device using a gate signal having a gate low voltage gradually decreasing corresponding to a resistance of a gate wiring.
The display devices are mainly composed of a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED).
In this case, the liquid crystal display device is driven by using the optical anisotropy and polarization properties of the liquid crystal. Since the liquid crystal molecules have a long structure, the liquid crystal molecules have a directional arrangement, and an electric field is artificially applied to the liquid crystal to control the orientation can do.
That is, when the arrangement of the liquid crystal molecules is changed by using the electric field, the light is refracted in the arrangement direction of the liquid crystal molecules due to the optical anisotropy of the liquid crystal, and an image can be displayed.
In recent years, an active matrix liquid crystal display (AM-LCD) device in which a thin film transistor and a pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video realization capability. The apparatus will be described with reference to the drawings.
1 is a view showing a conventional liquid crystal display device.
1, the conventional liquid
The
The
First to m-th gate lines GL1 to GLm and first to n-th data lines DL1 to DLn are formed on the first substrate of the
Although not shown, a black matrix, a color filter layer, and a common electrode are sequentially stacked on a second substrate of the
The
The
The
The
The
The
The non-display area (NDA) serves as a failure factor for expanding the bezel of the liquid crystal display device (10).
In order to achieve a narrow bezel by minimizing the area of the non-display area NDA, a gate driver for both sides of the liquid crystal panel is omitted, and a gate signal and a data signal are generated by an integrated driver on the top of the liquid crystal panel. A display device has been proposed.
In such a liquid crystal display device, vertical gate wirings are formed in the longitudinal direction of the liquid crystal panel in order to transfer gate signals from the integrated driver on the liquid crystal panel to the horizontal gate wirings formed in the lateral direction of each liquid crystal panel.
However, the length of the vertical gate wiring varies depending on the position of the horizontal gate wiring, and a deviation occurs in the delay of the gate signal due to the difference in resistance due to the difference in length of the vertical gate wiring.
Such a delay deviation of the gate signal hinders normal driving of the liquid crystal panel and increases the dispersion by making the variation (? Vp) of the pixel voltage of the pixel electrode connected to the thin film transistor uneven, thereby increasing the dispersion of the variation of the pixel voltage .
2A and 2B are diagrams showing a delay time of a gate signal of a conventional liquid crystal display device. FIG. 2A shows a gate signal output from the integrated driver, and FIG. 2C shows the gate signal at the lower end of the liquid crystal panel remote from the integrated driver.
2A, the gate signal output from the integrated driver increases from the first voltage V1 to the second voltage V2 at the first time point t1 and is maintained until the second time point t2, Is a square wave that decreases from the second voltage (V2) to the first voltage (V1) at the second time point (t2).
The gate signal is transmitted through the vertical gate line, and the falling time is increased due to the delay due to the resistance of the vertical gate line. As shown in FIG. 2B, at the upper portion of the liquid crystal panel, The first voltage V1 is reached at a third time point t3 later than the second time point t2 due to the resistance, and as shown in Fig. 2C, at the lower end portion of the liquid crystal panel, And reaches the first voltage V1 at the fourth time point t4 later than the third time point t3.
That is, the falling time (t3-t2) of the gate signal at the upper end of the liquid crystal panel and the falling time (t4-t2) of the gate signal at the lower end of the liquid crystal panel are different from each other. As a result, The variation of the proportional pixel voltage variation (? Vp = (Cgd / Clc + Cst + Cgd) * (? Vg)) increases and the quality of the image displayed by the liquid crystal display device decreases.
SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and it is an object of the present invention to provide a method of driving a liquid crystal display which reduces a delay of a gate signal by using two kinds of gate low voltages.
Another object of the present invention is to provide a method of driving a liquid crystal display device that minimizes delayed scattering of a gate signal by using a gate-low voltage gradually decreasing corresponding to a resistance of a vertical gate wiring.
According to an aspect of the present invention, there is provided an image processing apparatus including a drive control unit for generating a gate control signal, a data control signal, and image data using a video signal and a plurality of timing signals; An integrated driver for generating a gate signal and a data signal using the gate control signal, the data control signal, and the image data; First to mth horizontal gate wirings and first to nth data wirings for displaying an image using the gate signal and the data signal and forming pixel regions to intersect with each other, And the first to the n-th data lines, the gate signal having a gate high voltage in a period between a rising time point and a falling time point, And has a first gate low voltage in an under-driving interval after the falling point, and a second gate low voltage in a period after the under-driving interval.
The first gate-low voltage may gradually decrease corresponding to the resistances of the first through the n-th vertical gate wirings.
The difference between the first and second gate-low voltages may be less than or equal to the difference between the second gate-low voltage and the gate-high voltage.
The width of the under-driving section may be different depending on the resistance of the first to the n-th vertical gate wirings.
According to another aspect of the present invention, there is provided a method of driving a plasma display panel, including: generating a gate control signal, a data control signal, and image data using a video signal and a plurality of timing signals; An integrated driver generating a gate signal and a data signal using the gate control signal, the data control signal, and the image data; First to m-th horizontal gate wirings, first to n-th data wirings, and first to m-th horizontal gate wirings which cross each other to form a pixel region and are connected in parallel Wherein the liquid crystal panel including the first to nth vertical gate wirings spaced apart from each other includes an image display using the gate signal and the data signal, And a first gate low voltage in an under-driving period after the falling point and a second gate low voltage in a period after the under-driving period. The driving method of a liquid crystal display device according to claim 1, to provide.
The first gate-low voltage may gradually decrease corresponding to the resistances of the first through the n-th vertical gate wirings.
The difference between the first and second gate-low voltages may be less than or equal to the difference between the second gate-low voltage and the gate-high voltage.
The width of the under-driving section may be different depending on the resistance of the first to the n-th vertical gate wirings.
In the present invention, the effect of reducing the delay of the gate signal by first outputting a relatively low first gate low voltage and then outputting a relatively high second gate low voltage to under-drive the gate signal have.
Further, there is an effect that the delayed scattering of the gate signal in the liquid crystal panel is minimized by outputting the first gate-low voltage gradually decreasing in correspondence with the resistance of the vertical gate wiring to under-drive the gate signal.
1 is a view showing a conventional liquid crystal display device.
2A to 2C are diagrams showing a degree of delay of a gate signal of a conventional liquid crystal display device.
3 is a view illustrating a liquid crystal display device according to a first embodiment of the present invention.
4 is a diagram showing a gate signal of a liquid crystal display device and a voltage used for generating a gate signal according to the first embodiment of the present invention.
5A to 5C are diagrams showing the degree of delay of the gate signal of the liquid crystal display device according to the first embodiment of the present invention.
6 is a view showing a gate signal of a liquid crystal display device and a voltage used for generating a gate signal according to a second embodiment of the present invention;
7A to 7D are diagrams showing the degree of delay of the gate signal of the liquid crystal display device according to the second embodiment of the present invention.
Hereinafter, a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.
3 is a view illustrating a liquid crystal display device according to a first embodiment of the present invention.
3, the liquid
The
The
First to mth horizontal gate lines GLH1 to GLHm and first to nth data lines DL1 to DLn are formed on the first substrate of the
The vertical gate wirings GLV1 to GLVn which are not connected to the horizontal gate wirings GLH1 to GLHm when the number of the vertical gate wirings GLV1 to GLVn is larger than the number of the horizontal gate wirings GLH1 to GLHm (m> n) And the vertical gate lines GLV1 to GLVn may be used for signal transmission such as a common voltage.
In each pixel region P, a thin film transistor (TFT) T connected to the horizontal gate lines GLH1 to GLHm and the data lines DL1 to DLn is formed. In the thin film transistor T, A storage capacitor Cst and a liquid crystal capacitor Clc may be connected.
Although not shown, a black matrix, a color filter layer, and a common electrode are sequentially stacked on a second substrate of the
The liquid crystal layer between the pixel electrode, the common electrode, the pixel electrode, and the common electrode connected to the thin film transistor T constitutes a liquid crystal capacitor Clc.
The
The gate signal generated in the
The
Here, the first and second
On the other hand, in another embodiment, the integrated driver may be configured as an integrated integrated circuit that is mounted on a film and a film and generates a gate signal and a data signal.
The driving
For example, the driving
The driving
On the other hand, the
In the liquid
Accordingly, the non-display area NDA of the
In this liquid
The delay reduction of the gate signal due to under-driving will be described with reference to the drawings.
4A and 4B are diagrams illustrating gate signals and voltages used for generating a gate signal of the liquid crystal display device according to the first embodiment of the present invention, and FIGS. 5A to 5C are cross-sectional views of the liquid crystal display device according to the first embodiment of the present invention. FIG. 3 is a diagram showing the degree of delay of a gate signal.
5A shows the gate signal Vg output from the
4, the shift register of the
Specifically, the shift register of the
During one frame, the first gate low voltage VGL1 is maintained at the first voltage V1 and the second gate low voltage VGL2 is maintained at the second voltage V2 which is higher than the first voltage V1. And the gate high voltage VGH is kept constant at the third voltage V3 which is larger than the second voltage V2.
Therefore, the gate signal Vg generated by using the first and second gate low voltages VGL1 and VGL2 and the gate high voltage VGH has the same shape for one frame and is output from the
The gate signal Vg output in the same form is delayed differently from each other while being transmitted through the first to nth vertical gate wirings GLV1 to GLVn to form the first to nth horizontal gate wirings GLH1 to GLHm, They have different shapes.
5A, the gate signal Vg output from the
The gate signal Vg is transmitted through the first to the n-th vertical gate lines GLV1 to GLVn and is delayed by the resistance of the first to the n-th vertical gate lines GLV1 to GLVn to generate a falling time As shown in FIG. 5B, at the upper end of the
That is, by using the first gate low voltage VGL1 of the first voltage V1 which is smaller than the second voltage V2 during the under driving period (the interval between t2 and t3) which is the initial stage of the fall of the gate signal Vg, The falling time t4-t2 of the gate signal Vg at the upper end of the
Here, the first voltage V1 of the first gate low voltage VGL1, the second voltage V2 of the second gate low voltage VGL2, and the third voltage V3 of the gate high voltage VGH, The difference V2-V1 between the first and second voltages V1 and V2 may be determined in accordance with the specifications of the
In the first embodiment, the under-driving periods t2 to t3, to which the first gate low voltage VGL1 of the first voltage V1 is applied, are applied to the first to nth horizontal gate lines GLH1 to GLHm Driving periods t2 to t3 are equal to the resistances of the first to nth vertical gate wirings GLV1 to GLVn (i.e., the first to nth horizontal gate wirings GLH1 to GLHm) The position of the light emitting diode (LED). For example, the under-driving period t2 to t3 may have a gradually decreasing or increasing width corresponding to the first to nth horizontal gate lines GLH1 to GLHm.
The width of the under-driving period t2 to t3 may be equal to or less than three times the width of the gate high section t1 to t2 between the rising time point and the falling time point at which the gate high voltage VGH is output ((t3- t2)? 3X (t2-t1)).
Table 1 shows the falling time of the pixel voltage variation amount? Vp and the gate signal Vg in the liquid crystal display device according to the first and second embodiments of the present invention and the conventional liquid crystal display device.
As shown in Table 1, in the liquid
On the other hand, in the conventional liquid crystal display device, the fall time of the gate signal Vg in the two pixel regions P1 and P2 connected to the first gate wiring GL1 is 0.76 mu sec and 0.91 mu sec, The fall time of the gate signal Vg in the two pixel regions P3 and P4 connected to the gate wiring GLH is 3.64 mu sec and 3.64 mu sec respectively and the fall time of the gate signal Vg is 2.88 mu sec .
That is, the fall time of the gate signal Vg at the upper end and the lower end of the
In the liquid
On the other hand, in the conventional liquid crystal display device, the pixel voltage variation amounts of the two pixel regions P1 and P2 connected to the first gate wiring GL1 are 0.549 V and 0.531 V, respectively, The pixel voltage variation amounts of the two pixel regions P3 and P4 to be connected are 0.450 V and 0.446 V, respectively, and the variation of the pixel voltage variation is 0.103 V.
That is, the pixel voltage fluctuation amounts at the upper and lower ends of the
This is because the variation amount? Vg of the gate signal Vg is increased by the first gate low voltage VGL1 at the upper end of the
The first gate low voltage VGL1 used for generating the gate signal may be gradually reduced according to the pixel region P in order to reduce the dispersion of the pixel voltage variation, which will be described with reference to the drawings.
FIG. 6 is a view showing a gate signal and a voltage used for generating a gate signal in the liquid crystal display device according to the second embodiment of the present invention, and FIGS. 7a to 7d are cross-sectional views of the liquid crystal display device according to the second embodiment of the present invention. The liquid crystal display device of the second embodiment has the same configuration as that of the liquid crystal display device of the first embodiment and will be described with reference to FIG.
7A shows a gate signal Vg output from the
6, the shift register of the
Specifically, the shift register of the
During one frame, the first gate low voltage VGL1 gradually decreases from the second voltage V2 to the first voltage V1, and the second gate low voltage VGL2 is lower than the first voltage V1 And the gate high voltage VGH is held constant at the third voltage V3 which is larger than the second voltage V2.
For example, the first gate-low voltage VGL1 is applied to the first to the n-th vertical gate lines GLV1 to GLVn according to the resistance of the first to the n-th horizontal gate lines GLH1 to GLHm Can be linearly decreased from the voltage V2 to the first voltage V1.
Accordingly, the gate signal Vg generated by using the first and second gate low voltages VGL1 and VGL2 and the gate high voltage VGH is different from each other for one frame and output from the
However, the gate signals Vg output in different forms are delayed differently from each other while being transmitted through the first to the n-th vertical gate wirings GLV1 to GLVn, The first to nth horizontal gate lines GLH1 to GLHm have a similar shape to each other.
7A, the gate signal Vg output from the
7B, the gate signal Vg output from the
The gate signal Vg is transmitted through the first to the n-th vertical gate lines GLV1 to GLVn and is delayed by the resistance of the first to the n-th vertical gate lines GLV1 to GLVn to generate a falling time As shown in FIG. 7C, at the upper end of the
That is, during the period of the under-driving interval t2 and t3 during the falling period of the gate signal Vg, the first to the n-th vertical gate lines GLV1 to GLVn, The falling time t4-t2 of the gate signal Vg at the upper end of the
Here, the first voltage V1 of the first gate low voltage VGL1, the second voltage V2 of the second gate low voltage VGL2, and the third voltage of the gate high voltage VGH are supplied to the
In the second embodiment, the under-driving periods t2 to t3 to which the first gate low voltage VGL1 of the first voltage V1 is applied are the same for the first to nth horizontal gate lines GLH1 to GLHm Driving periods t2 to t3 are equal to the resistances of the first to nth vertical gate wirings GLV1 to GLVn (i.e., the first to nth horizontal gate wirings GLH1 to GLHm) The position of the light emitting diode (LED). For example, the under-driving period t2 to t3 may have a gradually decreasing or increasing width corresponding to the first to nth horizontal gate lines GLH1 to GLHm.
The width of the under-driving period t2 to t3 may be equal to or less than three times the width of the gate high section t1 to t2 between the rising time point and the falling time point at which the gate high voltage VGH is output ((t3- t2)? 3X (t2-t1)).
As shown in Table 1, in the liquid
That is, the fall time of the gate signal Vg at the upper end of the
In the liquid
That is, the pixel voltage fluctuation amount at the upper end of the
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that
110: liquid crystal display device 120: liquid crystal panel
130: Integrated driver 140:
VGL1: first gate low voltage VGL2: second gate low voltage
VGH: Gate high voltage
Claims (8)
An integrated driver for generating a gate signal and a data signal using the gate control signal, the data control signal, and the image data;
First to mth horizontal gate wirings and first to nth data wirings for displaying an image using the gate signal and the data signal and forming pixel regions to intersect with each other, And the first to the n-th data lines and the first to the n-th vertical data lines,
/ RTI >
Wherein the gate signal has a gate high voltage in a period between a rising time point and a falling time point and has a first gate low voltage in an under driving period after the falling time point and a second gate low voltage in a period after the under- And a liquid crystal display device.
And the first gate-low voltage gradually decreases corresponding to the resistances of the first through n-th vertical gate wirings.
Wherein a difference between the first and second gate-low voltages is equal to or less than a difference between the second gate-low voltage and the gate-high voltage.
And the width of the under-driving section is different depending on the resistances of the first to the n-th vertical gate wirings.
An integrated driver generating a gate signal and a data signal using the gate control signal, the data control signal, and the image data;
First to m-th horizontal gate wirings, first to n-th data wirings, and first to m-th horizontal gate wirings which cross each other to form a pixel region and are connected in parallel A liquid crystal panel including first to n-th vertical gate wirings spaced apart from each other, the method comprising: displaying an image using the gate signal and the data signal
Lt; / RTI >
Wherein the gate signal has a gate high voltage in a period between a rising time point and a falling time point and has a first gate low voltage in an under driving period after the falling time point and a second gate low voltage in a period after the under- A method of driving a liquid crystal display device having a voltage.
Wherein the first gate-low voltage is gradually decreased corresponding to the resistance of the first to the n-th vertical gate wirings.
Wherein a difference between the first gate low voltage and the second gate low voltage is equal to or less than a difference between the second gate low voltage and the gate high voltage.
And the width of the under-driving section is different depending on the resistances of the first to the n-th vertical gate wirings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020130109319A KR102049738B1 (en) | 2013-09-11 | 2013-09-11 | Liquid Crystal Display Device And Method Of Driving The Same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020130109319A KR102049738B1 (en) | 2013-09-11 | 2013-09-11 | Liquid Crystal Display Device And Method Of Driving The Same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20150030087A true KR20150030087A (en) | 2015-03-19 |
| KR102049738B1 KR102049738B1 (en) | 2019-11-28 |
Family
ID=53024279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020130109319A KR102049738B1 (en) | 2013-09-11 | 2013-09-11 | Liquid Crystal Display Device And Method Of Driving The Same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR102049738B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210035839A (en) * | 2019-08-20 | 2021-04-01 | 에이유 오프트로닉스 코퍼레이션 | Display device |
| US11295690B2 (en) | 2020-02-18 | 2022-04-05 | Samsung Display Co., Ltd. | Display device to improve display quality while minimizing bezel area |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070028063A (en) * | 2005-09-07 | 2007-03-12 | 비오이 하이디스 테크놀로지 주식회사 | Liquid crystal display |
| JP2008058357A (en) * | 2006-08-29 | 2008-03-13 | Sharp Corp | Active matrix substrate and display device with same |
| JP2010072363A (en) * | 2008-09-18 | 2010-04-02 | Toshiba Mobile Display Co Ltd | Liquid crystal display device |
| KR20110038318A (en) * | 2009-10-08 | 2011-04-14 | 엘지디스플레이 주식회사 | Array substrate and liquid crystal display device including the same |
| KR20120041570A (en) * | 2010-10-21 | 2012-05-02 | 엘지디스플레이 주식회사 | Display device and method of controlling gate pulse thereof |
| KR20120073824A (en) * | 2010-12-27 | 2012-07-05 | 엘지디스플레이 주식회사 | Liquid crystal display device |
-
2013
- 2013-09-11 KR KR1020130109319A patent/KR102049738B1/en active IP Right Grant
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070028063A (en) * | 2005-09-07 | 2007-03-12 | 비오이 하이디스 테크놀로지 주식회사 | Liquid crystal display |
| JP2008058357A (en) * | 2006-08-29 | 2008-03-13 | Sharp Corp | Active matrix substrate and display device with same |
| JP2010072363A (en) * | 2008-09-18 | 2010-04-02 | Toshiba Mobile Display Co Ltd | Liquid crystal display device |
| KR20110038318A (en) * | 2009-10-08 | 2011-04-14 | 엘지디스플레이 주식회사 | Array substrate and liquid crystal display device including the same |
| KR20120041570A (en) * | 2010-10-21 | 2012-05-02 | 엘지디스플레이 주식회사 | Display device and method of controlling gate pulse thereof |
| KR20120073824A (en) * | 2010-12-27 | 2012-07-05 | 엘지디스플레이 주식회사 | Liquid crystal display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210035839A (en) * | 2019-08-20 | 2021-04-01 | 에이유 오프트로닉스 코퍼레이션 | Display device |
| US11295690B2 (en) | 2020-02-18 | 2022-04-05 | Samsung Display Co., Ltd. | Display device to improve display quality while minimizing bezel area |
Also Published As
| Publication number | Publication date |
|---|---|
| KR102049738B1 (en) | 2019-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102146828B1 (en) | Display device | |
| US9870747B2 (en) | Display device | |
| US9398687B2 (en) | Display device including line on glass | |
| US8345026B2 (en) | Display apparatus | |
| US10235955B2 (en) | Stage circuit and scan driver using the same | |
| KR101351381B1 (en) | Liquid crystal display and apparatus for driving the same | |
| JP2008116964A (en) | Liquid crystal display device and method of driving the same | |
| JP2010055059A (en) | Display device | |
| KR20150060360A (en) | Display device | |
| US8717271B2 (en) | Liquid crystal display having an inverse polarity between a common voltage and a data signal | |
| KR20160002511A (en) | Display device | |
| US20170154595A1 (en) | Display device | |
| KR20090082751A (en) | Liquid crystal display appartus | |
| CN105741732B (en) | Gate drivers, the display device with gate drivers and its driving method | |
| KR102394393B1 (en) | Display device | |
| KR101244773B1 (en) | Display device | |
| JP2014085661A (en) | Display device | |
| KR102049738B1 (en) | Liquid Crystal Display Device And Method Of Driving The Same | |
| KR102180914B1 (en) | Display device | |
| US20130278570A1 (en) | Gate driving circuit and display apparatus having the same | |
| KR102411379B1 (en) | Display panel and display device using the same | |
| KR101761407B1 (en) | Liquid Crystal Display Device | |
| KR101384014B1 (en) | Liquid crystal display | |
| KR101265087B1 (en) | Liquid crystal display device | |
| KR101268390B1 (en) | Driving apparatus for liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right |