KR20140141296A - Gate driver and liquid crystal display device inculding thereof - Google Patents

Abstract

The present invention discloses a gate driver. More specifically, the present invention relates to a gate-in-panel (GIP) type gate driver which is mounted on a liquid crystal panel as a thin film transistor and supplies a gate driving signal to a pixel, and a liquid crystal display device including the same. According to an embodiment of the present invention, a dummy stage of the gate driver can be substituted by a structure which generates one gate driving signal, i.e., a reset signal, rather than an even-odd number sharing structure, thereby minimizing the number of thin film transistors of the dummy stage, and therefore, reducing an area of the gate driver.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driver and a liquid crystal display (LCD)

The present invention relates to a gate driver, and more particularly, to a GIP (Gate-In-Panel) gate driver that is mounted in a liquid crystal panel with a thin film transistor to supply a gate driving signal to a pixel and a liquid crystal display including the same.

2. Description of the Related Art [0002] With the development of information electronic devices for realizing high-resolution and high-quality images such as portable telephones (portable phones) and notebook computers, and HDTVs, flat panel display devices ) Are increasingly in demand. Such flat panel display devices include a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) OLED). Of these, liquid crystal displays (LCDs) are currently being studied extensively because of mass production technology, ease of driving means, realization of high image quality, and realization of a large area screen.

In particular, an active matrix type liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying dynamic images. In order to control such a switching device, a liquid crystal display device is provided with a gate driver, and in recent years, the gate driver is provided not in a driving IC separate from the liquid crystal panel but in the form of a thin film transistor on a liquid crystal panel.

FIG. 1 is a view schematically showing a structure of a gate driving unit included in a conventional liquid crystal display device.

1, a conventional gate driver includes a plurality of stages (not shown) for outputting gate driving voltages Vg1 to Vgn to gate wirings formed in a display panel (not shown) in synchronization with predetermined clock signals CLK1 to CLK8 ST1 to STn (n is a natural number)). Each of the above-described stages ST1 to STn is composed of a plurality of transistors.

In this case, the clock signals CLK1 to CLK8 are eight-phase structures using eight different timing signals, and a four-phase or six-phase six-phase structure with four clock signals is widely used according to the design intention. In the case of the gate driver using the signals CLK1 to CLK8, there is an advantage that power consumption is smaller than other methods.

In the conventional gate driver, one stage has one output. In the figure, the thin film transistors in two neighboring stages are shared a predetermined number of times and the Qb node (not shown) is divided into the even and odd- The number of the thin film transistors is reduced and the size of the gate driver is reduced.

The gate driver of this structure has a structure in which the first stage ST1 receives the start signal (not shown) and the first and second clock signals CLK1 and CLK2 and superimposes the three horizontal periods 3H for the four horizontal periods 4H, And the second stage ST2 outputs a third gate driving signal Vg3 of a high level. The first gate driving signal Vg2 is a high level signal. Here, the third gate driving signal Vg3 is a signal that is superimposed on the second gate driving signal Vg2 and the three horizontal periods 3H, and the second stage ST2 then sequentially applies the fourth gate driving signal Vg4 .

Particularly, during the driving of the next stage STn-1 of the second stage ST2, its gate driving signal is applied again to the front-end stage as a reset signal and the first stage ST1 and the second gate driving signals Vg1 and Vg2 ) Is output at a low level.

When this operation is repeated and the m-th gate driving signal (Vgm, m is a natural number) is output until the n-th stage (n ST), the operation for one frame is completed. At this time, since the n-th stage and the (n-1) th stage nST do not have a subsequent stage, a dummy stage DT1 or DT2 for separately generating a reset signal must be provided.

However, although the dummy stages DT1 and DT2 do not directly generate and output a gate driving signal, the gate driving unit has the same structure as the other stages ST1 to STn, occupies the same area, Which is a disadvantage in minimizing the width of the non-display region except for the display region, but can not be removed due to the role of providing the reset signal.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-mentioned problems, and it is an object of the present invention to simplify the structure of a dummy stage for generating a reset signal supplied to the last two stages of a gate driver to minimize the number of thin film transistors, So as to realize a four-row bezel type liquid crystal display device.

In order to achieve the above object, a gate driver according to an embodiment of the present invention includes: a plurality of stages connected to two of a plurality of gate lines formed on a liquid crystal panel to output a gate driving signal; And a dummy stage having one output for applying a reset signal to at least one of the plurality of stages.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention includes: a liquid crystal panel in which a plurality of gate wirings and data wirings are cross-formed in a matrix form and pixels are defined at intersections; A gate driver having a plurality of stages connected to two of the plurality of gate gate lines and sequentially supplying a gate driving signal to the pixels; A data driver connected to the data line and supplying a data signal to the pixel; And a timing controller for controlling the gate driver and the data driver, wherein the gate driver includes a dummy stage including a dummy stage having one output for applying a reset signal to at least one of the plurality of stages, do.

According to the embodiment of the present invention, by replacing the dummy stage of the gate driver with a structure for generating one gate driving signal, i.e., a reset signal, not the odd-odd shared structure, the number of the thin film transistors of the dummy stage is minimized, It is possible to reduce the area.

FIG. 1 is a view schematically showing a structure of a gate driving unit included in a conventional liquid crystal display device.
2 is a diagram illustrating the entire structure of a liquid crystal display device including a gate driver according to an embodiment of the present invention.
FIG. 3A is a diagram illustrating a structure of a gate driver and a dummy portion of the present invention, and FIG. 3B is a diagram illustrating a clock signal and a gate driving signal input to and output from the gate driver of FIG. 3A.
FIG. 4 is a view showing an example of an equivalent circuit diagram for one stage of the gate driver of the present invention, and FIG. 5 is a diagram showing an equivalent circuit diagram for one stage of the dummy section of the present invention.

Hereinafter, a gate driver according to a preferred embodiment of the present invention and a liquid crystal display including the same will be described with reference to the drawings.

2 is a diagram illustrating the entire structure of a liquid crystal display device including a gate driver according to an embodiment of the present invention.

2, the liquid crystal display of the present invention includes a display area A / A in which a plurality of pixels P are formed to display an image, and a non-display area N / A liquid crystal display device according to an embodiment of the present invention includes a liquid crystal panel 100 in which A is defined and a timing control unit 110 that controls each of the driving units. A gate driver 120 including a dummy stage for supplying a reset signal to the stage and a data driver 130 connected to the liquid crystal panel 100 to supply a data signal Vdata to the pixel P.

The liquid crystal panel 100 includes a plurality of gate lines GL on a transparent substrate and a plurality of data lines DL arranged in a matrix in a direction perpendicular to the gate lines GL, P) is defined. At least one thin film transistor T serving as a switching element is formed in each pixel P and a plurality of thin film transistors T are formed in each thin film transistor T And the liquid crystal capacitor LC is controlled by the liquid crystal capacitor LC. An image is not displayed outside the display area A / A, and a non-display area N / A in which the gate driver 120 and various wirings are extended is defined.

The aforementioned thin film transistor T is turned on in response to the gate drive signal Vg of high level from the gate line GL and the data signal Vdata supplied from the data line DL in synchronization therewith is supplied to the liquid crystal capacitor LC. Here, the liquid crystal capacitor LC is a capacitor structure formed by a common electrode facing the liquid crystal material and a pixel electrode connected to the thin film transistor T. Although not shown, the liquid crystal capacitor LC may further be connected to a storage capacitor (not shown) to stably maintain the charged voltage level until the next frame of the charged data signal Vdata.

The arrangement state of the liquid crystal material is varied according to the data signal Vdata charged through the thin film transistor T so that the light transmittance of the liquid crystal capacitor LC is controlled to realize the gray level.

The timing controller 110 generates a gate control signal GCS and a data control signal DCS by receiving an image signal applied from an external source and a predetermined timing signal, And 130, respectively.

The timing controller 110 generates and supplies not only the gate control signal GCS for controlling the gate driver 120 but also one or more clock signals CLK for driving the gate driver VG, The eight-phase structure in which the clock signal CLK is eight can be applied.

Although not shown, the timing controller 110 is designed to receive image-related signals and timing signals output from the external system via a predetermined interface, without noise, at a high speed. Such interfaces include a low voltage differential signal (LVDS) method or a transistor-transistor logic (TTL) interface method.

A gate driver 120 formed of a plurality of thin film transistors is formed on a non-display area N / A of at least one side of the liquid crystal panel 100. A plurality of And is electrically connected to the gate wiring line GL of FIG.

The gate driving unit 120 applies a gate driving signal Vg to the gate line GL arranged on the liquid crystal panel 100 in response to the gate control signal GCS applied from the timing controller 110, The data signal Vdata of the analog waveform supplied from the data driver 140 is connected to each of the thin film transistors T And is applied to the liquid crystal capacitor CLC.

The gate control signal GCS includes a gate start pulse, a gate shift clock, and a gate output enable signal.

The gate driving signal VG has two voltage levels of a high level and a low level and sequentially supplies the gate line GL every 1 to 4 horizontal periods (1 to 4H) at a high level during one frame (1 frame) . Here, the gate driving signal VG output to the adjacent gate line GL is overlapped by 1 to 3 horizontal periods (1 to 3H), and the data signal Vdata is supplied to the pixels on one horizontal line in one horizontal period (1H).

The gate driving unit 120 may be set such that no overlapping period exists between the gate driving signals VG. However, since the liquid crystal panel 100 realizes a high resolution image and is formed in a large area, It is preferable that the supply time of each gate driving signal Vg is increased and overlapped with each other so as to prevent a malfunction due to the shortage of the gate driving signal Vg.

The gate driver 120 includes a Qb node shared double output stage, one of which outputs two gate driving signals Vg, and two dummy Stage 125 as shown in FIG. Unlike the other stages, the dummy stage 125 is not a Qb node shared structure. The dummy stage 125 has a single output structure in which one stage outputs only one signal. 100 in the vertical direction is smaller than that in the conventional case.

The data driver 130 converts the aligned image signal RGB input according to the data control signal DCS input from the timing controller 110 into an analog data signal Vdata using the reference voltage . The data signal Vdata is latched by one horizontal period (1H) and output to the liquid crystal panel 100 simultaneously through all the data lines DL corresponding to the gate driving signal Vg.

The data control signal DCS includes a source start pulse (SSP), a source shift clock (SSC), and a source output enable (SOE).

According to the above-described structure, the liquid crystal display device including the gate driver of the present invention realizes two dummy stages connected to the last stage of the gate driver 120 as a single output structure instead of a double output structure, So that the width of the liquid crystal panel in the vertical direction can be reduced.

Hereinafter, a gate driver of a liquid crystal display according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 3A is a diagram illustrating a structure of a gate driver and a dummy portion of the present invention, and FIG. 3B is a diagram illustrating a clock signal and a gate driving signal input to and output from the gate driver of FIG. 3A.

3A and 3B, the gate driver 120 of the present invention applies gate driving voltages Vg1 to Vgm to gate wirings formed in a display panel (not shown) in synchronization with predetermined clock signals CLK1 to CLK8, And a plurality of stages ST1 to STn for outputting the plurality of stages ST1 to STn.

In the figure, the configuration of the present invention is described as an example of an 8-phase structure gate driver that is driven in synchronism with eight clock signals (CLK1 to CLK8). However, in the case where a clock signal has a 2-phase, 4-phase or 6-phase The technical idea of the present invention can be applied to the gate driver.

Although not shown, a normal power supply voltage VDD and a ground voltage VSS for driving the gate driver 120 are supplied to each of the stages ST1 to STn. Each of the stages ST1 to STn shares a predetermined number of thin film transistors in one stage and divides a Qb node (not shown) into an even number and a odd number and alternates the two output terminals to output high level gate driving signals Vg1- Vgm).

In the first stage ST1, the first and second start signals Vst1 and Vst2 are input as start signals, and in synchronization with the first and second clock signals CLK1 and CLK2, (Vg1, Vg2) sequentially. Also, the first stage ST1 receives the m-2 gate driving signal Vgm-2 of the (n-1) th stage STn-1 as a reset signal.

That is, each stage receives the second gate driving signal of the stage after the rear stage as a reset signal, outputs a low level gate driving signal, and supplies the gate driving signal to the start signal of the subsequent stage.

The (n-1) -th stage STn-1 outputs the (m-3) th and (m-2) th gate driving signals Vgm-3 and Vgm- To the reset signal of the first stage ST1 and the start signal of the first dummy stage DT1. The n-th stage STn outputs the m-1 and m-th gate driving signals Vgm-1 and Vgm and the m-th gate driving signal Vgm to the reset signal of the second stage ST2, 2 dummy stage DT2.

The first and second dummy stages DT1 and DT2 receive the m-2 and mth gate driving signals Vgm-2m and Vgm as start signals, respectively, and the n-1th stage and the nth stage STn- 1, STn) of the first and second reset signals rst1 and rst2. The first and second dummy stages DT1 and DT2 receive the first and second start signals Vst1 and Vst2 as a reset signal.

According to this structure, the gate driver 120 of the present invention receives the start signals Vst1 and Vst2 and the first and second clock signals CLK1 and CLK2 in the first stage ST1, Level first and second gate driving signals Vg1 and Vg2 having overlapping periods of 3 horizontal periods 3H and then the second stage ST2 outputs the third and fourth gate driving signals (Vg3, Vg4). Here, the first and second gate driving signals Vg1 and Vg2 may be signals that are overlapped with each other in three horizontal periods (3H).

When the m-th gate driving signal Vgm is output until the n-th stage n ST is repeated, the operation for one frame is completed, and the first and second reset signals rst 1 and rst 2 of the dummy stage When output, the next frame starts.

Particularly, the dummy portion 125 of the present invention is a single output structure in which one stage has one output signal, so that the number of the thin film transistors is smaller than that of the conventional one and the total area of the gate driver 120 can be designed to be small .

On the other hand, the gate drive signals Vgm-3 to Vgm are output in synchronization with the clock signals CLK1 to CLK8 and the data signal Vdata of the horizontal line corresponding to each gate drive signal Vgm-3 to Vgm is 1 An image is displayed as it is outputted in the horizontal period (1H).

Hereinafter, an example of the gate driver and the dummy portion according to the embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a view showing an example of an equivalent circuit diagram for one stage of the gate driver of the present invention, and FIG. 5 is a diagram showing an equivalent circuit diagram for one stage of the dummy section of the present invention.

4, one stage STn included in the gate driver of the present invention includes an odd stage (ODD) for outputting the (m-1) th gate driving signal Vgm-1, And a radar stage EVEN for outputting a signal.

In particular, the illustrated stage STn is a double output structure in which the Qb_o node Qb_o and the Qb_e node Qb_e are mutually shared to reduce the number of thin film transistors, The total number of transistors is 26, totaling 13 transistors. In addition, the ODD and EVEN have the same structure in addition to the connection structure of the shared Qb_o node Qb_o and Qb_e node Qb_e.

The first thin film transistor T1_1 is turned on by the first start signal Vst1 to charge the Q1 node Q1 with the power supply voltage VDD and the first thin film transistor T1_2 charges the second start signal Vst2 ) To charge the Q2 node (Q2) with the power supply voltage (VDD).

The second thin film transistor T2 receives the next and next gate driving signals Vnext and discharges the Q1 node Q1 to the ground voltage VSS.

As the Qb_o node Qb_o is charged, the third 3o thin film transistor T3o is turned on to discharge the Q1 and Q2 nodes Q1 and Q2 and the third e thin film transistor T3e becomes conductive And discharges Q1 and Q2 nodes Q1 and Q2.

The fourth thin film transistor T4A turns on the fourth and fourth thin film transistors T4_1 and T4_2 as the good power supply voltage VDD_O and the odd power source voltage VDD_E alternately go to the high level. The fourth and fourth thin film transistors T4_1 and T4_2 charge the Qb_o node Qb_o or the Qb_e node Qb_e through the high level power supply voltage VDD_O or the nadir power source voltage VDD_E. The fourth Q thin film transistor T4Q plays a role of discharging the Q2 node Q2 when the Q1 node Q1 is charged or discharging the Q1 node Q1 when the Q2 node Q2 is charged.

The fifth thin film transistor T5 discharges the Qb_o node Qb_o and Qb_e node Qb_e to the ground voltage VSS as the first start signal Vst1 is applied and the fifth Q thin film transistor T5Q discharges Q1 Qb_o node Qb_o or Qb_e node Qb_e as the node Q1 or Q2 node Q2 is charged and the fifth QI thin film transistor T5QI discharges Q1 node Q1 or Q2 node Q2 And turns off the fourth transistor T4 as it is charged.

The sixth transistor T6_1 functions as a pull-up buffer and is turned on as the node Q1 is charged so that the first clock signal CLK1 of the high level is turned on to the m- 1 gate drive signal Vgm-1. Also, the sixth transistor T6_2 turns on as the Q2 node Q2 is charged to output the high-level second clock signal CLK2 as the m-th gate driving signal Vgm.

The seventh thin film transistor T7o functions as a pull-up buffer and outputs the (m-1) th gate drive signal Vgm-1 to the low level as the Qb_o node Qb_o is charged And at the same time, keeps the m-th gate driving signal Vgm at a low level. The seventh eighth thin film transistor T7e allows the m-th gate driving signal Vgm-1 to be kept at a low level as the Qb_e node Qb_e is charged, and at the same time, the mth gate driving signal Vgm And outputs it to the low level.

Driving of the stage of the gate driver according to the above-described structure will be described as follows.

As the first start signal Vst1 of the high level is inputted, the first thin film transistor T1_1 of the odd stage ODD is turned on to charge the Q1 node Q1 to the high level, The transistor T4Q and the fifth Q film transistor T5Q are turned on so that the Qb_o node Qb_o and the Qb_e node Qb_e are discharged. At this time, the fourth power source voltage VDD_O is in a high level state and the fourth A thin film transistor T4A is in a diode state, and a current flows through the fourth Q thin film transistor T4Q to turn on the fourth and fourth thin film transistors T4_1 and T4_2. Is maintained in the turn-off state.

Next, when the high-level first clock signal CLK1 is applied, the gate-source voltage of the sixth_1th TFT T6_1 is varied to output the m-1th gate driving signal Vgm-1 of high level .

Then, as the high level second start signal Vst2 is input, the first thin film transistor T1_2 of the odd number EVEN is turned on to charge the Q2 node Q2 to a high level, The fifth thin film transistor T4Q and the fifth thin film transistor T5Q are turned on so that the Qb_o node Qb_o and the Qb_e node Qb_e are maintained in a discharged state. Next, when the high-level second clock signal CLK2 is applied, the gate-source voltage of the sixth_2 thin film transistor T6_2 is varied to output the high-level m-th gate driving signal Vgm. Here, the second start signal Vst2 and the second clock signal CLK2 are delayed by one horizontal period (1H) and the first start signal Vst1 and the first clock signal (CLK1) The m-th gate driving signal Vgm-1 and the m-th gate driving signal Vgm are outputted so that the three horizontal periods 3H overlap each other.

3 gate drive signal Vgm + 3 from the (n + 2) th stage STn + 2 to the second thin film (Vnext) as the next stage stage signal Vnext, though not shown, Is applied to the transistor T2, and the Q1 node Q1 and the Q2 node Q2 are discharged. At this time, since the fifth power source voltage VDD_O is in the high level state and the fifth Qi thin film transistor T5QI is turned off, the fourth thin film transistor T4_1 is turned on to connect the Qb_o node Qb_o to the even power source voltage VDD_O ).

Accordingly, the seventh thin film transistor T7o is turned on to sequentially shift the m-1 gate driving signal Vgm-1 and the mth gate driving signal Vgm to a low level. The seventh thin film transistor T7o and the seventh eighth thin film transistor T7e are determined to be turned on and off by the unipolar power supply voltage VDD_O and the radix power supply voltage VDD_E.

Hereinafter, a structure of a dummy stage according to an embodiment of the present invention will be described with reference to the drawings. Although only the first dummy stage DT1 is shown in the drawing, the second dummy stage (not shown) also has the same circuit structure.

Referring to FIG. 5, the dummy stage DT1 included in the gate driver of the present invention supplies a first reset signal rst1 to the front stage.

In particular, the dummy stage DT1 of the present invention has a single output structure in which one stage outputs one reset signal, and the number of the thin film transistors provided therein is 17. Therefore, as compared with the stage having a double output structure having 26 thin film transistors, nine thin film transistors can be omitted, and at least two reset signals are required, so that 18 thin film transistors can be reduced compared to the conventional one. .

The first thin film transistor T1 is turned on by the m-2 gate driving signal Vgm-2 to charge the Q node Q with the power supply voltage VDD.

The second N thin film transistor T2N is turned on by the start signal Vst to discharge the Q node Q to the ground voltage VSS.

The third_O thin film transistor T3_O is turned on to discharge the Q node Q as the Qb_O node Qb_O is charged and the third_E thin film transistor T3_E becomes conductive as the Qb_E node Qb_E is charged, Q).

The fourth N_O thin film transistor T4N_O and the fourth N_E thin film transistor T4N_E charge the Qb_O node Qb_O and the Qb_E node Qb_E with the superior power supply voltage VDD_O and the odd power supply voltage VDD_E, It plays a role.

The fourth_O thin film transistor T4_O and the fourth_E thin film transistor T4_E serve to charge the Qb_O node Qb_O and the Qb_E node Qb_E to the even power supply voltage VDD_O and the odd power supply voltage VDD_E, respectively .

 The fifth Vdd_O thin film transistor T5Vdd_O and the fifth Vdd_E thin film transistor T5Vdd_E are respectively connected to the ground voltage VSS according to the odd power source voltage VDD_E and the superior power source voltage VDD_O by connecting Qb_O node Qb_O and Qb_E node Qb_E, As shown in FIG. The fifth Q_O thin film transistor T5Q_O and the fifth Q_E thin film transistor T5Q_E discharge the Qb_O node Qb_O and the Qb_E node Qb_E to the ground voltage VSS as the Q node Q is charged do. The fifth-O thin film transistor T5_O and the fifth E thin film transistor T5_E are connected to the Qb_O node Qb_O and the Qb_E node Qb_E as the m-2 gate driving signal Vgm-2 of high level is applied. And discharges to the ground voltage VSS.

The sixth thin film transistor T6 functions as a pull-up buffer and turns on the second clock signal CLK2 of a high level as the Q1 node Q1 is charged to the first reset And outputs it as a signal rst1.

The seventh thin film transistor T7_O functions as a pull-up buffer and causes the first reset signal rst1 to be output at a low level as the Qb_O node Qb_O is charged, The 7_E thin film transistor T7_E causes the first reset signal rst1 to be output at a low level as the Qb_E node Qb_E is charged.

Driving of the dummy stage of the gate driver according to the above-described structure will be described as follows.

The first thin film transistor T1 is turned on to charge the Q node Q to a high level and the fifth Q_O thin film transistor (Vgm-2) is turned on as the m-2 start signal Vgm- T5Q_O and the fifth Q_E thin film transistor T5Q_E are turned on to discharge Qb_o node Qb_o and Qb_e node Qb_e. At this time, when the good power supply voltage VDD_O is in the high level state, the fourth_O thin film transistor T4_O is in the diode state, but the current flows through the fifth Q_O thin film transistor T5Q_O so that the Qb_O node Qb_O is at the low level, The discharge state is maintained in accordance with the voltage VSS. This is the same as when the ninth power source voltage VDD_E is in the high level state and the fourth_E thin film transistor T4_E is in the diode state, the Qb_E node Qb_E maintains the low level for a reason corresponding thereto.

Next, when the high-level second clock signal CLK2 is applied, the gate-source voltage of the sixth thin-film transistor T6 is varied to output the high-level first reset signal rst1.

Then, as the start signal Vst of high level is inputted, the second N thin film transistor T2N is turned on so that the Q node Q is discharged to the ground voltage VSS level, (T6) is turned off. At the same time, the good power supply voltage VDD_O is charged in the Qb_O node Qb_O, and the Qb_E node Qb_E is maintained in the discharged state.

Accordingly, the seventh thin film transistor T7_O is turned on and the first reset signal rst1 is transited to the low level. The turn-on and turn-off times of the seventh TFT (T7_O) and the seventh TFT (T7_E) are determined by the unipolar power supply voltage VDD_O and the radix power supply voltage VDD_E.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

A / A: display area N / A: non-display area
P: pixel GL: gate wiring
DL: Data line GCS: Gate control signal
DCS: data control signal RGB: image signal
Vg: gate drive signal Vdata: data signal
100: liquid crystal panel 110: timing controller
120: Gate driver 125:
130: Data driver

Claims (10)

A plurality of stages connected to two of the plurality of gate wirings formed on the liquid crystal panel to output a gate driving signal; And
A dummy stage having one output for applying a reset signal to at least one of the plurality of stages,
And a gate driver. The method according to claim 1,
Wherein the gate driver comprises:
Phase clock signal structure. The method according to any one of claims 1 and 2,
The dummy stage is divided into first and second dummy stages,
Wherein the first dummy stage supplies a first reset signal to an (n-1) (n is a natural number) stage of the plurality of stages,
The second dummy stage may include supplying a second reset signal to the n-th (n is a natural number) stage of the plurality of stages
And a gate driver. The method of claim 3,
Wherein the first and second dummy stages are arranged in a matrix,
Numbered gate drive signals (Vgm-2, Vgm (m is a natural number)) of the n-1th stage and the nth stage, respectively, as a start signal. The method of claim 3,
Wherein the first and second dummy stages are arranged in a matrix,
Respectively, in synchronization with the second clock signal and the fourth clock signal. The method of claim 3,
Wherein the first and second dummy stages are arranged in a matrix,
Respectively, in synchronization with the second clock signal and the fourth clock signal. The method of claim 3,
Wherein the first and second dummy stages are arranged in a matrix,
And the start signal of the plurality of stages is received as a reset signal and is driven. The method according to claim 1,
Wherein the one stage comprises:
Q1 node, Qb_o node and Qb_e node; And
A Q2 node is formed and is divided into a superior node sharing the Qb_o node and the Qb_e node,
A first 1 < th > thin film transistor T1_1 which is turned on by a first start signal to charge the node Q1 with a power supply voltage;
A first thin film transistor T1_2 turned on by a second start signal to charge the node Q2 with a power supply voltage;
A second thin film transistor (T2) receiving a gate driving signal from the rear stage and discharging the node Q1 to a ground voltage;
A third < RTI ID = 0.0 > o < / RTI > thin film transistor (T3o) which conducts as the Qb_o node is charged and discharges the Q1 and Q2 nodes;
A third e thin film transistor (T3e) which is turned on when the Qb_e node is charged and discharges the Q1 and Q2 nodes;
4_1 and 4_2 thin film transistors T4_1 and T4_2 for respectively charging the Qb_o node or the Qb_e node corresponding to a high level good power supply voltage or a radial power supply voltage;
A fourth A thin film transistor T4A for turning on the fourth and fourth thin film transistors T4_1 and T4_2 according to the good power supply voltage and the odd power source voltage;
A fourth Q thin film transistor T4Q discharging the Q2 node when the Q1 node is charged and discharging the Q1 node Q1 when the Q2 node is charged;
A fifth thin film transistor (T5) for discharging the Qb_o node and the Qb_e node to a ground voltage as the first start signal is applied;
A fifth Q thin film transistor T5Q for discharging the Qb_o node or the Qb_e node as the Q1 node or the Q2 node is charged;
A fifth QI thin film transistor T5QI for turning off the fourth transistor T4 when the Q1 node or the Q2 node is charged;
A sixth transistor T6_1 for turning on the Q1 node as the node Q1 is charged to output a high-level clock signal as an (m-1) -th gate driving signal Vgm-1;
A sixth_2 thin film transistor T6_2 which is turned on as the node Q2 is charged to output a high-level clock signal as the m-th gate driving signal Vgm;
A seventh thin film transistor T7o for outputting the (m-1) th gate driving signal Vgm-1 at a low level as the Qb_o node is charged; And
A seventh thin film transistor T7e for outputting the m-th gate driving signal Vgm at a low level as the Qb_e node is charged,
And a gate driver. The method according to claim 1,
In the dummy stage, a Q node, a Qb_O node, and a Qb_E node are formed,
A first thin film transistor (T1) turned on by an m-2 gate drive signal (Vgm-2) to charge the Q node with a power supply voltage;
A second N thin film transistor T2N which is turned on by a start signal to discharge the Q node to a ground voltage;
A third_O thin film transistor (T3_O) which conducts when the Qb_O node is charged and discharges the Q node;
A third E thin film transistor (T3_E) which is turned on when the Qb_E node is charged and discharges the Q node;
A fourth N_O thin film transistor T4N_O and a fourth N_E thin film transistor T4N_E for charging the Qb_O node and the Qb_E node with an excellent power supply voltage and a radix power supply voltage, respectively, in accordance with the start signal;
A fourth_O thin film transistor (T4_O) and a fourth_E thin film transistor (T4_E) for charging the Qb_O node and the Qb_E node according to an excellent power supply voltage and a ninth power supply voltage, respectively;
A fifth Vdd_O thin film transistor (T5Vdd_O) and a fifth Vdd_E thin film transistor (T5Vdd_E) for discharging the Qb_O node and the Qb_E node to a ground voltage in accordance with the radial power supply voltage and the superior power supply voltage, respectively;
A fifth Q_O thin film transistor T5Q_O and a fifth Q_E thin film transistor T5Q_E for discharging the Qb_O node and the Qb_E node Qb_E to the ground voltage as the Q node is charged, respectively;
A fifth_O thin film transistor T5_O and a fifth_E thin film transistor T5_E for discharging the Qb_O node and the Qb_E node to the ground voltage in response to application of a high level m-2 gate driving signal Vgm-2;
A sixth thin film transistor (T6) for turning on the Q1 node as it is charged and outputting a clock signal as a first reset signal;
A seventh O thin film transistor T7_O for outputting the first reset signal at a low level as the Qb_O node is charged; And
A seventh E thin film transistor T7_E for outputting the first reset signal at a low level as the Qb_E node is charged,
And a gate driver. A liquid crystal panel in which a plurality of gate wirings and data wirings are cross-formed in a matrix form and pixels are defined at intersections;
A gate driver having a plurality of stages connected to two of the plurality of gate gate lines and sequentially supplying a gate driving signal to the pixels;
A data driver connected to the data line and supplying a data signal to the pixel; And
And a timing controller for controlling the gate driver and the data driver,
Wherein the gate driver comprises:
And a dummy stage comprising a dummy stage having one output for applying a reset signal to at least one of the plurality of stages
And the liquid crystal display device.

Images