KR20140132174A - Display device - Google Patents

Abstract

A display device a plurality of gate lines extended in a first direction; a plurality of data lines extended in a second direction, a plurality of pixels connected to the gate lines and the data lines respectively; a gate driver driving the gate lines; a data driver driving the data lines in response to a plurality of clock signals and a data signal; and a timing controller providing the clock signals and the data signal to the data driver and controlling the gate driver. The timing controller outputs the clock signals to adjust output timing of the data driving signals provided to the data lines according to distances in the first direction between the gate driver and the data lines.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device having improved display quality.

Generally, a display device includes a display panel for displaying an image and a data driver and a gate driver for driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor. The data driver outputs a data driving signal to the data lines, and the gate driver outputs a gate driving signal for driving the gate lines.

In such a display device, a gate-on voltage is applied to a gate electrode of a thin film transistor connected to a gate line to be displayed, and then a data voltage corresponding to the display image is applied to the source electrode to display an image. As the thin film transistor is turned on, the data voltage applied to the liquid crystal capacitor and the storage capacitor must be maintained for a predetermined time even after the thin film transistor is turned off. However, the size of the display panel is increased, and a signal delay can be generated on the transmission path of the gate signal output from the gate driver by adopting the high-speed driving method. In this case, the charging rate of the liquid crystal capacitors located far from the gate driver becomes lower than the charging rate of the liquid crystal capacitors located close to each other, so that the picture quality becomes uneven in one display panel.

Accordingly, it is an object of the present invention to provide a display device with improved display quality.

According to an aspect of the present invention, there is provided a display device including: a plurality of gate lines extended in a first direction; a plurality of data lines extended in a second direction; A data driver for driving the plurality of data lines in response to a plurality of clock signals and a data signal, and a data driver for driving the plurality of data lines in response to the plurality of data signals, And a timing controller for providing the plurality of clock signals and the data signal to the data driver and controlling the gate driver. The timing controller outputs the plurality of clock signals so that the output timing of the data driving signal provided to the plurality of data lines is adjusted in accordance with the distance between the gate driver and the plurality of data lines in the first direction .

In this embodiment, the plurality of data lines are divided into a plurality of data line groups, and the plurality of clock signals correspond to the plurality of data line groups, respectively.

In this embodiment, the data driver includes a plurality of data driver ICs, and the plurality of clock signals are provided to the plurality of data driver ICs, respectively.

In this embodiment, each of the plurality of data driver ICs drives a corresponding k (k is a positive integer) data lines of the plurality of data lines.

In this embodiment, the plurality of data driver ICs include a first data driver IC and a second data driver IC sequentially sequenced in the first direction, And provides the second data driver integrated circuit with a second clock signal delayed by a predetermined time from the first clock signal provided to the integrated circuit.

In this embodiment, the plurality of data driver integrated circuits include first data driver integrated circuits and second data driver integrated circuits sequentially arranged in the first direction, And provides the second data driver ICs with a second clock signal delayed by a predetermined time to a first clock signal provided to the driver integrated circuits.

In this embodiment, the plurality of data driver ICs are sequentially arranged in the first direction, and the timing controller is arranged to control the distance between the gate driver and the plurality of data driver ICs in the first direction Thereby providing the plurality of clock signals with a predetermined delay time to the plurality of data driver integrated circuits, respectively.

According to the present invention having such a configuration, the output timing of the data driving signal can be adjusted according to the distance between the gate driver and the data line. Therefore, the quality of the display device can be improved.

1 is a plan view of a display device according to an embodiment of the present invention.
2 is a diagram showing a relationship between a gate driving signal and a data driving signal provided to a data line adjacent to the gate driver.
3 is a diagram showing a relationship between a data driver signal and a gate signal provided to a data line far from the gate driver.
FIG. 4 is a timing diagram exemplarily showing signals generated in the display device shown in FIG. 1. FIG.
FIG. 5 is a view showing a gate signal and a data driving signal provided in the first pixel shown in FIG.
6 is a view showing a gate signal and a data driving signal provided to the second pixel shown in FIG.
FIG. 7 is a timing diagram illustrating exemplary signals generated in the display device shown in FIG. 1 when first through eighth clock signals having different delay times are provided to the data driver integrated circuits shown in FIG. 1 .
8 is a timing diagram of signals generated in the display device shown in FIG. 1 according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an embodiment of the present invention.

1, a display device 100 includes a display panel 110, a printed circuit board 120, a timing controller 130, a plurality of data driving circuits 141-148 and a gate driver 160 do.

The display panel 110 includes a display area AR provided with a plurality of pixels PX and a non-display area NAR adjacent to the display area AR. The display area AR is an area where an image is displayed, and the non-display area NAR is an area where an image is not displayed. The display panel 110 may be a glass substrate, a silicon substrate, a film substrate, or the like.

The printed circuit board 120 may include various circuits for driving the display panel 110. The data circuit board 120 may include a plurality of wires for connecting to the timing controller 130, the gate driver 160, and the data driving circuits 141-148.

The timing controller 130 is electrically connected to the printed circuit board 120 through a cable 132. In another embodiment, the timing controller 130 may be mounted directly on the printed circuit board 130.

The timing controller 130 provides the video data DATA and the first control signal CONT1 to the data driver circuits 141-148 through the cable 132 and supplies the second control signal CONT2 to the gate driver 160). The first control signal CONT1 includes a horizontal synchronization start signal, clock signals TP1 to TP8 and a line latch signal. The second control signal CONT2 includes a vertical synchronization start signal, an output enable signal, A pulse signal CPV1, a second gate pulse signal CPV2, and the like.

Each of the plurality of data driving circuits 141-148 may be implemented with a tape carrier package (TCP) or a chip on film (COF), and the data driver IC 151-158 Respectively. Each of the data driver ICs 151-158 drives the plurality of data lines in response to the data signal DATA from the timing controller 130 and the first control signal CONT1. The data driver integrated circuits 151-158 may not be disposed on the printed circuit board 120 but may be mounted directly on the display panel 110. [

Each of the data driver ICs 151-158 drives the corresponding K (K is a positive integer) data lines of the data lines DL11 to DL8K as data driving signals. In this embodiment, each of the data driver ICs 151-158 is responsive to the clock signals TP1 to TP8 included in the first control signal CONT1 provided from the timing controller 130, The output timing of the data driving signal provided to the data lines DL1 to DL8K can be changed.

The plurality of data driving circuits 141-148 are arranged in the first direction on the first side of the display panel 110 side by side. The gate driver 160 is arranged on the second side of the display panel 110.

The gate driver 160 may be implemented as a circuit using an amorphous silicon gate (ASG), an oxide semiconductor, a crystalline semiconductor, or a polycrystalline semiconductor using an amorphous silicon thin film transistor (a-Si TFT) Display area (NAR) of the non-display area (NAR). In another embodiment, the gate driver 160 may be implemented with a tape carrier package (TCP) or a chip on film (COF). The gate driver 160 drives the gate lines GL1 to GLn in response to the second control signal CONT2 from the timing controller 130. [

The gate driver 160 drives the gate lines GL1 to GLn in response to the second control signal CONT2 from the timing controller 130. [

One row of switching transistors connected thereto is turned on while the gate-on voltage VON is applied to one gate line, at which time the data driver ICs 151-158 generate a data drive signal corresponding to the data signal DATA To the data lines DL11-DL8K. The data driving signals supplied to the data lines DL11-DL8K are applied to the corresponding pixels through the turned-on switching transistors. Here, a period during which one row of the switching transistors is turned on, that is, one period of the data enable signal DE and the first and second gate clock signals CKV1 and CKV2 is referred to as a '1 horizontal period' Quot; 1H ".

2 and 3 are views showing an example of a gate signal and a data driving signal provided to one of the gate lines shown in FIG. FIG. 2 shows a relationship between a data driving signal and a gate signal provided in a data line adjacent to a gate driver, and FIG. 3 shows a relationship between a data driving signal and a gate signal provided in a data line far from the gate driver .

Referring to FIGS. 2 and 3, the gate signal Gi generated from the gate driver 160 (shown in FIG. 1) is transmitted through the gate line GLi. The first pixel PXi11 is connected to the gate line GLi and the data line DL11 and the second pixel PXi81 is connected to the gate line GLi and the data line DL8k. It can be seen that the gate signal Gi output from the gate driver 160 is delayed by a predetermined time when it is supplied from the gate driver 160 to the pixel PXi81 far away in the first direction X1.

When the data driver ICs 151-158 provide the data drive signals D11-D8k at the same timing, i.e., simultaneously to the data lines DL11-DL8k, the delay d of the gate signal Gi, The charge rate of the second pixel PXi81 which is distant from the first pixel PXi11 adjacent to the gate driver 160 in the first direction X1 is lowered.

FIG. 4 is a timing diagram exemplarily showing signals generated in the display device shown in FIG. 1. FIG.

Referring to FIG. 4, the first to fourth clock signals TP1 to TP4 generated from the timing controller 130 have the same waveform, and the fifth to eighth clock signals TP5 to TP8 have the same waveform . The fifth to eighth clock signals TP5 to TP8 are delayed from the first to fourth clock signals TP1 to TP4 by a delay time td.

The first to fourth clock signals TP1 to TP4 are provided to the respective data driver ICs 151 to 154 shown in FIG. 1, and the fifth to eighth clock signals TP5 to TP8 are provided to the data driver ICs 151 to 154 shown in FIG. Are provided to each of the data driver integrated circuits 155-158 shown in FIG.

The gate driver 160 responds to the first gate pulse signal CPV1 and the second gate pulse signal CPV2 included in the second control signal CONT2 provided from the timing controller 130 to the gate lines GL1 to GLn . The first gate pulse signal CPV1 is a signal for driving the odd gate lines GL1, GL3, GL5, ..., GLn-1 of the plurality of gate lines GL1 to GLn, (CPV2) is a signal for driving the even-numbered gate lines G2, G4, G6, ..., Gn among the plurality of gate lines GL1 to GLn. Each of the pulses in the first gate pulse signal CPV1 corresponds to the odd gate lines GL1, GL3, GL5, ..., GLn-1 and each pulse in the second gate pulse signal CPV2 corresponds to the odd- And correspond to the lines GL2, GL4, GL6, ..., GLn, respectively.

The predetermined gate line GLi is driven by the gate signal Gi of the gate-on voltage VON level when the first gate pulse signal CPV1 is activated to the high level and the gate signal Gi of the first gate pulse signal CPV1 is driven to the low level It is driven by the gate signal Gi of the gate-off voltage (VOFF) level. When the second gate pulse signal CPV2 is activated to the high level, the gate line GLi + 1 is driven by the gate signal Gi + 1 of the gate-on voltage VON level and the second gate pulse signal CPV2 is driven by the gate signal Gi + When it is inactivated to the low level, it is driven by the gate signal Gi + 1 of the gate off voltage (VOFF) level.

The polling edge of the gate signal Gi at the gate-on voltage (VON) level provided to the gate line GLi is lowered to the kickback voltage (VKB) level and then becomes the gate-off voltage (VOFF) level.

The time until the next pulse of the first to fourth clock signals TP1 to TP4 occurs after the gate signal Gi transitions to the gateoff voltage VOFF level is the first output enable time tOE1 . The time until the next pulse of the fifth to eighth clock signals TP5 to TP8 occurs after the gate signal Gi transitions to the gateoff voltage VOFF level is the second output enable time tOE2 . When the fifth to eighth clock signals TP5 to TP8 are delayed by the delay time td from the first to fourth clock signals TP1 to TP4, the second output enable time tOE1 is lower than the first output enable time tOE1, The enable time tOE2 becomes longer.

As described above, the first output enable time tOE1 for the data lines having a small delay amount of the gate signal Gi is shortened and the second output enable time tOE1 for the data lines having the large delay amount of the gate signal Gi is shortened. the delay of the gate signal Gi can be compensated for by varying the delay time tOE2.

FIG. 5 is a view showing a gate signal and a data driving signal provided in the first pixel shown in FIG.

1, 4 and 5, the data driver IC 151 drives the data lines DL11 to DL1K in response to the first clock signal TP1. For example, the timing of the data driving signal D11 provided to the first pixel PXi11 is the same as the timing of the data driving signal D11 shown in Fig.

6 is a view showing a gate signal and a data driving signal provided to the second pixel shown in FIG.

1, 4, and 6, the data driver IC 158 drives the data lines DL81 to DL8K in response to the eighth clock signal TP8. For example, the rising edge of the data driving signal D81 provided to the second pixel PXi81 is delayed by the delay time td from the rising edge of the data driving signal D11 provided to the first pixel PXi11. The delay time td is preferably set in consideration of the delay time of the gate signal Gi transmitted through the gate line GLi.

After the delay time td by the delay time td than the data driving signal D11 provided to the gate driver 160 in the first direction PXi11 in the first direction X1, The delay of the gate signal Gi transmitted to the gate line GLi can be compensated by providing the gate signal D81.

The timing diagram shown in FIG. 4 previously divides the data driver integrated circuits 151-158 shown in FIG. 1 into two groups. That is, each of the first group of data driver ICs 151-154 is provided with first to fourth non-delayed clock signals TP1-TP4, and the second group of data driver ICs 155- 158 respectively provided with the fifth to eighth clock signals TP5 to TP8 delayed by the delay time td.

In another embodiment, the timing controller 130 may provide the first to eighth clock signals TP1-TP8 with different delay times to the data driver ICs 151-158.

FIG. 7 is a timing diagram illustrating exemplary signals generated in the display device shown in FIG. 1 when first through eighth clock signals having different delay times are provided to the data driver integrated circuits shown in FIG. 1 .

Referring to FIGS. 1 and 7, the timing controller 130 provides the first to eighth clock signals TP1 to TP8 with different delay times to the data driver ICs 151-158. The second clock signal TP2 is a signal delayed by the first delay time td1 from the first clock signal TP1. The eighth clock signal TP8 is a signal delayed by the eighth delay time td8 from the first clock signal TP1. At this time, the eighth delay time td8 of the eighth clock signal TP8 is set to be the same as the delay time td8 until the next pulse of the first clock signal TP1 is generated after the gate signal Gi transits to the gateoff voltage VOFF level Is shorter than the first output enable time tOE1.

8 is a timing diagram of signals generated in the display device shown in FIG. 1 according to another embodiment of the present invention.

Referring to FIGS. 1 and 8, the first to fourth clock signals TP1 to TP4 generated from the timing controller 130 have the same waveform, and the fifth to eighth clock signals TP5 to TP8 And has the same waveform. The fifth to eighth clock signals TP5 to TP8 are delayed from the first to fourth clock signals TP1 to TP4 by a delay time td.

In the example shown in FIG. 4, the first through fourth clock signals TP1 through TP4 and the fifth through eighth clock signals TP5 through TP8 have the same pulse widths. In the example shown in FIG. 8, the fifth to eighth clock signals TP5 to TP8 have rising edges delayed by the delay time td from the first to fourth clock signals TP1 to TP4, The polling edges of the eighth to eighth clock signals TP5 to TP8 are the same as the first to fourth clock signals TP1 to TP4.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical ideas which fall within the scope of the following claims and equivalents thereof should be interpreted as being included in the scope of the present invention .

100: display device 110: display panel
120: printed circuit board 130: timing controller
141-148: Data driving circuit
151-158: Data Driver Integrated Circuit
160: gate driver

Claims (7)

A plurality of gate lines extending in a first direction;
A plurality of data lines extending in a second direction;
A plurality of pixels each connected to a plurality of gate lines and a plurality of data lines;
A gate driver for driving the plurality of gate lines;
A data driver for driving the plurality of data lines in response to a plurality of clock signals and a data signal; And
And a timing controller for providing the plurality of clock signals and the data signal to the data driver and controlling the gate driver;
The timing controller includes:
And outputs the plurality of clock signals so that an output timing of a data driving signal provided to the plurality of data lines is adjusted according to a distance between the gate driver and the plurality of data lines in the first direction Device. The method according to claim 1,
The plurality of data lines are divided into a plurality of data line groups,
Wherein the plurality of clock signals correspond to the plurality of data line groups, respectively. 3. The method of claim 2,
The data driver includes:
A plurality of data driver integrated circuits,
Wherein the plurality of clock signals are provided to the plurality of data driver ICs, respectively. The method of claim 3,
Wherein each of the plurality of data driver ICs drives a corresponding k (k is a positive integer) data lines among the plurality of data lines. The method of claim 3,
Wherein the plurality of data driver integrated circuits comprise a first data driver integrated circuit and a second data driver integrated circuit sequentially arranged in the first direction,
Wherein the timing controller provides the second data driver integrated circuit with a second clock signal obtained by delaying a first clock signal provided to the first data driver integrated circuit by a predetermined time. The method of claim 3,
The plurality of data driver integrated circuits comprising first data driver integrated circuits and second data driver integrated circuits sequentially arranged in the first direction,
Wherein the timing controller provides a second clock signal to the second data driver ICs by delaying a first clock signal provided to the first data driver ICs by a predetermined time. The method of claim 3,
Wherein the plurality of data driver integrated circuits are sequentially arranged in the first direction,
Wherein the timing controller provides the plurality of clock signals having a predetermined delay time to the plurality of data driver integrated circuits, respectively, according to the distance in the first direction between the gate driver and the plurality of data driver integrated circuits And the display device.

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