KR20140119714A - Photoactive devices with improved distribution of charge carriers, and methods of forming same - Google Patents

Abstract

a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a second base region comprising a plurality of quantum wells disposed between the first base region and the second base region, And a well structure. The multiple quantum well structure includes at least three quantum well regions and at least two barrier regions. The electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than the electron hole energy barrier between the second quantum well region and the first quantum well region. Methods of forming such devices include sequentially epitaxially depositing layers of such multiple quantum well structures and selecting the composition and configuration of the layers such that electron hole energy barriers are varied across the multiple quantum well structure do.

Description

[0001] The present invention relates to photoactive devices having improved distribution of charge carriers and methods of forming the same,

Embodiments of the present invention generally relate to photoactive devices comprising III-V semiconductor materials and methods of forming such photoactive devices.

Photovoltaic devices are devices that are configured to convert electrical energy into electromagnetic radiation, or to convert electromagnetic radiation into electrical energy. Photoactive devices include, but are not limited to, light-emitting diodes (LEDs), semiconductor lasers, photodetectors, and solar cells. These photoactive devices often include one or more planar layers of III-V semiconductor materials. The Group III-V semiconductor materials include one or more elements from the group IIIA of the Periodic Table of Elements such as boron (B), aluminum (Al), gallium (Ga), indium (In) and thallium (Tl) (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi). The planar layers of the III-V semiconductor material may be crystalline and may comprise a single crystal of a III-V semiconductor material.

Layers of crystalline III-V semiconductor material generally include some amount of defects within the crystal lattice of the III-V semiconductor material. These defects in the crystal structure may include, for example, point defects and line defects (e.g., threading dislocations). These defects are detrimental to the performance of photoactive devices fabricated on or in the layer of III-V semiconductor material.

Additionally, currently known methods for the production of crystalline III-V semiconductor material layers generally involve epitaxial growth of the III-V semiconductor material on the surface of the underlying substrate , The lower substrate has a crystal lattice similar to, but slightly different from, the crystalline lattice of the crystalline III-V semiconductor material. As a result, when the crystalline III-V semiconductor material layer is grown on another underlying substrate material, the crystalline lattice of the crystalline III-V semiconductor material may be mechanically strained. As a result of this strain, as the thickness of the layer of III-V semiconductor material in the growth process increases, defects such as dislocations at some critical thickness become energetically favorable and stress stress may build up inside the layer of III-V semiconductor material until defects are formed within the layer of III-V semiconductor material to mitigate stress buildup.

From the above viewpoint, it is difficult to produce relatively thick layers of crystalline III-V semiconductor material having relatively low concentrations of defects therein.

The photoactive devices may comprise an active region comprising a plurality of quantum well regions, each of which may comprise a layer of III-V semiconductor material. The quantum well regions may be separated from one another by barrier regions, which may also include a layer of III-V semiconductor material, but may include layers of different composition for quantum well regions.

There is a mismatch between the mobility of electrons and electron holes (vacant electron orbitals) in at least some III-V semiconductor materials. In other words, electrons can move relatively easily through III-V semiconductor materials compared to electron holes. This mismatch between electrons and electron holes can lead to non-uniform distribution of electrons and electron holes in active areas of photoactive devices. This phenomenon is described in "Reduction of Efficiency Droop in InGaN Light Emitting Diodes by Coupled Quantum Wells" (Applied Physics Letters, Vol. 93, pg. 171113, 2008) and CH Wang et al., "Efficiency Droop Quot; Alleviation in InGaN / GaN Light-Emitting Diodes by Graded-Thickness Multiple Quantum Wells "(Applied Physics Letters, Vol. 97, pg. 181101, 2010).

The present invention is intended to overcome, at least in part, the disadvantages mentioned above in connection with prior art embodiments.

In some embodiments, the present invention provides a semiconductor device comprising a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, Emitting semiconductor devices including multiple quantum well structures disposed between two base regions. The multiple quantum well structure includes at least three quantum well regions and at least two barrier regions. Wherein a first one of the at least two barrier regions is disposed between a first one of the at least three quantum well regions and a second one of the quantum well regions. And a second barrier region of the at least two barrier regions is disposed between the second quantum well region and the third one of the at least three quantum well regions. The first quantum well region is located closer to the first base region than the third quantum well region and the third quantum well region is located closer to the second base region than the first quantum well region. Wherein each of the first quantum well region, the second quantum well region and the third quantum well region has a well region thickness of at least about 2 nanometers in a direction extending between the first base region and the second base region Wherein each of the first barrier region and the second barrier region has a barrier region thickness greater than or equal to each of the well region thicknesses in a direction extending between the first base region and the second base region. In addition, the electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than the electron hole energy barrier between the second quantum well region and the first quantum well region.

In further embodiments, the present invention includes devices comprising at least one light emitting diode (LED). Wherein the LED comprises a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a second base region disposed between the first base region and the second base region Lt; / RTI > multiple quantum well structures. The multiple quantum well structure includes at least three quantum well regions and at least two barrier regions. Wherein a first one of the at least two barrier regions is disposed between a first one of the at least three quantum well regions and a second one of the quantum well regions and a second one of the at least two barrier regions, Is disposed between the second quantum well region and the third quantum well region of the at least three quantum well regions. The first quantum well region is located closer to the first base region than the third quantum well region and the third quantum well region is located closer to the second base region than the first quantum well region. Wherein each of the first quantum well region, the second quantum well region, and the third quantum well region includes In _x Ga _{1 - x} N, and the direction extending between the first base region and the second base region With a well region thickness of at least about 2 nanometers. Wherein each of the first barrier region and the second barrier region comprises In _y Ga _{1- y} N, y is at least about 0.5, and the well region Has a barrier region thickness greater than or equal to each of the region thicknesses and at least about 2 nanometers. Wherein the electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than the electron hole energy barrier between the second quantum well region and the first quantum well region.

In still other embodiments, the present invention includes methods of forming radiation emitting devices. According to these methods, a plurality of III-V semiconductor material volumes are sequentially epitaxially deposited on the substrate to form a first barrier region disposed between the first quantum well region and the second quantum well region and a second barrier region disposed between the second quantum well region and the second quantum well region. And a second barrier region disposed between the well region and the third quantum well region. Each of the first quantum well region, the second quantum well region and the third quantum well region may be formed to have a well region thickness of at least about 2 nanometers. Each of the first barrier region and the second barrier region may be formed to have a barrier region thickness greater than or equal to each of the well region thicknesses. In addition, the first quantum well region and the second quantum well region are arranged such that the electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than the electron hole energy barrier between the second quantum well region and the first quantum well region. , The second quantum well region and the third quantum well region may be selected.

In still other embodiments, the present invention includes methods of forming radiation emitting devices. According to these methods, a plurality of openings are formed which extend through the layer of semiconductor material strained on the strain relief layer. The strained semiconductor material and the strain relief layer are heat treated to cause deformation of the strain relief layer and relaxation of the strained semiconductor material to form at least one volume of the relaxed semiconductor material. Wherein a plurality of III-V semiconductor material volumes are sequentially epitaxially deposited on at least one volume of the relaxed semiconductor material to form a first barrier region disposed between the first quantum well region and the second quantum well region, 2 quantum well region and a second barrier region disposed between the third quantum well region and the second quantum well structure. The first quantum well region, the second quantum well region and the third quantum well region are each formed to have a well region thickness of at least about 2 nanometers. Wherein each of the first barrier region and the second barrier region is formed to have a barrier region thickness greater than or equal to each of the well region thicknesses. The first quantum well region and the second quantum well region are arranged such that the electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than the electron hole energy barrier between the second quantum well region and the first quantum well region, The second quantum well region and the third quantum well region are selected.

While specific reference may be made in detail to the embodiments of the invention, as claimed, and illustrated in the accompanying drawings, wherein advantages of embodiments of the present invention are apparent from the following detailed description when read in conjunction with the accompanying drawings, Can be:
1 is a simplified cross-sectional view of a radiation emitting semiconductor device and corresponding energy band diagram for the device;
Figures 2-5 are used to illustrate a method of forming a radiation emitting semiconductor device in accordance with embodiments of the present disclosure;
2 is a simplified cross-sectional view of a layer of strained semiconductor material over a strain relief layer on a base substrate;
Figure 3 is a simplified cross-sectional view as in Figure 2 showing a plurality of openings extending through a layer of strained semiconductor material;
Figure 4 is a simplified cross-sectional view, as in Figures 2 and 3, showing the volumes of relaxed semiconductor material formed by relaxation of the strained semiconductor material with the help of a strain relief layer; And
5 is a simplified cross-sectional view of a radiation emitting semiconductor device disposed on a volume of the relaxed semiconductor material shown in FIG.

The designations shown herein are not meant to be actual drawings of any particular material, semiconductor structure or device, or method, but merely idealized representations employed to illustrate the invention. Additionally, elements common between the figures may retain the same reference numerals.

As used herein, the term "III-V semiconductor material" refers to one or more elements (B, Al, Ga, In and Tl) from group IIIA of the periodic table and one or more elements Means any material consisting mainly of elements (N, P, As, Sb and Bi) and includes.

As used herein, the term "critical thickness" means the maximum thickness at which the formation of defects, such as dislocations, within the material becomes energetically favorable when used with respect to the material.

As used herein, the term "epitaxial layer of material" refers to a layer of material formed at least substantially of a single crystal of the material, such that the single crystal exhibits a known crystallographic orientation.

As used herein, the term "growth lattice parameter ", when used with respect to the epitaxial layer of a semiconductor material, refers to the average lattice constant of the semiconductor material layer, as evidenced by the layer of semiconductor material when the semiconductor material layer is epitaxially grown at elevated temperatures It means constant.

As used herein, the term "lattice strain " when used with respect to a material layer means the strain of the crystal lattice in a direction at least substantially parallel to the plane of the material layer, and compressive strain ) Or a tensile strain. Similarly, the term "average lattice constant" when used with respect to a material layer means the mean lattice constants at dimensions at least substantially parallel to the plane of the material layer.

Similarly, the term "strained" means that the crystal lattice is deformed from the normal spacing for this material such that the lattice spacing is different from what is normally accessible for such material in a homogeneous relaxed crystal For example, stretched or compressed).

Embodiments of the present disclosure include photoactive devices, such as radiation emitting structures (e.g., LEDs), that are adapted to provide an improved distribution of electron holes across multiple quantum well structures during driving of the photoactive devices And a multiple quantum well structure having an energy band structure.

1 shows an exemplary embodiment of a radiation emitting semiconductor device 100 of the present disclosure. The semiconductor device 100 may include, for example, an LED. A simplified energy band diagram represented by semiconductor device 100 is shown above semiconductor device 100 of FIG. Other regions within the energy band structure are aligned with the regions of the corresponding semiconductor device 100, respectively.

1, the radiation emitting semiconductor device 100 includes a first base region 102, a second base region 104, and a second base region 104 between the first base region 102 and the second base region 104, Lt; RTI ID = 0.0 > 106 < / RTI >

The multiple quantum well structure 106 includes at least three quantum well regions. 1, semiconductor device 100 includes a first quantum well region 108, a second quantum well region 110, a third quantum well region 112, and a fourth quantum well region < RTI ID = 0.0 > 114). In additional embodiments, however, the radiation emitting semiconductor device 100 may include only three quantum well regions or more than four quantum well regions.

Each of the quantum well regions 108 - 114 has a respective well region thickness 115 in a direction extending between the first base region 102 and the second base region 104. The individual well region thicknesses 115 of the quantum well regions 108-114 may be the same or different. In an exemplary, non-limiting manner, each of the individual well region thicknesses 115 is about 2 nanometers or more, about 5 nanometers or more, about 10 nanometers or more, about 20 nanometers or more Lt; / RTI >

In the embodiment of FIG. 1, the first quantum well region 108 is located near the first base region 102 and the fourth quantum well region 114 is located near the second base region 104. The first quantum well region 108 is located closer to the first base region 102 than the second quantum well region 110 and the second quantum well region 110 is closer to the second quantum well region 112 than the third quantum well region 112. [ Is located closer to the first base region 102 and the third quantum well region 112 is closer to the first base region 102 than the fourth quantum well region 114. Similarly, the fourth quantum well region 114 is located closer to the second base region 104 than the third quantum well region 112 and the third quantum well region 112 is located closer to the second quantum well region 110 And the second quantum well region 110 is located closer to the second base region 104 than the first quantum well region 108. The second quantum well region 110 is closer to the second base region 104 than the first quantum well region 108,

The barrier region may be disposed between adjacent quantum well regions 108-114. 1, a first barrier region 116 is disposed between the first quantum well region 108 and the second quantum well region 110, and a second barrier region 118 is disposed between the first quantum well region 108 and the second quantum well region 110. [ Is disposed between the second quantum well region 110 and the third quantum well region 112 and the third barrier region 120 is disposed between the third quantum well region 112 and the fourth quantum well region 114 do.

Each of the barrier regions 116-120 has a respective barrier region thickness 121 in a direction extending between the first base region 102 and the second base region 104. [ The individual barrier region thicknesses 121 of the barrier regions 116-120 may be the same or different. Each of the individual barrier region thicknesses 121 is greater than the well region thicknesses 115 to prevent tunneling of electrons through the barrier regions 116-120 between the quantum well regions 108-114 Can be the same. In an exemplary, non-limiting manner, each of the individual barrier region thicknesses 121 is about 2 nanometers or more, about 5 nanometers or more, about 10 nanometers or more, about 15 nanometers or more , Up to about 20 nanometers or more.

The multi-quantum well structure 106 may be, for example, about 10 nanometers or more, about 20 nanometers or more, about 50 nanometers or more in a direction extending between the first base region 102 and the second base region 104, Nanometers or more, about 85 nanometers or more, about 140 nanometers or more.

The first base region 102 may comprise an n-type semiconductor material and the second base region 104 may comprise a p-type semiconductor material. In an exemplary, non-limiting manner, each of the first base region 102 and the second base region 104 comprises a III-V semiconductor material such as In _z Ga _{1- z} N (where z is about 0.02 to about 0.17) . The first base region 102 may be an intrinsic or doped n-type III-V semiconductor material and the second base region 104 may be an intrinsic or doped p-type semiconductor material.

The first base region 102 may be electrically and structurally connected to the first conductive contact 142 and the second base region 104 may be electrically and electrically connected to the second conductive contact 144. [ Can be structurally linked. Each of the first conductive contact 142 and the second conductive contact 144 may include, for example, one or more metals (e.g., aluminum, titanium, platinum, nickel, gold, etc.) , Multiple layers of such metals or metal alloys. In further embodiments, the first conductive contact 142 and / or the second conductive contact 144 may each be doped or comprise an intrinsic n-type or p-type semiconductor material.

The metals and metal alloys may not be transparent to the wavelengths or wavelengths of the electromagnetic radiation generated in the multiple quantum well structure 106 during the driving of the semiconductor device 100. Thus, as shown in FIG. 1, the second conductive contact 144 may not cover the entire surface of the second base region 104. For example, the second conductive contact 144 may be patterned so that one or more apertures extend through the second conductive contact 144. In this configuration, radiation generated in the multiple quantum well structure 106 that is transmitted out of the semiconductor device 100 passes through the second conductive contact 144 through the second base region 104. Additionally or alternatively, the first conductive contact 142 may be patterned as described with reference to the second conductive contact 144.

Referring to the energy band diagram of FIG. 1, the first conductive contact 142 and the first base region 102 may provide electrons 146 to the multiple quantum well structure 106. The second conductive contact 144 and the second base region 104 may provide electron holes 148 to the multiple quantum well structure 106. As previously mentioned, the electrons 146 may exhibit a higher mobility in the multiple quantum well structure 106 relative to the electron holes 148. Thus, in previously known devices, when a voltage across a multiple quantum well structure 106 between a first base region 102 and a second base region 104 is applied, electrons 146 reach the multi- Electron holes 148 may be more evenly distributed across the multiple quantum well structure 106 and the second base region 104 may be more uniformly distributed across the well structure 106, Lt; RTI ID = 0.0 > quantum well < / RTI > This non-uniform distribution of electron holes 148 across multiple quantum well structures 106 is not required for non-radiant Auger recombination of pairs of electrons 146 and electron holes 148, Increase probability.

As described above, the multiple quantum well structure 106 of embodiments of the present disclosure is configured to provide an improved distribution of electron holes 148 across the multiple quantum well structure 106 in the driving process of the semiconductor device 100 And has a tailored energy band structure.

Continuing with the energy band diagram of Figure 1, the quantum well regions 108-114 may have a material composition and a structural configuration selected to provide bandgap energy 132 to each of the quantum well regions 108-114 have. In the embodiment shown in Figure 1, the band gap energy 132 is at least substantially the same within the other quantum well regions 108-114. In further embodiments, the band gap energy 132 of one or more of the quantum well regions 108-114 may be different than the band gap energy of the other quantum well regions 108-114.

The barrier regions 116-120 may have a material composition and a structural configuration selected to provide respective band gap energies 124-128 in each of the barrier regions 116-120. 1, the band gap energy 124 in the first barrier region 116 may be greater than the band gap energy 126 in the second barrier region 118, The band gap energy 126 in the second barrier region 118 may be greater than the band gap energy 128 in the third barrier region 120. [ In addition, each of the band gap energies 132 of the quantum well regions 108-114 may be less than each of the band gap energies 124-128 of the barrier regions 116-120.

In this configuration, the electron hole energy barrier 136 between the fourth quantum well 114 and the third quantum well 112 causes the electron hole energy barrier between the third quantum well 112 and the second quantum well 110 And the electron hole energy barrier 138 between the third quantum well 112 and the second quantum well 110 may be less than the electron hole energy barrier 138 between the second quantum well 110 and the first quantum well 108. [ And may be smaller than the electron hole energy barrier 140. In other words, across the barrier regions 116-120, the electron hole energy barriers 136-140 provide electron holes 148 (from the second base region 104 to the multiple quantum well structure 106) Can be increased in a step-wise manner across multiple quantum well structures 106 in a direction extending to first base region 102 (e.g. The electron hole energy barriers 136-140 are the differences in the valence band energies across the interfaces between the quantum well regions 108-114 and the adjacent barrier regions 116-120. As a result of electron hole energy barriers 136-140 increasing across barrier regions 116-120 as they move from the second base region 104 toward the first base region 102, A more uniform distribution of the electron holes 148 within the substrate 106 can be achieved and this can lead to improved efficiency in the driving process of the radiation emitting semiconductor device 100.

As previously mentioned, barrier regions 116-120 may have selected material compositions and structural configurations to provide different respective band gap energies 124-128 in barrier regions 116-120, respectively . In an exemplary, non-limiting manner, each of the barrier regions 116-120 may comprise a ternary Group III nitride such as In _y Ga _{1- y} N (y is at least about 0.05). The increase in indium content (i.e., the increase in y value) in In _y Ga _{1- y} N of the barrier regions 116-120 can reduce the band gap energy of the barrier regions 116-120 have. The second barrier region 118 may have a higher indium content than the first barrier region 116 and the third barrier region 120 may have a higher indium content than the second barrier region 118 Lt; / RTI > In an exemplary, non-limiting manner, the first barrier region 116 may comprise In _y Ga _{1- y} N (where y may range from about 0.05 to about 0.15), the second barrier region 118 may include In _y Ga _{1 - y} N (where y is about 0.10 to about 0.20), and the third barrier region 120 may include In _y Ga _{1- y} N (where y is about 0.15 to about 0.25).

The quantum well regions 108-114 may also include a ternary Group III nitride such as In _x Ga _{1- x} N (where x may be at least about 0.12, or up to about 0.17 or more).

The quantum well regions 108-114 and the barrier regions 116-120 described above are generally formed on a plane of a III-V semiconductor material (e.g., a ternary Group III nitride such as indium gallium nitride (InGaN)). Layer. The layers of III-V semiconductor material may be crystalline and may comprise a single crystal of a III-V semiconductor material.

As is known in the art, layers of crystalline III-V semiconductor material generally include some amount of defects within the crystal lattice of the III-V semiconductor material. Defects in such a crystal structure may include, for example, point defects and line defects (e. G., Threading dislocations). These defects are detrimental to the performance of photoactive devices comprising layers of III-V semiconductor material.

The layers of crystalline III-V semiconductor material may be prepared by epitaxially growing layers of a III-V semiconductor material on the surface of the bottom substrate, wherein the bottom substrate comprises a crystalline lattice of crystalline III- Have similar but slightly different crystal lattices. As a result, when the crystalline III-V semiconductor material is grown onto another underlying substrate material, the crystal lattice of the crystalline III-V semiconductor material can be mechanically strained. As a result of this strain, as the thickness of the layer of III-V semiconductor material in the growth process increases, defects such as dislocations in some critical thicknesses become energetically favorable and the III- The stress inside the layer of III-V semiconductor material increases until defects are formed within the layer of semiconductor material.

When the layers of indium gallium nitride (InGaN) are deposited epitaxially, the critical thickness of the layers of indium gallium nitride decreases as the indium content increases. Thus, it may be difficult or impossible to manufacture indium gallium nitride layers with relatively high indium concentrations, having relatively high layer thicknesses and relatively low concentrations of internal defects.

In order to overcome these difficulties, recently developed methods have been developed for multi-quantum wells including the quantum well regions 108-114 and barrier regions 116-120 of a ternary Group III nitride such as indium gallium nitride, Can be used to fabricate the quantum well structure 106. In an exemplary, non-limiting manner, United States Patent Application Publication No. 2010/0032793, published Feb. 11, 2010 by Guenard et al., United States of America published by Letertre et al. On July 15, 2010 Methods such as those described in patent application publication publication no. 2010/0176490, or in any of U.S. Patent Application Publication No. 2010/0109126, published by Arena et al., On May 6, 2010, Can be used to fabricate the multiple quantum well structure 106 of the emitting semiconductor device 100.

Non-limiting examples of methods that may be used to fabricate the multiple quantum well structure 106 of the radiation emitting semiconductor device 100 as described herein are described below with reference to FIGS. 2-5.

2, a substrate 152 may be provided that includes a strained semiconductor material layer 158 on a base substrate 156 and an intervening strain relief layer 154 therebetween. The base substrate 156 may include any one or more of, for example, sapphire, silicon carbide, silicon, and metallic materials (e.g., molybdenum, tantalum, etc.). The strain relief layer 154 may include materials such as, for example, silicate glass, phosphosilicate glass, borosilicate glass, or borophosphosilicate glass. have. The strained semiconductor material 158 may be used as a seed layer for epitaxially depositing a plurality of layers on top of it to ultimately form the multiple quantum well structure 106 described above. In an exemplary, non-limiting manner, the strained semiconductor material layer 158 may include In _z Ga _{1- z} N (where z is about 0.06 to about 0.08).

The strained semiconductor material layer 158 may comprise a III-V semiconductor material. Illustrative and in non-limiting manner, the strained layer of semiconductor material 158 is at least one of gallium nitride (GaN), indium gallium nitride (In _x Ga _{1- x} N), and aluminum gallium nitride (Al _x Ga _{1- x} N) One can be included.

Referring to FIG. 3, a plurality of openings 160 may be formed to extend through the strained semiconductor material layer 158. In an exemplary, non-limiting manner, the mask and etch process can be used to form openings 160 through the strained semiconductor material layer 158. After forming the openings 160 through the strained semiconductor material layer 158, the remaining portion of the strained semiconductor material layer 158 is etched away by at least a portion of the relaxed semiconductor material 162, The structure may be plastically relaxed in a manner that allows for subsequent relaxation of stress and / or strain within the remaining portion of the strained semiconductor material layer 158. For example, ) Or at a temperature that can be elastically deformed.

Referring to FIG. 5, various layers of the radiation emitting semiconductor device 100 (FIG. 1) are formed by sequentially epitaxially depositing a plurality of III-V semiconductor material volumes onto a volume of the relaxed semiconductor material 162 Can be formed. For example, the first base region 102 of the n-type ternary Group-III nitride having the composition and composition as described above may be epitaxially deposited on the volume of the relaxed semiconductor material 162. Thereafter, quantum well regions 108-114 and barrier regions 116-120 comprising a ternary Group III nitride having the same composition and composition as described above are epitaxially deposited on the first base region 102 So as to form the multiple quantum well structure 106. The second base region 104 of the p-type semiconductor material having the composition and configuration as described above may be epitaxially deposited on the multiple quantum well structure 106.

In some embodiments, the substrate 152 may be removed to provide access to the first base region 102, for example, to form one or more electrical contacts or contact layers thereon. One or more etching processes, a grinding process, a chemical-mechanical polishing (CMP) process, a laser ablation process, and a registered SMART CUT (R) Can be removed. The first conductive contact 142 may then be formed on or otherwise provided on the first base region 102 and the second conductive contact 144 may then be formed on the second base region 104, .

Additional non-limiting exemplary embodiments of the present disclosure are provided below.

Example 1: A first base region comprising an n-type III-V semiconductor material; a second base region comprising a p-type III-V semiconductor material; And a multiple quantum well structure disposed between the first base region and the second base region, wherein the multiple quantum well structure includes at least three quantum well regions and at least two barrier regions, Wherein a first barrier region of the two barrier regions is disposed between a first one of the at least three quantum well regions and a second quantum well region and a second one of the at least two barrier regions comprises a first quantum well region and a second quantum well region, Wherein the second quantum well region is disposed between the second quantum well region and the third quantum well region of at least three quantum well regions, the first quantum well region being closer to the first base region than the third quantum well region, The third quantum well region being located closer to the second base region than the first quantum well region; Wherein each of the first quantum well region, the second quantum well region, and the third quantum well region has a well region thickness of at least about 2 nanometers in a direction extending between the first base region and the second base region Wherein each of the first barrier region and the second barrier region has a barrier region thickness greater than or equal to each of the well region thicknesses in a direction extending between the first base region and the second base region; Wherein the electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than the electron hole energy barrier between the second quantum well region and the first quantum well region.

Embodiment 2: A radiation emitting semiconductor device according to Embodiment 1, wherein each of the first quantum well region, the second quantum well region, and the third quantum well region includes a ternary Group III nitride.

Embodiment 3: A radiation emitting semiconductor device according to Embodiment 2, wherein the ternary Group III nitride includes In _x Ga _1-x N.

Embodiment 4: A radiation emitting semiconductor device according to Embodiment 3, wherein x is at least about 0.12.

Embodiment 5 Any of the radiation-emitting semiconductor devices of Embodiments 1 to 4, wherein each of the first barrier region and the second barrier region includes a ternary Group III nitride.

Embodiment 6: A radiation emitting semiconductor device according to Embodiment 5, wherein the ternary Group III nitride in the first barrier region and the second barrier region includes In _y Ga _{1- y} N.

Embodiment 7: A radiation emitting semiconductor device according to Embodiment 6, wherein y is at least about 0.05.

Embodiment 8: An optional radiation emitting semiconductor device according to any one of Embodiments 1 to 4, wherein each of the first barrier region and the second barrier region includes a binary Group III nitride.

Embodiment 9: A radiation emitting semiconductor device according to Embodiment 8, wherein the binary Group III nitride of the first barrier region and the second barrier region includes GaN.

Embodiment 10: A radiative emission semiconductor device as in any of the embodiments 1 to 9, wherein the well region region thickness of each of the first quantum well region, the second quantum well region, and the third quantum well region is at least about 5 Nanometer.

11. The radiation emitting semiconductor device of embodiment 10 wherein the thickness of the well region of each of the first quantum well region, the second quantum well region, and the third quantum well region is at least about 10 nanometers do.

12. The radiation emitting semiconductor device of embodiment 11 wherein the thickness of the well region of each of the first quantum well region, the second quantum well region, and the third quantum well region is at least about 20 nanometers do.

13. The radiating semiconductor device of any one of embodiments 1 to 12 wherein the first barrier region has a first band gap energy and the second barrier region has a second band gap energy, And the two band gap energy is smaller than the first band gap energy.

14. A radiating semiconductor device as in any of the embodiments 1 to 13, wherein the multiple quantum well structure further comprises one or more additional quantum well regions and one or more additional barrier regions, Electron hole energy barriers between the adjacent quantum well regions in the quantum well structure decrease stepwise across the multiple quantum well structure from the first base region to the second base region.

Example 15: A first base region comprising an n-type III-V semiconductor material; a second base region comprising a p-type III-V semiconductor material; A multi-quantum well structure disposed between the first base region and the second base region, the multi-quantum well structure including at least three quantum well regions and at least two barrier regions, Wherein a first barrier region of the at least two barrier regions is disposed between a first one of the at least three quantum well regions and a second quantum well region, Wherein the first quantum well region is disposed between the second quantum well region and the third quantum well region of the three quantum well regions, the first quantum well region being closer to the first base region than the third quantum well region, The third quantum well region is located closer to the second base region than the first quantum well region; Wherein each of the first quantum well region, the second quantum well region, and the third quantum well region includes In _x Ga _{1 - x} N, and the direction extending between the first base region and the second base region Wherein each of the first barrier region and the second barrier region comprises In _y Ga _1-y N, y is at least about 0.5, and the first base region and the second base region have a thickness of at least about 2 nanometers, A barrier region thickness greater than each of the well region thicknesses in a direction extending between the second base regions and at least about 2 nanometers; Wherein the electron hole energy barrier between the third quantum well region and the second quantum well region is less than the electron hole energy barrier between the second quantum well region and the first quantum well region. (LED).

Embodiment 16: The apparatus of embodiment 15, wherein the well region thickness of each of the first quantum well region, the second quantum well region, and the third quantum well region is at least about 5 nanometers.

Embodiment 17 The apparatus of Embodiment 15 or the apparatus of Embodiment 16 wherein the first barrier region has a first band gap energy and the second barrier region has a second band gap energy, And the energy is smaller than the first band gap energy.

Embodiment 18 The apparatus of Embodiment 15 or the apparatus of Embodiment 17 wherein the multiple quantum well structure has a total structure thickness of at least about 10 nanometers in a direction extending between the first base region and the second base region .

Example 19: Sequentially epitaxially depositing a plurality of III-V semiconductor material volumes on a substrate to form a first barrier region disposed between a first quantum well region and a second quantum well region and a second barrier region disposed between the second quantum well region And a second barrier region disposed between the third quantum well region and the second quantum well structure; Forming the first quantum well region, the second quantum well region and the third quantum well region each to have a well region thickness of at least about 2 nanometers; Forming each of the first barrier region and the second barrier region to have a barrier region thickness greater than or equal to each of the well region thicknesses; And an electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than an electron hole energy barrier between the second quantum well region and the first quantum well region, And selecting the composition of each of the second quantum well region and the third quantum well region.

Embodiment 20: The method of Embodiment 19, further comprising the step of forming each of the first quantum well region, the second quantum well region and the third quantum well region so as to include a ternary Group III nitride.

Example 21: The method of embodiment 20 further comprises the step of selecting the ternary Group III nitride to include In _x Ga _{1- x} N.

Example 22: The method of embodiment 21 further comprising forming the In _x Ga _{1- x} N such that x is at least about 0.12.

Example 23: The method of embodiment 22, further comprising forming each of the first barrier region and the second barrier region so as to include ternary Group III nitride.

Example 24: The method of embodiment 23, further comprising the step of selecting the ternary Group III nitride of the first barrier region and the second barrier region to include In _y Ga _{1- y} N.

Example 25: The method of embodiment 24 further comprising forming the In _y Ga _{1- y} N such that y is at least about 0.05.

Embodiment 26: The method of any one of embodiments 19-22, further comprising forming each of the first barrier region and the second barrier region to include a binary Group III nitride.

Example 27: The method of embodiment 26 further comprising the step of selecting the binary Group III nitride of the first barrier region and the second barrier region to include GaN.

28. The method as in any of the embodiments 19-27, wherein each of the first quantum well region, the second quantum well region, and the third quantum well region is at least about 5 nanometers To have a region thickness.

Embodiment 29. The method of embodiment 28, wherein forming the first quantum well region, the second quantum well region and the third quantum well region each have a respective well region thickness of at least about 10 nanometers, .

Embodiment 30: The method of embodiment 29, wherein forming the first quantum well region, the second quantum well region and the third quantum well region each have a respective well region thickness of at least about 20 nanometers .

Embodiment 31. A method as in any of the embodiments 19-30, comprising forming the first barrier region to have a first band gap energy, and forming the second barrier region to have a second band gap energy greater than the first band gap energy To have a second second band gap energy.

Embodiment 32. The method of any one of embodiments 19-27, further comprising forming the multiple quantum well structure to have a total structure thickness of at least about 10 nanometers.

Example 33: forming a plurality of openings extending through a layer of semiconductor material strained onto a strain relief layer; Heat treating the strained semiconductor material and the strain relief layer to cause deformation of the strain relief layer and relaxation of the strained semiconductor material to form at least one volume of the relaxed semiconductor material; Sequentially epitaxially depositing a plurality of III-V semiconductor material volumes onto at least one volume of the relaxed semiconductor material to form a first barrier region disposed between the first quantum well region and the second quantum well region, Forming a multiple quantum well structure comprising a first quantum well region, a second quantum well region and a second barrier region disposed between the first quantum well region and the third quantum well region; Forming the first quantum well region, the second quantum well region and the third quantum well region each to have a well region thickness of at least about 2 nanometers; Forming each of the first barrier region and the second barrier region to have a barrier region thickness greater than or equal to each of the well region thicknesses; And an electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than an electron hole energy barrier between the second quantum well region and the first quantum well region, And selecting the composition of each of the second quantum well region and the third quantum well region.

Embodiment 34. The method of embodiment 33, further comprising the step of forming each of the first quantum well region, the second quantum well region and the third quantum well region so as to include a ternary Group III nitride.

Example 35: The method of embodiment 34, further comprising the step of selecting the ternary Group III nitride to include In _x Ga _{1- x} N.

Example 36: The method of embodiment 35 further comprising forming the In _x Ga _{1- x} N such that x is at least about 0.12.

Example 37: A method as in any of the embodiments 33-36, further comprising forming each of the first barrier region and the second barrier region to include a ternary Group III nitride.

Example 38: The method of embodiment 37, further comprising the step of selecting the ternary Group III nitride of the first barrier region and the second barrier region to include In _y Ga _{1- y} N.

Example 39: The method of embodiment 38, further comprising forming the In _y Ga _{1- y} N such that y is at least about 0.05.

Embodiment 40: The method of any one of embodiments 33-36, further comprising forming each of the first barrier region and the second barrier region to include a binary Group III nitride.

Example 41: The method of embodiment 40, further comprising the step of selecting the binary Group III nitride of the first barrier region and the second barrier region to include GaN.

42. The method of any one of embodiments 33-41 wherein each of the first quantum well region, the second quantum well region and the third quantum well region is at least about 5 nanometers To have a region thickness.

Embodiment 43. The method of embodiment 42, further comprising forming each of the first quantum well region, the second quantum well region and the third quantum well region to have a respective well region thickness of at least about 10 nanometers .

Embodiment 44. The method of embodiment 43, further comprising the step of forming each of the first quantum well region, the second quantum well region and the third quantum well region to have a respective well region thickness of at least about 20 nanometers .

Embodiment 45. A method as in any of the embodiments 33-44, comprising forming the first barrier region to have a first band gap energy, and forming the second barrier region to have a second band gap energy greater than the first band gap energy To have a second second band gap energy.

Embodiment 46: The method of any one of embodiments 33-41, further comprising forming the multiple quantum well structure to have a total structure thickness of at least about 10 nanometers.

Embodiment 47. The method of any one of embodiments 33-46, further comprising forming the strained semiconductor material to include In _z Ga _{1- z} N.

Example 48: A method of Example 47, further comprising at least such that z is about 0.06 to about 0.08 the step of forming the In _z Ga _1-z N.

Example 49: The method of any one of embodiments 33-48, wherein said strain relief layer is formed to include at least one of a silicate glass, a phosphosilicate glass, a borosilicate glass, and a borophosphosilicate glass .

Those skilled in the art will recognize and appreciate that the invention has been described herein with reference to specific exemplary embodiments thereof, but is not limited thereto. Rather, many additions, omissions, and improvements to the exemplary embodiments may be made without departing from the scope of the present invention as claimed herein. For example, features from one exemplary embodiment are included within the scope of the present invention, as may be considered by the inventors, and may be combined with features of other embodiments.

Claims (20)

a first base region comprising an n-type III-V semiconductor material;
a second base region comprising a p-type III-V semiconductor material;
And a multi-quantum well structure disposed between the first base region and the second base region,
Wherein the multi-quantum well structure comprises at least three quantum well regions and at least two barrier regions, wherein a first one of the at least two barrier regions comprises at least three A second quantum well region and a second quantum well region of the at least two quantum well regions are disposed between a first quantum well region and a second quantum well region of the at least two barrier regions, Wherein the first quantum well region is located closer to the first base region than the third quantum well region and the third quantum well region is located between the first quantum well region and the second quantum well region, Located closer to the second base region;
Wherein each of the first quantum well region, the second quantum well region, and the third quantum well region includes In _x Ga _{1 - x} N and includes at least a first quantum well region and a second quantum well region in a direction extending between the first base region and the second base region Wherein each of the first barrier region and the second barrier region comprises In _y Ga _1-y N, y is at least about 0.5, and the first barrier region and the second barrier region each have a thickness of about 2 nanometers, A barrier region thickness greater than each of said well region thicknesses in a direction extending between said base region and said second base region, said barrier region thickness being at least about 2 nanometers; And
Wherein an electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than an electron hole energy barrier between the second quantum well region and the first quantum well region. And at least one light-emitting diode (LED). The method according to claim 1,
Wherein the thickness of the well region of each of the first quantum well region, the second quantum well region, and the third quantum well region is at least about 5 nanometers. ≪ RTI ID = 0.0 > . The method according to claim 1,
Wherein the first barrier region has a first bandgap energy and the second barrier region has a second band gap energy and the second band gap energy is less than the first band gap energy. And at least one light emitting diode (LED). The method according to claim 1,
Wherein the multi-quantum well structure has a total structure thickness of at least about 10 nanometers in a direction extending between the first base region and the second base region. ≪ RTI ID = 0.0 > . The method according to claim 1,
Wherein the first base region comprises a volume of a relaxed semiconductor material. ≪ Desc / Clms Page number 13 > Forming a plurality of openings extending through a layer of semiconductor material strained onto a strain relaxation layer;
Heat treating the strained semiconductor material and the strain relief layer to cause deformation of the strain relief layer and relaxation of the strained semiconductor material to form at least one volume of the relaxed semiconductor material;
Sequentially epitaxially depositing a plurality of III-V semiconductor material volumes onto at least one volume of the relaxed semiconductor material to form a first barrier region disposed between the first quantum well region and the second quantum well region, Forming a multiple quantum well structure comprising a first quantum well region, a second quantum well region and a second barrier region disposed between the first quantum well region and the third quantum well region;
Forming the first quantum well region, the second quantum well region and the third quantum well region each to have a well region thickness of at least about 2 nanometers;
Forming each of the first barrier region and the second barrier region to have a barrier region thickness greater than or equal to each of the well region thicknesses; And
The first quantum well region and the second quantum well region are arranged such that the electron hole energy barrier between the third quantum well region and the second quantum well region is smaller than the electron hole energy barrier between the second quantum well region and the first quantum well region, Selecting a composition of each of the second quantum well region and the third quantum well region. The method according to claim 6,
Further comprising forming each of the first quantum well region, the second quantum well region and the third quantum well region to include In _x Ga _{1- x} N. 8. The method of claim 7,
further comprising forming the In _x Ga _{1- x} N so that x is at least about 0.12. The method according to claim 6,
Further comprising forming each of the first barrier region and the second barrier region to include In _y Ga _{1- y} N. 10. The method of claim 9,
y & lt _{; /} RTI &_gt; is at least about 0.05. & lt _; RTI ID ₌ 0.0 > The method according to claim 6,
Further comprising forming each of the first barrier region and the second barrier region to include a binary Group III nitride. 12. The method of claim 11,
Further comprising the step of selecting the binary Group III nitride in the first barrier region and the second barrier region to include GaN. The method according to claim 6,
Further comprising forming each of the first quantum well region, the second quantum well region and the third quantum well region to have a respective well region thickness of at least about 5 nanometers. 14. The method of claim 13,
Further comprising forming each of the first quantum well region, the second quantum well region and the third quantum well region to have a respective well region thickness of at least about 10 nanometers. 15. The method of claim 14,
Further comprising forming each of the first quantum well region, the second quantum well region and the third quantum well region to have a respective well region thickness of at least about 20 nanometers. The method according to claim 6,
Forming the first barrier region to have a first band gap energy and forming the second barrier region to have a second band gap energy less than the first band gap energy, / RTI > The method according to claim 6,
Further comprising forming the multiple quantum well structure to have a total structure thickness of at least about 10 nanometers. The method according to claim 6,
Further comprising forming the strained semiconductor material to include In _z Ga _{1 - z} N. 19. The method of claim 18,
such that z is about 0.02 to about 0.17 The method of forming a copy-emitting device further comprising the step of forming the In _z Ga _{1- z} N. The method according to claim 6,
Wherein the strain relief layer is formed to include at least one of silicate glass, phosphosilicate glass, borosilicate glass, and borophosphosilicate glass Wherein said radiation-emitting device is a light-emitting device.

Images