KR20140093383A

KR20140093383A - Solar cell

Info

Publication number: KR20140093383A
Application number: KR1020130005524A
Authority: KR
Inventors: 심경진
Original assignee: 엘지전자 주식회사
Priority date: 2013-01-17
Filing date: 2013-01-17
Publication date: 2014-07-28

Abstract

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate including a base region and an impurity region; An impurity layer formed corresponding to the base region on the semiconductor substrate and having a conductivity type different from that of the impurity region; An oxide film located between the impurity layer and the semiconductor substrate; A first electrode connected to the impurity region; And a second electrode connected to the impurity layer.

Description

Solar cell {SOLAR CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a solar cell having an improved structure.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

The solar cell may be formed by forming a conductive region and an electrode electrically connected to the conductive region on the semiconductor substrate so as to cause photoelectric conversion. In addition, a solar cell is formed with a passivation film for passivating a conductive region to improve characteristics, and an antireflection film for preventing reflection.

However, in the conventional solar cell, the efficiency of the solar cell may be lowered due to the recombination in the semiconductor substrate and the long travel distance of the carrier. Therefore, it is required to be designed so as to maximize the efficiency of the solar cell.

The present invention provides a solar cell capable of maximizing efficiency.

According to the embodiments of the present invention, it is possible to optimize the structure of the impurity region included in the semiconductor substrate and the impurity layer formed in the semiconductor substrate to effectively prevent the recombination of erasures and to minimize the movement distance of the carriers. An oxide film is provided between the semiconductor substrate and the impurity layer to improve the interface characteristics and smoothly transfer carriers generated by the tunneling to the second electrode. In addition, since both the impurity region and the impurity layer are located on the back surface of the semiconductor substrate, it is possible to minimize the shading loss of light incident on the front surface of the semiconductor substrate. Thus, the efficiency of the solar cell can be maximized.

1 is a rear plan view of a solar cell according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line II-II in FIG.
3 is a rear plan view of a solar cell according to a modification of the present invention.
4 is a rear plan view of a solar cell according to another modification of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a rear plan view of a solar cell according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG.

1, a solar cell 100 according to the present embodiment includes a substrate 110 (hereinafter referred to as a "semiconductor substrate") on which a plurality of unit cells 120 are placed, The first and second electrodes 24,

At this time, in this embodiment, the plurality of unit cells 120 may have a honeycomb shape as an example. That is, each of the unit cells 120 may have a hexagonal cross-sectional shape, and the center of the three adjacent unit cells 120 may be triangular. If the plurality of unit cells 120 have a honeycomb shape as described above, the unit cells 120 can be arranged most densely, thereby increasing the number of unit cells 120 disposed in the same area and improving the efficiency of the solar cell 100 can do.

However, the present invention is not limited thereto. 3, each of the unit cells 120 may have a rectangular shape and a plurality of unit cells 120 may be arranged in a matrix. The shape of each unit cell 120 and the arrangement of the plurality of unit cells 120 can be variously modified. For example, each unit cell 120 may have a circular shape, an elliptical shape, or various polygonal shapes, and a plurality of adjacent unit cells 120 may be arranged to have various shapes such as a matrix shape and a rhombus shape .

The structure of each unit cell 120 and the structure of the first and second electrodes 24 and 34 will be described in detail with reference to FIG.

The semiconductor substrate 110 includes an impurity region 20 that constitutes a part of the semiconductor substrate 110 and the semiconductor substrate 110 has a material and / or a crystal structure different from that of the semiconductor substrate 110 The impurity layer 30 of the conductivity type opposite to that of the impurity region 20 is formed.

More specifically, the semiconductor substrate 110 includes an impurity region 20 and a base region 10 having different conductivity types. At this time, the impurity region 20 is doped with an impurity opposite to the conductivity type to the base region 10, and has the same material and crystal structure as the base region 10, and is a different conductivity type region. For example, the semiconductor substrate 110 made of the base region 10 may be prepared, and then the impurity region 20 may be formed by doping a portion of the semiconductor substrate 110 with impurities. As the doping method, various methods such as heat diffusion method and ion implantation method can be used. Thus, the semiconductor substrate 110 including the base region 10 and the impurity region 20 can be formed.

The base region 10 may comprise, for example, silicon containing a first conductivity type impurity. As the silicon, single crystal silicon may be used, and the first conductivity type impurity may be n-type, for example. That is, in this embodiment, n-type impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) which are Group 5 elements as impurities for the base region 10 can be used.

The impurity region 20 may include, for example, silicon having a second conductivity type impurity. As the silicon, single crystal silicon may be used, and the second conductivity type impurity may be p-type, for example. That is, a p-type impurity such as boron (B), aluminum (Al), gallium (Ga), or indium (In), which is a Group 3 element, can be used as an impurity for forming the impurity region 20 in this embodiment.

As described above, the base region 10 and the impurity region 20 have different conductivity types to form a pn junction. When the pn junction is irradiated with light, the carriers generated by the photoelectric effect are collected by the first and second electrodes 24 and 34, and electric energy is generated. At this time, since the p-type impurity region 20 is formed widely, holes having a low moving speed can be effectively collected.

Referring to FIG. 2, in this embodiment, the impurity region 20 may be located on the rear surface of the semiconductor substrate 10. The impurity region 20 includes a first portion 20a having a relatively high impurity concentration and a relatively low resistance and a second portion 20b having a relatively high impurity concentration and having a lower impurity concentration than the first portion 20a. Lt; RTI ID = 0.0 > 20b. &Lt; / RTI > The first portion 20a is formed to be in contact with a part or all (i.e., at least a part of) the first electrode 24.

As described above, in this embodiment, a second portion 20b having a relatively high resistance is formed at a portion where the first electrode 24 is not formed, thereby implementing a shallow emitter. Thus, the current density of the solar cell 100 can be improved. In addition, it is possible to reduce the contact resistance with the first electrode 24 by forming the first portion 20a having a relatively low resistance at the portion adjacent to the first electrode 24. [ That is, the emitter layer 20 of this embodiment can maximize the efficiency of the solar cell 100 by the selective emitter structure.

However, the present invention is not limited thereto, and the impurity region 20 may have a homogeneous emitter structure having a uniform doping concentration. Of course, various modifications are possible.

Referring again to FIG. 1, the impurity region 20 may be formed corresponding to the central portion of the unit cell 120. The first portion 20a may be formed in an island shape at the center of each unit cell and the second portion 20b may be formed to be wider than the first portion 20a in the peripheral portion of the first portion 20a .

The second portion 20b realizes a shallow emitter and contributes substantially to photoelectric conversion, and is formed wider than the first portion 20a, so that photoelectric conversion can be smoothly performed. The second portions 20b may be spaced apart from each other to correspond to the unit cells 120 as shown in FIG. However, the present invention is not limited thereto, and the second portion 20b may be connected to each other in the neighboring unit cell 120 in the direction in which the first electrode 24 extends (the horizontal direction in the drawing). Although the second portion 20b has a circular shape and is spaced apart from the impurity layer 30 in plan view, the present invention is not limited thereto. That is, the second portion 20b may have a hexagonal shape or other various shapes so as to correspond to the shape of the unit cell 120, and may have a shape other than a portion connected to the impurity layer 30 or a portion thereof Or may be formed in all portions. Thus, the shape of the second portion 20b can be variously modified.

At this time, the second portion 20b may be doped to a relatively low concentration that does not increase the series resistance to minimize the Auger recombination. In one example, the doping concentration of the first portion 20a may be between 1 × 10 ¹⁷ / cm ³ and 1 × 10 ¹⁹ / cm ³ . This doping concentration is such that photoelectric conversion can occur well without increasing the series resistance.

The carrier formed by the second portion 20b is collected into the first portion 20a located at the central portion of the unit cell 120 and is transferred to the first electrode 24. When the first portion 20a is positioned at the center of the unit cell 120 as in the present embodiment, the distance of movement of the generated carrier to the first portion 20a can be minimized, and the collection efficiency of the carrier can be improved .

Then, the impurity layer 30 is located apart from the impurity region 20. In this embodiment, the impurity layer 30 may be a separate layer having a crystal structure different from that of the semiconductor substrate 110. In one example, the impurity layer 30 may be a polycrystalline silicon layer including a first conductivity type impurity (for example, n-type). At this time, the impurity layer 30 is formed of polycrystalline silicon and can be easily manufactured by various methods. The impurity layer 30 may be formed by chemical vapor deposition or the like and the first conductive impurity may be doped in the process of forming the impurity layer 30. [ For example, the impurity layer 30 can be formed while a gas containing the first conductive impurity is injected into the gas used in the chemical vapor deposition method. Alternatively, after the impurity layer 30 is formed, a first conductive impurity may be doped separately to form the impurity layer 30 including the first conductive impurity.

An oxide film 32 may be positioned between the impurity layer 30 and the semiconductor substrate 110. This oxide film 32 can effectively prevent the recombination due to the tunneling effect while improving the interface characteristics between the impurity layer 30 and the semiconductor substrate 110. The thickness of the oxide film 32 may be 5 nm or less and 0.5 nm to 5 nm (for example, 0.5 nm to 2 nm) in order to sufficiently realize the tunneling effect. If the thickness of the oxide film 32 exceeds 5 nm, the tunneling may not occur smoothly and the solar cell 100 may not operate. If the thickness of the oxide film 32 is less than 0.5 nm, the recombination characteristics may be deteriorated. In order to further improve the tunneling effect, the thickness of the oxide film 32 may be 0.5 nm to 2 nm. However, the present invention is not limited thereto, and the thickness of the oxide film 32 may be varied.

Referring to FIG. 1, the impurity layer 30 and the oxide film 32 may be located at a boundary portion of a plurality of unit cells 120, and more specifically, May be continuously formed along the edges of the first electrode 120 that intersect with each other. For example, the impurity layer 30 and the oxide film 32 may be formed in one direction while having a zigzag shape.

As described above, in this embodiment, the n-type impurity layer 30, which may cause a large amount of erase recombination, may be formed as a separate layer from the semiconductor substrate 110 to prevent the occurrence of erasure recombination in the semiconductor substrate 110 . An oxide film 32 is disposed between the impurity layer 30 and the semiconductor substrate 110 to improve the interface characteristics and smoothly transfer carriers generated by the tunneling to the second electrode 34.

The insulating layer 40 is formed on one surface of the semiconductor substrate 110 (more specifically, the rear surface where the impurity region 20 and the impurity layer 30 are located). The insulating layer 40 is formed covering the semiconductor substrate 110 and a part of the impurity layer 30 so as to insulate the impurity region 20 from the impurity layer 30.

In addition, the insulating layer 40 plays a role of passivation. In this embodiment, the insulating layer 40 may include aluminum oxide, zirconium oxide, hafnium oxide, or the like, which is suitable for passivation of the p-type impurity region 20. These oxides can induce field effect passivation due to the high negative charge as compared with other materials used as a passivation film. Thus, the impurity region 20 of p-type can be effectively passivated. In particular, the insulating layer 40 can be formed using aluminum oxide since effective passivation is possible and easy to manufacture.

The insulating layer 40 is provided with openings 40a and 40b which expose a part of the impurity layer 30 and a part of the impurity region 20 and are electrically connected to the first and second electrodes 24 And 34 are electrically connected to the impurity region 20 and the impurity layer 30, respectively.

The first electrode 24 may be formed to correspond to the center portion of the unit cell 120 and may be point-contacted with the first portion 20a at a portion corresponding to the first portion 20a. That is, the first electrode 24 may be point-contacted with the first portion 20a at a portion where the first portion 20a is formed while being extended in one direction on the insulating layer 40. [ However, the present invention is not limited thereto. Accordingly, when the first portion 20a has a long continuous shape, the first electrode 24 can be entirely contacted with the first portion 20a.

The second electrode 34 may be formed to correspond to the boundary portion of the unit cell 120 and may be partially contacted with the impurity layer 30 at a portion corresponding to the impurity layer 30. [ Alternatively, it may be entirely contacted at the boundary portion of the unit cell 120. However, the present invention is not limited thereto. As shown in FIG. 4, the second electrode 34 may be continuously formed along two adjacent edges of the unit cells 120 to have a zigzag shape. That is, the second electrode 34 may have substantially the same shape as the impurity layer 20, or may have a shape corresponding to each other, and the second electrode 34 may be formed on the impurity layer 30 to have a wide connection area. Thus, electrical characteristics and stability can be improved.

Since the first electrode 24 is formed through the center portion of the unit cell 120 and the second electrode 34 is formed at the boundary portion of the unit cell 120 in the present embodiment, The second electrodes 34 may be alternately positioned one at a time. If the first and second electrodes 24 and 34 include the same material, they may be formed together in one process.

The opening 40a may be formed in the insulating layer 40 and the first electrode 24 may be formed in the opening 40a by various methods such as a plating method and a deposition method. The opening 40b may be formed in the insulating layer 40 and the second electrode 34 may be formed in the opening 40b by various methods such as a plating method and a vapor deposition method.

Alternatively, the first and second electrode-forming paste may be applied on the insulating layer 40 by screen printing or the like, and then, through a fire through or a laser firing contact, And the second electrodes 24 and 34 may be formed. In this case, since the openings 40a and 40b are formed during the firing process, the step of forming the openings 40a and 40b may not be performed in advance.

Meanwhile, the front surface and / or the rear surface of the semiconductor substrate 110 may be textured to have irregularities such as pyramids. If the surface roughness of the semiconductor substrate 110 is increased due to such irregularities formed on the front surface of the semiconductor substrate 110, the reflectance of light incident through the front surface of the semiconductor substrate 110 can be reduced. Therefore, the amount of light reaching the pn junction formed at the interface between the semiconductor substrate 110 and the impurity region 20 can be increased, so that the optical loss can be minimized. In the present embodiment, concavities and convexities are formed only on the front surface of the semiconductor substrate 110, but the present invention is not limited thereto.

The entire front layer 50 may be formed on the front surface of the semiconductor substrate 110. The front whole layer 50 is a region doped with impurities at a concentration higher than that of the semiconductor substrate 110 and functions similarly to a back surface field (BSF). That is, electrons and holes separated by incident sunlight are prevented from recombining and disappearing on the front surface of the semiconductor substrate 110.

An antireflection layer 60 may be formed on the entire front layer 50. The antireflection film 60 may be formed entirely on the front surface of the semiconductor substrate 10. The antireflection film 60 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10 and immobilizes defects existing in the surface or bulk of the front surface front layer 50.

The amount of light reaching the pn junction formed at the interface between the base region 10 and the impurity region 20 can be increased by lowering the reflectance of light incident through the entire surface of the semiconductor substrate 110. [ Accordingly, the short circuit current Isc of the solar cell 100 can be increased. The defect can be passivated and the recombination site of the minority carriers can be removed to increase the open-circuit voltage (Voc) of the solar cell 100. Thus, the conversion efficiency of the solar cell 100 can be improved by increasing the open-circuit voltage and the short-circuit current of the solar cell 100 with the anti-reflection film 60.

The anti-radiation film 60 may be formed of various materials. For example, the antireflection film 60 may be formed of any one single film selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , And may have a combined multilayer structure. However, the present invention is not limited thereto, and it goes without saying that the anti-reflection film 60 may include various materials.

According to the embodiment of the present invention, the impurity region 20 formed in the semiconductor substrate 110 has a less conductive type of ohmic recombination, and the conductive type impurity layer 30, Is formed on the semiconductor substrate 110 as a separate layer. Accordingly, it is possible to effectively prevent the recombination of electrons in the semiconductor substrate 110.

At this time, an oxide film 32 is provided between the semiconductor substrate 110 and the impurity layer 30 to improve the interfacial characteristics and smoothly transfer carriers generated by the tunneling to the second electrode 34. The impurity region 20 is located at the central portion of the unit cell 120 and the impurity layer 30 is located at the boundary portion of the unit cell 120 so that the photoelectric conversion is performed over a wide area, The moving distance can be reduced.

The impurity region 30 and the first and second electrodes 24 and 34 are all located on the rear surface of the semiconductor substrate 110 so that the light incident on the front surface of the semiconductor substrate 110 Shading loss can be minimized.

As described above, according to the present embodiment, efficiency of the solar cell 100 can be maximized by optimizing the structure so as to prevent recombination, reduce the moving distance of the carrier, and minimize the shading loss.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
110: semiconductor substrate
10: Base area
20: impurity region
24: first electrode
30: impurity layer
32: oxide film
34: Second electrode
40: Insulating layer
50: Front whole layer
60: antireflection film

Claims

A semiconductor substrate including a base region and an impurity region;
An impurity layer formed corresponding to the base region on the semiconductor substrate and having a conductivity type different from that of the impurity region;
An oxide film located between the impurity layer and the semiconductor substrate;
A first electrode connected to the impurity region; And
And a second electrode connected to the impurity layer
&Lt; / RTI >

The method according to claim 1,
Wherein the impurity layer has a crystal structure different from that of the semiconductor substrate.

3. The method of claim 2,
Wherein the semiconductor substrate has a single crystal structure,
Wherein the impurity layer has a polycrystalline structure.

The method according to claim 1,
Wherein the oxide film has a thickness of 0.5 nm to 5 nm.

The method according to claim 1,
Wherein the base region is of a first conductivity type,
The impurity region is of the second conductivity type,
Wherein the impurity layer is the first conductive type.

The method according to claim 1,
Wherein the impurity region is p-type,
Wherein the impurity layer is n-type.

The method according to claim 1,
Wherein the impurity region includes a first portion having a first resistance, and a second portion having a resistance higher than the first resistance.

The method according to claim 1,
The first portion is formed in an island shape,
Wherein the second portion is formed in a peripheral portion of the first portion to have a larger area than the first portion.

The method according to claim 1,
And an insulating layer covering the semiconductor substrate and insulating the impurity region from the impurity layer.

10. The method of claim 9,
Wherein the first electrode is connected to the impurity region through a first opening formed in the insulating layer,
And the second electrode is connected to the impurity layer through a second opening formed in the insulating layer.

10. The method of claim 9,
Wherein the insulating layer comprises at least one of aluminum oxide, zirconium oxide, and hafnium oxide.

The method according to claim 1,
Wherein the semiconductor substrate is divided into a plurality of unit cells,
The impurity region is located at a central portion of the unit cell,
Wherein the impurity layer is located at a boundary portion of the unit cell.

13. The method of claim 12,
The impurity region is formed in an island shape in each unit cell,
Wherein the impurity layer is formed to extend over the plurality of unit cells.

13. The method of claim 12,
Wherein the impurity region is formed so as to extend across the plurality of unit cells in a direction in which the first electrode extends.

13. The method of claim 12,
Wherein the plurality of unit cells have a honeycomb shape.

16. The method of claim 15,
Wherein the impurity layer is continuously formed in the plurality of unit cells to have a zigzag shape.

17. The method of claim 16,
Wherein the second electrode is elongated in a straight line.

17. The method of claim 16,
And the second electrode has a zigzag shape corresponding to the impurity layer.

16. The method of claim 15,
Wherein the impurity region includes a first portion having a first resistance and a second portion having a resistance higher than the first resistance,
Wherein the first electrode is point-contacted to the first portion while being extended over the plurality of unit cells.

13. The method of claim 12,
Wherein each unit cell has a shape of a circle, an ellipse, or a polygon.

The method according to claim 1,
Wherein the impurity region, the impurity layer, and the first and second electrodes are located on the rear surface of the semiconductor substrate.