KR20140093037A - Driving integrated circuit for display device - Google Patents

Abstract

The present invention relates to a driver integrated circuit for a display device capable of reducing power consumption. The driver integrated circuit for the display device comprises; a driving voltage producing unit which produces a low level driving voltage lower than a normal driving voltage when a reset signal from the outside is in a non-active state and produces the normal driving voltage when the reset signal from the outside is in a set-up state and an active state; and a panel driving unit which receives the low level driving voltage and the normal driving voltage in order from the driving voltage producing unit, produces all kinds of driving control signals necessary to drive a display panel by being driven according to the low level driving voltage, and supplies the driving control signals to the display panel when the reset signal from the outside is in the active state.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a driving integrated circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving integrated circuit for a display device, and more particularly to a driving integrated circuit for a display device capable of reducing power consumption.

The driving integrated circuit is driven by receiving a power supply voltage from the system. At this time, the driving integrated circuit generates a driving voltage from the point of time when the power supply voltage is input, and operates on the basis of the generated driving voltage, and conventionally, there is a problem that the power consumption of the driving integrated circuit becomes high because the voltage is relatively high.

  SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-mentioned problems, and it is an object of the present invention to provide a method and a device for driving a driving integrated circuit using a low level driving voltage having a magnitude lower than a normal driving voltage when the reset signal is non- And to reduce the power consumption by driving the driving integrated circuit by using the normal driving voltage when the driving integrated circuit is driven.

According to an aspect of the present invention, there is provided a drive integrated circuit for a display device, the drive integrated circuit including: a reset driving circuit for generating a low level drive voltage having a magnitude smaller than a normal drive voltage when a reset signal from the outside is inactive, A driving voltage generator for generating the normal driving voltage when the signal is in a setup state and an active state; And a low level driving voltage and a normal driving voltage sequentially from the driving voltage generating unit and driven according to the low level driving voltage to generate various driving control signals required for driving the display panel, And a panel driver for supplying the drive control signals to the display panel when the display panel is in an active state.

Wherein the driving voltage generator outputs an input / output power supply voltage of a low level when the reset signal is in an inactive state and outputs an input / output power supply voltage of a high level when the reset signal is in a set state and an active state; A low level voltage generating unit for generating the low level driving voltage according to a low level input / output power supply voltage supplied from the output control unit and supplying the low level driving voltage to the panel driving unit; And a normal level voltage generator for generating the normal driving voltage according to the high level input / output power supply voltage supplied from the output controller and supplying the normal driving voltage to the panel driving unit.

Wherein the output control unit includes a reset switch connected between an input / output power supply line for transmitting the input / output power supply voltage and an input terminal, the reset control being controlled according to a reset signal from the outside; When the reset signal is in an inactive state, the input node is maintained at a low level input / output power supply voltage.

Wherein the low level voltage generator comprises: a inverter for inverting a level of an input / output power supply voltage applied to the input terminal; And a first switch connected between an output terminal and a power supply line which is controlled in accordance with an output from the inverter and transmits a power supply voltage from the outside; And the output terminal is connected to the panel driving unit.

The normal level voltage generator includes: a resistor; A comparator that compares a preset reference voltage with a voltage applied to one terminal of the resistor and adjusts the magnitude of the output based on the comparison result; A constant current switch controlled according to an output from the comparator and connected between the power supply line and the other terminal of the resistor; And a second switch connected between one terminal of the resistor and the output terminal, the second switch being controlled according to an input / output power supply voltage applied to the input terminal.

The power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level when power is input to the display device; Wherein the reset signal is sequentially changed from the inactive state to the set state and the active state after the power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level.

The channel resistance of the second switch is smaller than the channel resistance of the first switch and the channel resistance of the second switch is equal to the channel resistance of the constant current switch.

The reset signal has a low level when the reset signal is in an inactive state, alternates between a high level and a low level in a setup state, and has a high level when the reset signal is in an active state.

According to another aspect of the present invention, there is provided a driving integrated circuit for a display device, the driving integrated circuit including a driving circuit for generating a low level driving voltage having a magnitude smaller than a normal driving voltage when the reset signal from the outside is in an inactive state and a set- A driving voltage generator for generating the normal driving voltage when an external reset signal is active; And a low level drive voltage and a normal drive voltage from the drive voltage generation unit and is driven in accordance with the low level drive voltage to generate various drive control signals required for driving the display panel, And a panel driver for supplying the drive control signals to the display panel when the display panel is in an active state.

Wherein the driving voltage generator outputs an input / output power supply voltage of a low level when the reset signal is in an inactive state and a setup state and outputs an input / output power supply voltage of a high level when the reset signal is in an active state; A low level voltage generating unit for generating the low level driving voltage according to a low level input / output power supply voltage supplied from the output control unit and supplying the low level driving voltage to the panel driving unit; And a normal level voltage generator for generating the normal driving voltage according to the high level input / output power supply voltage supplied from the output controller and supplying the normal driving voltage to the panel driving unit.

The reset signal having a low level when the reset signal is inactive, alternating between a high level and a low level when in a setup state, and a high level when in an active state; The output control unit starts counting each time the reset signal from the outside is maintained at a high level and outputs a reset signal of a high level when the counted value becomes 2. When the counted value is less than 2 A counter for outputting a reset signal of a low level; And a reset switch connected between the input node and the input / output power supply line for transmitting the input / output power supply voltage, the reset switch being controlled according to a reset signal provided from the counter; When the reset signal is in an inactive state, the input node is maintained at a low level input / output power supply voltage.

Wherein the low level voltage generator comprises: a inverter for inverting a level of an input / output power supply voltage applied to the input terminal; And a first switch connected between the power supply line and the output terminal, the power supply line being controlled according to an output from the inverter and transmitting a power supply voltage from the outside; And the output terminal is connected to the panel driving unit.

The normal level voltage generator includes: a resistor; A comparator that compares a preset reference voltage with a voltage applied to one terminal of the resistor and adjusts the magnitude of the output based on the comparison result; A constant current switch between the power supply line and the other terminal of the resistor, the constant current switch being controlled according to an output from the comparator; And a second switch connected between one terminal of the resistor and the output terminal, the second switch being controlled according to an input / output power supply voltage applied to the input terminal.

The power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level when power is input to the display device; Wherein the reset signal is sequentially changed from the inactive state to the set state and the active state after the power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level.

The channel resistance of the second switch is smaller than the channel resistance of the first switch and the channel resistance of the second switch is equal to the channel resistance of the constant current switch.

And a power sensing unit for sensing a state of the power source voltage and discharging the voltage of the input terminal to the ground when the power source voltage drops to a low level.

The driving integrated circuit for a display device according to the present invention has the following effects.

First, since the driving voltage is maintained at a lower level than the normal voltage during the time from when the power supply voltage is input to the driving integrated circuit to when the reset signal is set to the set state or the active state, the power consumption can be reduced compared to the conventional case.

Second, since the low level drive voltage rises to the normal drive voltage when the reset signal is active, when the drive integrated circuit supplies the drive control signals to the display panel (that is, when the reset signal is active) It is possible to prevent a phenomenon in which the driving voltage is instantaneously reduced by the load.

1 is a view showing a display device according to an embodiment of the present invention;
Fig. 2 is a detailed configuration diagram of the display panel of Fig. 1
Fig. 3 is a detailed configuration diagram of the driving integrated circuit of Fig. 1
4 is a diagram showing a first embodiment of the driving voltage generating unit of FIG. 3; FIG.
5 is a view for explaining the operation of the driving voltage generator according to the first embodiment;
6 is a view showing a second embodiment of the driving voltage generating unit of FIG. 3; FIG.
7 is a view for explaining the operation of the driving voltage generator according to the second embodiment;
8 is a view showing a third embodiment of the driving voltage generating unit of FIG. 3; FIG.
9 is a view for explaining a comparison between a low level drive voltage and a normal drive voltage;
10 is a graph showing a simulation result using a driving integrated circuit according to an embodiment of the present invention

FIG. 1 is a view showing a display device according to an embodiment of the present invention, and FIG. 2 is a detailed configuration diagram of the display panel of FIG.

The display device according to the embodiment of the present invention includes a system SYS, a drive IC (D-IC) and a display panel (DSP) as shown in Fig.

As shown in Fig. 2, the display panel DSP includes i * j pixels PX, i (i is a natural number greater than 1) gate lines, j And a plurality of data lines DL1 to DLj. Here, the gate signals GS are applied to the gate lines. Specifically, first to i-th gate signals are applied to the first to i-th gate lines GL1 to GLi, respectively. The data voltages DV are applied to the first to j-th data lines DL1 to DLj.

These pixels PX are arranged in a matrix form on the display panel DSP. These pixels PX are divided into a red pixel R for displaying red, a green pixel G for displaying green, and a blue pixel B for displaying blue. At this time, the red pixels, the green pixels and the blue pixels R, G, B adjacent in the horizontal direction are unit pixels for displaying one unit image.

J pixels (hereinafter, the nth horizontal line pixels) arranged along the nth horizontal line (n is any one of 1 to i) are connected in common to one gate line, and the first to jth data And are individually connected to each of the lines DL1 to DLj.

Though not shown in the figure, each pixel includes a thin film transistor that turns on according to a gate signal from a gate line to switch a data voltage DV from the data line, and a thin film transistor A common electrode disposed opposite to the pixel electrode, and a liquid crystal cell disposed between the pixel electrode and the common electrode. Here, the pixel electrodes are individually provided for each pixel, while the common electrode is provided for only one pixel.

The system SYS outputs a vertical synchronizing signal, a horizontal synchronizing signal, a clock signal, and image data (Img-Data) through an interface circuit through a low voltage differential signaling (LVDS) transmitter of a graphic controller. The system SYS also supplies the power supply voltage VCI, the input / output power supply voltage IOVCC, the reference power supply voltage VCC, the first reference voltage DDVDH, the second reference voltage DDVDL, and the reset signal RESET And outputs it. A horizontal synchronization signal, a clock signal video data, a power supply voltage VCI, an input / output power supply voltage IOVCC, a reference power supply voltage VCC, a first reference voltage DDVDH, and a first reference voltage DDVDH output from the system SYS. 2 reference voltage DDVDL and the reset signal RESET are input to the driving integrated circuit D-IC.

The driving integrated circuit D-IC receives the vertical synchronizing signal, the horizontal synchronizing signal, the clock signal, the image data, the power supply voltage VCI, the input / output power supply voltage IOVCC, the reference power supply voltage VCC, The first reference voltage DDVDH, the second reference voltage DDVDL, and the reset signal RESET to generate various drive control signals necessary for driving the display panel DSP. For example, these various drive control signals include a data voltage DV, a gate signal GS and a common voltage Vcom. Here, the data voltage DV is an analog signal for the image data Img-Data, which is a digital signal.

Here, the construction of the driving integrated circuit (D-IC) will be described in detail as follows.

3 is a detailed configuration diagram of the driving integrated circuit (D-IC) of FIG.

The driving integrated circuit (D-IC) includes a driving voltage generating section 301 and a panel driving section 302, as shown in Fig.

The driving voltage generating unit 301 receives the power supply voltage VCI, the input / output power supply voltage IOVCC and the reset signal RESET from the system SYS to generate the low level driving voltage VDD_L and the normal driving voltage VDD_N , And sequentially supplies them to the panel driving unit 302. Here, the low level drive voltage VDD_L has a voltage value lower than the normal drive voltage VDD_N. The driving voltage generating unit 301 generates the inactive state low level driving voltage VDD_L and supplies it to the panel driving unit 302 while the reset signal RESET is in the set state and the active state And supplies the normal driving voltage VDD_N to the panel driver 302.

The panel driving unit 302 is driven by sequentially receiving the low level driving voltage VDD_L and the normal driving voltage VDD_N from the driving voltage generating unit 301. That is, the panel driver 302 is driven in accordance with the low-level driving voltage VDD_L inputted in order to generate various driving control signals necessary for the display panel DSP. Thereafter, the panel driver 302 is driven in accordance with the normal driving voltage VDD_N. The panel driver 302 supplies the above-described various drive control signals to the display panel DSP when the reset signal RESET becomes active.

The reset signal RESET is a signal that determines the timing at which the driving integrated circuit D-IC supplies the above-described driving control signals to the display panel DSP. This reset signal RESET is input to the driving IC D- (I.e., when the power supply voltage VCI is at a low level) before the power supply voltage VCI is input. This reset signal RESET remains inactive for a predetermined time after the power supply voltage VCI is input to the driving integrated circuit D-IC (i.e., the power supply voltage VCI becomes high level) And then changes to a setup state and an active state.

As described above, according to the present invention, during a period from when the power supply voltage VCI is input to the driving integrated circuit (D-IC) to when the reset signal RESET becomes the set-up state or the active state, The power consumption can be reduced as compared with the conventional case. On the other hand, since the driving voltage is restored to the original normal value at the time when the driving control signals are supplied to the display panel DSP, that is, when the reset signal RESET changes to the active state, the load of the display panel As shown in Fig.

Further, since the low level drive voltage rises to the normal drive voltage when the reset signal is active, when the drive integrated circuit supplies the drive control signals to the display panel (i.e., when the reset signal is active) It is possible to prevent a phenomenon in which the driving voltage is instantaneously reduced by the load.

Meanwhile, the driving voltage generator 301 according to the present invention may have the following configuration.

FIG. 4 is a diagram illustrating a first embodiment of the driving voltage generator 301 of FIG. 3. Referring to FIG.

4, the driving voltage generating unit 301 includes an output control unit 401, a low level voltage generating unit 402, and a normal level voltage generating unit 403.

The output controller 401 outputs a low level input / output power supply voltage IOVCC when the reset signal RESET is inactive. When the reset signal RESET is in the setup and active states, the output controller 401 outputs a high level input / (IOVCC).

The output control unit 401 includes a reset switch Tr_R which is controlled in response to a reset signal RESET from the system SYS and has an input / And is connected between the power supply line and the input terminal IT. The reset switch Tr_R is turned on or off according to the reset signal RESET from the system SYS and applies the input / output power supply voltage IOVCC at the turn-on to the input terminal IT.

On the other hand, when the reset signal RESET is in the inactive state, the input terminal IT is maintained at the input / output power supply voltage IOVCC of low level. That is, when the power of the display device is turned off, the reset signal RESET, the power supply voltage VCI, the input / output power supply voltage IOVCC, the reference power supply voltage VCC, the first reference voltage DDVDH, The reset signal RESET drops to the ground level later than the input / output power supply voltage IOVCC. Therefore, the reset signal RESET is reset to the ground level after the display device is powered off, ) Falls to a low level.

The low level voltage generating unit 402 generates the low level driving voltage VDD_L in accordance with the low level input / output power supply voltage IOVCC supplied from the output control unit 401 and supplies the low level driving voltage VDD_L to the panel driving unit 302.

The low-level voltage generator 402 includes an inverter INV and a first switch Tr1.

The inverter INV inverts the level of the input / output power supply voltage IOVCC applied to the input terminal IT. For example, if a high level input / output power supply voltage IOVCC is applied to the input terminal IT, the inverter INV outputs a low level input / output power supply voltage IOVCC.

The first switch Tr1 is controlled according to the output from the inverter INV and is connected between the power supply line for transmitting the power supply voltage VCI and the output terminal OT. The first switch Tr1 is turned on or off according to an output from the inverter INV and outputs the turn-on power supply voltage VCI as a low level drive voltage. The low-level driving voltage output through the first switch Tr1 is input to the panel driver 302 through the output terminal OT. Here, the low-level driving voltage applied to the output terminal OT due to the channel resistance of the first switch Tr1 has a value smaller than the power supply voltage VCI.

The normal level voltage generator 403 generates the normal driving voltage VDD_N according to the high level input / output power supply voltage IOVCC supplied from the output controller 401 and supplies the normal driving voltage VDD_N to the panel driver 302.

The normal level voltage generator 403 includes a resistor R, a comparator COM, a constant current switch Tr_C, and a second switch Tr2.

The comparator COM compares a preset reference voltage Vref with a voltage applied to one terminal of the resistor R, and adjusts the magnitude of the output based on the comparison result. A reference voltage Vref is applied to the first input terminal IT of the comparator COM and a terminal voltage of the resistor R is applied to the second input terminal IT. An output according to the comparison result is output to the output terminal OT of the comparator COM. That is, when the voltage applied to the second input terminal IT is smaller than the reference voltage Vref, the comparator COM outputs the reference voltage Vref when the voltage (one terminal voltage of the resistor R) becomes equal to the reference voltage Vref To increase its output to. On the other hand, when the voltage applied to the second input terminal IT is larger than the reference voltage Vref, the comparator COM outputs the voltage Vref of the self- Decrease the output.

The constant current switch Tr_C is controlled in accordance with the output from the comparator COM and is connected between the power supply line and the other terminal of the resistor R. [ The constant current switch Tr_C adjusts the amount (current density) of the current flowing from the power supply line toward the resistor R in accordance with the output from the comparator COM.

The second switch Tr2 is controlled in accordance with the input / output power supply voltage IOVCC applied to the input terminal IT and is connected between one terminal of the resistor and the output terminal OT. The second switch Tr2 is turned on or off according to the input / output power supply voltage IOVCC and outputs one terminal voltage of the resistor R at the turn-on time as the normal driving voltage VDD_N. The normal driving voltage VDD_N output through the second switch Tr2 is input to the panel driver 302 through the output terminal OT. Here, the normal driving voltage VDD_N applied to the output terminal OT due to the channel resistance of the second switch Tr2 has a value smaller than the power supply voltage VCI. At this time, the channel area of the second switch Tr2 is set to be larger than the channel area of the first switch Tr1 described above, so that the channel resistance of the second switch Tr2 is larger than the channel area of the first switch Tr1 Becomes smaller than the resistance. The channel area of the constant current switch Tr_C is also set to be larger than the channel area of the first switch Tr1. Here, the constant current switch Tr_C and the second switch Tr2 may have the same channel area. For example, if the channel width and the channel length of the constant current switch Tr_C are set to 20 [um] and 0.6 [um], respectively, the second switch Tr2 is also set to have the same channel width and channel length as the constant current switch Tr_C Lt; / RTI > At this time, the channel width and the channel length of the first switch Tr1 may be set to 4 [um] and 0.8 [um], respectively. Here, the larger the channel width, the smaller the channel resistance, while the longer the channel length, the greater the channel resistance.

In addition, the number of switches connected in parallel may be different from each other to adjust the channel resistance. For example, 30 constant current switches Tr_C having a channel area as described above are connected in parallel, thirty second switches Tr2 having a channel area as described above are connected in parallel, The channel resistance can be adjusted by connecting two first switches Tr1 having the same channel area as the first switch Tr1 in parallel.

Due to the difference in channel resistance, the low level drive voltage VDD_L output through the first switch Tr1 has a smaller value than the normal drive voltage VDD_N output through the second switch Tr2.

Hereinafter, the operation of the driving voltage generator 301 according to the first embodiment will be described with reference to FIGS. 4 and 5. FIG.

5 is a diagram for explaining the operation of the driving voltage generator 301 according to the first embodiment.

As shown in FIG. 5, when power is input to the display device at time T1, the power supply voltage VCI, the input / output power supply voltage IOVCC, and the reference power supply voltage VCC rise to a high level at that point. On the other hand, the reset signal RESET maintains the inactive state at the time T1. That is, the reset signal RESET is held at a low level. On the other hand, since the reset signal RESET is at the low level, the reset switch Tr_R supplied thereto is turned off. Therefore, the input / output terminal IT maintains the low input / output power supply voltage IOVCC. As a result, a high level input / output power supply voltage IOVCC is outputted from the inverter INV. The input / output power supply voltage IOVCC of the high level turns on the first switch Tr1, and the power supply voltage VCI is outputted through the turned-on first switch Tr1. The voltage output through the first switch Tr1 is directly the low level drive voltage VDD_L.

On the other hand, since the input terminal IT is maintained at the low-level input / output power supply voltage IOVCC at the time T1, the second switch Tr2 supplied with the low-level input / output power supply voltage IOVCC is turned off .

Therefore, at the time T1, the low level drive voltage VDD_L is applied to the output terminal OT through the first switch Tr1 turned on. The low level drive voltage VDD_L applied to the output terminal OT is supplied to the panel driver 302. This low level drive voltage VDD_L is a time at which the reset signal RESET changes from the time point when the power supply voltage VCI is raised to the high level ) To the panel driving unit 302. The panel driving unit 302 is provided with the panel driving unit 302 and the panel driving unit 302. That is, as shown in FIG. 5, the low level drive voltage VDD_L is supplied to the panel driver 302 from the time T1 to the time T2. The panel driver 302 operates according to the low level drive voltage VDD_L from the time T1 to the time T2, and generates various drive control signals based on the low level drive voltage VDD_L during this period.

During a period from time T2 to time T3, the reset signal RESET is maintained in a set-up state, during which the reset signal RESET sequentially has a high level and a low level. When this reset signal RESET becomes high level, the reset switch Tr_R supplied thereto is turned on. Then, a high level input / output power supply voltage IOVCC is applied to the input terminal IT through the turn-on reset switch Tr_R. Then, the first switch Tr1, which receives the high level input / output power supply voltage IOVCC through the inverter INV, is turned off. On the other hand, the first switch Tr1, which receives the high level input / output power supply voltage IOVCC, 2 switch Tr2 is turned on. Therefore, the normal driving voltage VDD_N is outputted through the turned-on second switch Tr2. The normal driving voltage VDD_N is supplied to the panel driver 302 through the output terminal OT.

On the other hand, when the reset signal RESET changes to the low level between the time T2 and the time T3, the reset switch Tr_R is turned off. At this time, the input terminal IT also has the high level input / output power supply voltage IOVCC. ≪ / RTI >

Thereafter, at time T3, the reset signal RESET changes to the active state. That is, at the time T3, the reset signal RESET changes to the high level. Then, the reset switch Tr_R is turned on, and the input / output power supply voltage IOVCC of high level is supplied again to the input terminal IT thereof.

On the other hand, as the reset signal RESET changes to the active state, the panel drive unit 302 transmits the above-described various drive control signals to the display panel DSP. That is, the panel driving unit 302 supplies the driving control signals to the display panel DSP in response to the reset signal RESET becoming active.

On the other hand, the reset signal RESET may be held at a high level for a short time before the power supply voltage VCI rises to a high level. At this time, the reset switch Tr_R is turned on, and the input / output power supply voltage IOVCC of low level is applied to the input terminal IT.

Meanwhile, the first reference voltage DDVDH and the second reference voltage DDVDL may be generated between the time T1 and the time T2.

Meanwhile, the driving voltage generator 301 according to the present invention may have the following configuration.

FIG. 6 is a diagram illustrating a second embodiment of the driving voltage generator 301 of FIG. 3. Referring to FIG.

6, the driving voltage generation section 301 includes an output control section 411, a low-level voltage generation section 402, and a normal level voltage generation section 403.

The output controller 411 outputs a low level input / output power supply voltage IOVCC when the reset signal RESET is in an inactive state and a setup state, and when the reset signal RESET is in an active state, (IOVCC).

This output control section 411 includes a counter CT and a reset switch Tr_R.

The counter CT starts a count every time the reset signal RESET from the system SYS is held at a high level and outputs a reset signal RESET of a high level when the counted value becomes 2 And outputs a low level reset signal RESET when the counted value is smaller than 2.

The reset switch Tr_R is controlled according to a reset signal RESET from the counter CT and is connected between an input / output power supply line for transmitting the input / output power supply voltage IOVCC and the input terminal IT. The reset switch Tr_R is turned on or off according to the reset signal RESET from the counter CT and applies the input / output power supply voltage IOVCC to the input terminal IT.

On the other hand, when the reset signal RESET is in the inactive state, the input terminal IT is maintained at the input / output power supply voltage IOVCC of low level. That is, when the power of the display device is turned off, the reset signal RESET, the power supply voltage VCI, the input / output power supply voltage IOVCC, the reference power supply voltage VCC, the first reference voltage DDVDH, The reset signal RESET drops to the ground level later than the input / output power supply voltage IOVCC. Therefore, the reset signal RESET is reset to the ground level after the display device is powered off, ) Falls to a low level.

On the other hand, the low-level voltage generator 402 and the normal-level voltage generator 403 in the second embodiment are respectively the same as those in the first embodiment described above, and therefore, description thereof will be omitted in the first embodiment described above do.

Hereinafter, the operation of the driving voltage generator 301 according to the second embodiment will be described with reference to FIGS. 6 and 7. FIG.

7 is a view for explaining the operation of the driving voltage generator 301 according to the second embodiment.

As shown in FIG. 7, when power is input to the display device at time T1, the power supply voltage VCI, the input / output power supply voltage IOVCC, and the reference power supply voltage VCC rise to a high level at that point. On the other hand, the reset signal RESET maintains the inactive state at the time T1. That is, the reset signal RESET is held at a low level. Since the reset signal RESET is at a low level, the counter CT supplied with the reset signal RESET outputs a low level reset signal RESET and supplies the reset signal RES_R to the reset switch Tr_R. Then, the reset switch Tr_R is turned off. Therefore, the input / output terminal IT maintains the low input / output power supply voltage IOVCC. As a result, a high level input / output power supply voltage IOVCC is outputted from the inverter INV. The input / output power supply voltage IOVCC of the high level turns on the first switch Tr1, and the power supply voltage VCI is outputted through the turned-on first switch Tr1. The voltage output through the first switch Tr1 is directly the low level drive voltage VDD_L.

On the other hand, since the input terminal IT is maintained at the low-level input / output power supply voltage IOVCC at the time T1, the second switch Tr2 supplied with the low-level input / output power supply voltage IOVCC is turned off .

Therefore, at the time T1, the low level drive voltage VDD_L is applied to the output terminal OT through the first switch Tr1 turned on. The low level drive voltage VDD_L applied to the output terminal OT is supplied to the panel driver 302. The low level drive voltage VDD_L is set to a time point T3 when the reset signal RESET changes from the active state to the active state at the time point T1 when the power source voltage VCI is raised to the high level ) To the panel driving unit 302. The panel driving unit 302 is provided with the panel driving unit 302 and the panel driving unit 302. That is, as shown in FIG. 7, the low level drive voltage VDD_L is supplied to the panel driver 302 from the time T1 to the time T3. The panel driver 302 operates according to the low level drive voltage VDD_L from the time T1 to the time T3 and generates the various drive control signals based on the low level drive voltage VDD_L during this period.

That is, the counter CT counts the high level of the reset signal RESET and outputs a high-level reset signal RESET at a time T3 when the count is high. At the time T3, The reset switch Tr_R is turned on by the reset signal RESET of the panel driver 302, thereby outputting the normal driving voltage VDD_N to the panel driver 302. Since the reset signal RESET becomes active at the time point T3, the panel drive unit 302 is driven by the normal drive voltage VDD_N and outputs the various drive control signals to the display panel DSP send.

On the other hand, the reset signal RESET may be held at a high level for a short time before the power supply voltage VCI rises to a high level. At this time, however, since the power supply voltage VCI is maintained at the low level, the counter CT is not operated and the reset signal RESET at this time is not counted.

Meanwhile, the first reference voltage DDVDH and the second reference voltage DDVDL may be generated between the time T1 and the time T2.

Meanwhile, the driving voltage generator 301 according to the present invention may have the following configuration.

8 is a view showing a third embodiment of the driving voltage generator 301 of FIG.

8, the driving voltage generating unit 301 includes an output control unit 411, a low level voltage generating unit 402, a normal level voltage generating unit 403, and a power sensing unit 800. [

The output control unit 401, the low-level voltage generation unit 402 and the normal level voltage generation unit 403 in the third embodiment are the same as those in the second embodiment described above. .

The power sensing unit 800 senses the state of the power supply voltage VCI and discharges the voltage of the input terminal IT to ground when the power supply voltage VCI falls to a low level. When the power of the display apparatus is turned off, the power supply voltage VCI falls to a low level, and the power sensing unit 800 then discharges the input terminal IT to the ground. Therefore, when the power of the display device is turned on, the input terminal IT thereof is kept in the low state, so that the low level drive voltage VDD_L as described above can be stably outputted.

The power sensing unit 800 may be installed in the driving voltage generator 301 of the first embodiment.

9 is a diagram for explaining a comparison between the low level drive voltage VDD_L and the normal drive voltage VDD_N.

9, the driving capability of the driving integrated circuit (D-IC) due to the low level driving voltage VDD_L is smaller than 1 to 2 [mA], and its output voltage (Ouput) About 1.3 to 1.4 [V], and its current consumption is less than 10 [uA].

However, the driving capability of the driving integrated circuit (D-IC) by the normal driving voltage (VDD_N) is larger than 20 to 30 [mA], its output voltage (Ouput) is about 1.5 [V] And its current consumption is greater than 50 [uA].

10 is a diagram showing a simulation result using a driving integrated circuit (D-IC) according to an embodiment of the present invention.

10, when the reset signal RESET is in an inactive state and a set-up state, a low-level driving voltage VDD_L is generated. When the reset signal RESET is in an active state, the normal driving voltage VDD_N is .

Meanwhile, the low level drive voltage VDD_L in the present invention is at least enough for the panel drive unit 302 to recognize the reset signal RESET inputted thereto and generate the various drive control signals and logic control signals described above .

On the other hand, in the first to third embodiments, the output terminal of the output control section 401 or 411 can be individually connected to the gate of the inverter INV and the gate of the second switch Tr2. The output terminal of the low level voltage generator 402 and the output terminal of the normal level voltage generator 403 may be connected to the panel driver 302 separately.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

D-IC: driving integrated circuit 301: driving voltage generating section
302: panel drive VCI: power supply voltage
IOVCC: I / O power voltage RESET: Reset signal
VDD_L: Low level drive voltage VDD_N: Normal drive voltage
Vcom: Common voltage DV: Data voltage
GS: Gate signal

Claims (16)

Generating a low level drive voltage having a magnitude smaller than a normal drive voltage when a reset signal from the outside is inactive and generating a drive voltage for generating the normal drive voltage when the reset signal from the outside is in a setup state and an active state, part; And
Level drive voltage and a normal drive voltage from the drive voltage generation unit and is driven according to the low level drive voltage to generate various drive control signals required for driving the display panel, And a panel driver for supplying the drive control signals to the display panel when the display panel is turned on. The method according to claim 1,
Wherein the driving voltage generator comprises:
An output controller for outputting a low level input / output power supply voltage when the reset signal is in an inactive state and outputting a high level input / output power supply voltage when the reset signal is in a setup state and an active state;
A low level voltage generating unit for generating the low level driving voltage according to a low level input / output power supply voltage supplied from the output control unit and supplying the low level driving voltage to the panel driving unit; And
And a normal level voltage generator for generating the normal driving voltage according to a high level input / output power supply voltage supplied from the output control unit and supplying the normal driving voltage to the panel driving unit. 3. The method of claim 2,
Wherein the output control unit includes a reset switch connected between an input / output power supply line for transmitting the input / output power supply voltage and an input terminal, the reset control being controlled according to a reset signal from the outside; And,
And the input node is held at a low level input / output power supply voltage when the reset signal is in an inactive state. The method of claim 3,
Wherein the low-
An inverter for inverting the level of the input / output power supply voltage applied to the input terminal; And
And a first switch connected between an output terminal and a power supply line which is controlled in accordance with an output from the inverter and transmits a power supply voltage from the outside;
And the output terminal is connected to the panel driving unit. 5. The method of claim 4,
Wherein the normal level voltage generator comprises:
resistance;
A comparator that compares a preset reference voltage with a voltage applied to one terminal of the resistor and adjusts the magnitude of the output based on the comparison result;
A constant current switch controlled according to an output from the comparator and connected between the power supply line and the other terminal of the resistor; And
And a second switch connected between one terminal of the resistor and the output terminal, the second switch being controlled according to an input / output power supply voltage applied to the input terminal. 6. The method of claim 5,
The power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level when power is input to the display device;
Wherein the reset signal is sequentially changed from the inactive state to the set state and the active state after the power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level. 6. The method of claim 5,
Wherein the channel resistance of the second switch is smaller than the channel resistance of the first switch and the channel resistance of the second switch is equal to the channel resistance of the constant current switch. The method according to claim 1,
Wherein the reset signal has a low level when the reset signal is in an inactive state and alternately has a high level and a low level in a setup state and has a high level when the reset signal is in an active state. Generating a low level drive voltage having a magnitude smaller than a normal drive voltage when the reset signal from the outside is in an inactive state and a setup state and generating a drive voltage for generating the normal drive voltage when the reset signal from the outside is in an active state part; And
Level drive voltage and a normal drive voltage from the drive voltage generation unit and is driven in accordance with the low level drive voltage to generate various drive control signals necessary for driving the display panel, And a panel driver for supplying the drive control signals to the display panel when the display panel is in a state of being turned on. 10. The method of claim 9,
Wherein the driving voltage generator comprises:
An output controller for outputting a low level input / output power supply voltage when the reset signal is in an inactive state and a setup state, and outputting a high level input / output power supply voltage when the reset signal is active;
A low level voltage generating unit for generating the low level driving voltage according to a low level input / output power supply voltage supplied from the output control unit and supplying the low level driving voltage to the panel driving unit; And
And a normal level voltage generator for generating the normal driving voltage according to a high level input / output power supply voltage supplied from the output control unit and supplying the normal driving voltage to the panel driving unit. 11. The method of claim 10,
The reset signal having a low level when the reset signal is inactive, alternating between a high level and a low level when in a setup state, and a high level when in an active state;
The output control unit starts counting each time the reset signal from the outside is maintained at a high level and outputs a reset signal of a high level when the counted value becomes 2. When the counted value is less than 2 A counter for outputting a reset signal of a low level; And a reset switch connected between the input node and the input / output power supply line for transmitting the input / output power supply voltage, the reset switch being controlled according to a reset signal provided from the counter; And,
And the input node is held at a low level input / output power supply voltage when the reset signal is in an inactive state. 12. The method of claim 11,
Wherein the low-
An inverter for inverting the level of the input / output power supply voltage applied to the input terminal; And
And a first switch connected between the output terminal and a power supply line that is controlled in accordance with an output from the inverter and transmits a power supply voltage from the outside;
And the output terminal is connected to the panel driving unit. 13. The method of claim 12,
Wherein the normal level voltage generator comprises:
resistance;
A comparator that compares a preset reference voltage with a voltage applied to one terminal of the resistor and adjusts the magnitude of the output based on the comparison result;
A constant current switch between the power supply line and the other terminal of the resistor, the constant current switch being controlled according to an output from the comparator; And
And a second switch connected between one terminal of the resistor and the output terminal, the second switch being controlled according to an input / output power supply voltage applied to the input terminal. 14. The method of claim 13,
The power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level when power is input to the display device;
Wherein the reset signal is sequentially changed from the inactive state to the set state and the active state after the power supply voltage, the input / output power supply voltage, and the reference power supply voltage rise to a high level. 14. The method of claim 13,
Wherein the channel resistance of the second switch is smaller than the channel resistance of the first switch and the channel resistance of the second switch is equal to the channel resistance of the constant current switch. 13. The method according to any one of claims 4 to 12,
And a power sensing unit for sensing a state of the power supply voltage and discharging the voltage of the input terminal to the ground when the power supply voltage drops to a low level.

Images