KR20140091396A - Array substrate of liquid crystal display and method of fabricating thereof - Google Patents

Abstract

Provided are an array substrate with a COT structure capable of improving the transmittance of a liquid crystal display device and a manufacturing method thereof. The array substrate includes a thin film transistor which is formed on a substrate, a color filter which is formed on the thin film transistor, a planarization layer which is formed on the color filter, a passivation layer which is formed on the planarization layer, a contact hole which is formed on the color filter, the planarization layer, and the passivation layer, exposes a drain electrode of the thin film transistor, and includes one wall with a step shape, and a column spacer which is formed on the passivation layer to fill the contact hole.

Description

[0001] ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY AND METHOD OF FABRICATING THEREOF [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an array substrate having a COT structure capable of improving the transmittance of a liquid crystal display device and a method of manufacturing the same.

Flat panel display devices (FPDs) are widely used in portable computers such as notebook computers and PDAs, as well as in portable telephones as well as monitors of desktop computers, in place of conventional cathode ray tube (CRT) It is an electronic information display device essential for realizing a lightweight system. Currently, flat panel display devices that are commercially available include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED). However, liquid crystal displays (LCDs) are now in the spotlight because of mass production technology, ease of driving means, realization of high image quality, and realization of a large area screen.

2. Description of the Related Art Generally, a liquid crystal display device includes a liquid crystal panel in which liquid crystal material is injected between two substrates, in which two substrates each having electrodes for generating an electric field are disposed to face each other, By controlling an optical anisotropy and a birefringence characteristic of the liquid crystal molecules by an electric field generated by the liquid crystal molecules. Therefore, the process of attaching the two substrates on which the two electrodes are formed in the process of manufacturing the liquid crystal display greatly affects the quality of the image, and the color on TFT (hereinafter referred to as COT) Structure was proposed.

1 is a view showing a structure of a conventional COT structure liquid crystal display device.

As shown in FIG. 1, a conventional COT structured liquid crystal display device comprises a lower substrate 1 and an upper substrate 2.

A gate electrode 3 made of a conductive material such as metal is formed on the lower substrate 1. A gate insulating film 4 made of silicon nitride (SiNx) or silicon oxide (SiO2) is formed on the gate electrode 3, The electrode is covered.

An active layer 5 made of amorphous silicon is formed on the gate insulating film 4 so as to overlap with the gate electrode 3. In addition, although not shown in the drawing, an ohmic contact layer (not shown) made of amorphous silicon doped with impurities may be formed on the active layer 5.

On the active layer 5, a source electrode 6 and a drain electrode 7 made of a conductive material such as a metal are formed. The source electrode 6 and the drain electrode 7 together with the gate electrode 3 form a thin film transistor (TFT).

The gate electrode 3 is connected to a gate line (not shown), the source electrode 6 is connected to a data line, and the gate line and the data line cross each other to define a pixel region.

On the entire surface of the lower substrate 1 including such a thin film transistor, a first protective film 8 for protecting the thin film transistor is formed of a silicon nitride film, a silicon oxide film or an organic insulating film.

On the first protective film 8, a color filter 9 is formed. In the color filter 9, R, G, and B colors are sequentially arranged, and one color corresponds to one pixel region. The color filter 9 should be formed so as not to remain in the portion corresponding to the drain electrode 7 exposed through the contact hole 15. [

On the color filter 9, an inorganic insulating film such as silicon oxide or silicon nitride, or a planarization film 10 made of an acrylic resin or an organic insulating film such as BCB is formed. The planarizing film 10 improves the stepped portion by the color filter 9.

The planarizing film 10 is formed so as to cover the upper surface and the side surface of the color filter 9 so that the color filter 9 does not flow out to the drain electrode 7 portion.

A large-area common electrode 11 made of a transparent conductive material is formed on the flattening film 10.

A second protective film 12 is formed on the common electrode 11 and the planarization film 10. A contact hole 15 for exposing the drain electrode 7 of the thin film transistor is formed in the second protective film 12, the planarization film 10 and the first protective film 8.

A plurality of rod-shaped pixel electrodes 13 connected to the drain electrode 7 through the contact hole 15 are formed on the second protective film 12.

The pixel electrode 13 is made of a transparent conductive material and generates a transverse electric field with the common electrode 11 formed on the planarization film 10. [

On the second protective film 12, a column spacer 14 is formed at a portion corresponding to the thin film transistor.

An upper substrate 2, which is spaced apart from the lower substrate 1 by a predetermined distance, is attached to the upper portion of the lower substrate 1 by a column spacer 14.

Further, a black matrix 21 for blocking light transmission and reflection is formed on the upper substrate 2. The black matrix 21 is formed on the upper substrate 2 so as to cover the thin film transistors of the lower substrate 1 and the contact holes 15. [

A liquid crystal is injected between the upper substrate 2 and the lower substrate 1. The liquid crystal molecules of the liquid crystal are aligned by the electric field generated when a voltage is applied to the pixel electrode 13 and the common electrode 11 Thereby displaying an image.

Since the contact hole 15 is formed to expose the drain electrode 7 of the thin film transistor, the color filter 9 is connected to the drain electrode 7 exposed through the contact hole 15 And reliability problems arise.

Therefore, in the conventional liquid crystal display device, the planarizing film 10 and the second protective film 12 should be formed so as to cover the side surface of the color filter 9, which increases the size of the contact hole 15. In addition, as the size of the contact hole 15 increases, the size of the black matrix 21 formed on the upper substrate 2 also increases, so that the transmissive region of the pixel region is reduced. This causes a decrease in transmittance of the liquid crystal display device .

An object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same that can reduce the size of a contact hole in a liquid crystal display device having a COT structure to improve transmittance.

According to an aspect of the present invention, there is provided an array substrate including a thin film transistor formed on a substrate, a color filter formed on the thin film transistor, a planarization film formed on the color filter, a passivation film formed on the planarization film, A contact hole formed in the color filter, the planarization film, and the passivation film to expose a drain electrode of the TFT, the contact hole having a wall formed in a stepped shape, and a column spacer formed on the passivation film to fill the contact hole .

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate, the method comprising: sequentially forming a thin film transistor, a color filter, a planarization film, and a passivation film on a substrate, Forming a flattening film and a contact hole having a stepped wall on the passivation film, and forming a column spacer to fill the contact hole.

The array substrate of the liquid crystal display device and the method of manufacturing the same according to the present invention can improve the transmissivity of the liquid crystal display device by increasing the aperture area of the pixel by reducing the size of the contact hole by forming the step-

Further, by forming the column spacer in the contact hole, it is possible to prevent the color filter from flowing out through the contact hole, thereby improving the reliability of the liquid crystal display device.

1 is a cross-sectional view showing the structure of a conventional COT structure liquid crystal display device.
2 is a plan view showing a partial area of an array substrate for a liquid crystal display according to an embodiment of the present invention.
3A to 3G are process sectional views of an array substrate cut along the line III-III 'in FIG.
4 is a cross-sectional view of a liquid crystal display including an array substrate according to an embodiment of the present invention.
5 is a cross-sectional view of an array substrate for a liquid crystal display according to another embodiment of the present invention.
6 is a cross-sectional view of a liquid crystal display device including an array substrate according to another embodiment of the present invention.

Hereinafter, an array substrate of a liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view showing a partial area of an array substrate for a liquid crystal display according to an embodiment of the present invention.

2, a gate wiring 103 is formed on a substrate 100 in one direction and a common wiring 104 is formed in a direction parallel to the gate wiring 103. The gate wiring 103, And a data line 105 which defines the pixel region P is formed to intersect.

A thin film transistor T is formed at a position where the gate wiring 103 and the data wiring 105 cross each other. The thin film transistor T may include a gate electrode 102, an active layer 108, a source electrode 112, and a drain electrode 114.

The gate electrode 102 may be formed to protrude from the gate wiring 103 and the source electrode 112 may be formed to protrude from the data wiring 105.

In the pixel region P, R, G, and B color filters 122 for implementing the color of the liquid crystal display device are formed. The color filter 122 may be arranged in a pixel region P of the liquid crystal display device in various forms. In this embodiment, the color filter 122 is a stripe pattern By way of example, but are not limited thereto.

A flattening film (not shown) for flattening the surface of the color filter 122 is formed on the color filter 122, and a rod-shaped common electrode 137 is formed on the flattening film, .

The common electrode 137 may extend from the common electrode wiring 136 connected to the common wiring 104 through the second contact hole 138 to the pixel region P. [

A passivation film (not shown) may be formed on the common electrode 137. The first contact hole 128 may be formed by patterning an organic insulating film formed on the passivation film, the planarizing film, the color filter 122, and the thin film transistor T. [ The first contact hole 128 exposes the drain electrode 114 of the thin film transistor T. [

The first contact hole 128 may be formed so that one wall has a stepped shape. For example, one wall of the first contact hole 128 formed in the color filter 122 may overlap with the first contact hole 128 formed in the planarization film and the passivation film. In addition, one wall of the first contact hole 128 formed in the planarization layer may be overlapped with the first contact hole 128 formed in the passivation layer. That is, one wall of the first contact hole 128 in the color filter 122, the planarization film, and the passivation film may be formed in a stepped shape having a step.

The first contact hole 128 formed in the color filter 122 is referred to as a color filter hole, the first contact hole 128 formed in the planarization film is referred to as a planarization film hole, The first contact hole 128 formed in the film is referred to as a passivation film hole.

The first contact hole 128 may be formed by one or more patterning processes, such as a color filter patterning process, a planarizing film patterning process, and a passivation film patterning process. In some cases, it may be formed by a single patterning process using a slit mask or the like.

A plurality of rod-shaped pixel electrodes 131 are formed on the passivation film so as to be spaced apart from the common electrode 137 by a predetermined distance. The pixel electrode 131 may extend from the pixel electrode wiring 130 connected to the drain electrode 114 of the thin film transistor T through the first contact hole 128 to the pixel region P. [

In the drawing, a plurality of common electrodes 137 and a plurality of pixel electrodes 131 are formed in a bending structure bent in the pixel region P. In this case, the data lines 105 are also connected to common electrodes 137 and pixels Or may be formed as a bent structure that is bent along the electrode 131.

The column spacer 150 is formed to fill the first contact hole 128. The column spacers 150 may function to maintain a gap between the array substrate 100 and an upper substrate (not shown) attached thereto.

The array substrate 100 on which the thin film transistor T, the color filter 122, the common electrode 137, the pixel electrode 131, and the column spacer 150 are formed is adhered to the upper substrate to form a liquid crystal display device have.

A black matrix (not shown) may be formed on the upper substrate to prevent transmission and reflection of light. The black matrix may be formed in a region corresponding to the thin film transistor T and the first contact hole 128 of the array substrate 100. [

Meanwhile, according to another embodiment of the present invention, the column spacers 150 of the array substrate 100 may be formed so as to replace the black matrix of the upper substrate. At this time, the column spacer 150 may be formed so as to fill the first contact hole 128 in the upper portion of the passivation film and extend to the region of the thin film transistor T on one side. The black matrix may be omitted from the upper substrate bonded to the array substrate 100. The column spacer formed to perform the black matrix function may be a black column spacer.

3A to 3G are process sectional views of an array substrate cut along the line III-III 'in FIG.

Hereinafter, a method for fabricating an array substrate according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3G. FIG.

Referring to FIG. 3A, a conductive metal is deposited on a substrate 100 and selectively patterned to form a gate wiring (103 in FIG. 2) extending in one direction of the substrate 100 and a gate electrode (102). Further, a common wiring (104 in Fig. 2) is also formed in a direction parallel to the gate wiring. The conductive metal may be selected from the group consisting of aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), moly titanium (MoTi) Cu / MoTi) may be used.

One of the inorganic insulating material groups including silicon nitride (SiNx) and silicon oxide (SiO2) is deposited on the entire surface of the substrate 100 on which the gate electrode 102 is formed to form the gate insulating film 106. [

Then, amorphous silicon (n + a-Si: H) containing pure amorphous silicon (a-Si: H) and impurities are sequentially deposited on the gate insulating film 106 and selectively patterned to form the gate electrode 102, An active layer 108 and an ohmic contact layer (not shown) are formed on the gate insulating film 106 adjacent to the gate insulating film 106.

Referring to FIG. 3B, chromium (Cr) or molybdenum (Mo) is deposited on the entire surface of the substrate 100 on which the active layer 108 and the ohmic contact layer are formed, and selectively patterned to form a source electrode (112) and the drain electrode (114) are formed.

An inorganic insulating film or an organic insulating film 116 is deposited on the entire surface of the substrate 100 on which the source and drain electrodes 114 are formed. Here, the inorganic insulating layer may be one of a group of inorganic insulating materials including silicon (SiN2) and silicon oxide (SiO2), and the organic insulating layer may be a photosensitive photo-acryl material or other photosensitive organic insulating material .

Referring to FIG. 3C, a dye for forming a color filter is applied on the organic insulating layer 116, and then color filters 122a and 122b are formed by selective patterning. Here, the color filters 122a and 122b may be formed by applying a photosensitive color resin and patterning the same.

A first contact hole, for example, a color filter hole 128a can be formed in the color filters 122a and 122b. Further, the organic insulating film 116 exposed by the color filter hole 128a is patterned to expose the drain electrode 114. Here, the patterning of the organic insulating film 116 may be formed in advance through patterning before the color filter hole 128a is formed.

Referring to FIG. 3D, a planarization film 118 is formed on the entire surface of the substrate 100 on which the color filters 122a and 122b are formed. The planarization layer 118 may be formed of an organic insulating material such as benzocyclobutene (BCB) and acrylic resin.

Then, the planarization film 118 may be patterned to form a first contact hole, for example, a planarization film hole 128b. At this time, one wall of the flattening film hole 128b is formed in a stepped shape having a step with one wall of the corresponding color filter hole 128a, so that a part of the color filter, that is, a part of the green color filter 122b is exposed . In other words, one wall of the color filter hole 128a may be formed to overlap the planarization film hole 128b.

The other wall of the planarization film hole 128b may be formed so as to overlap the inside of the color filter hole 128a so that the planarization film 118 covers the entire area of the color filter, that is, the red color filter 122a. have.

3E, a selected one of the transparent conductive metal groups including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) is deposited and patterned on the planarization layer 118 to form the common electrode 137, .

Referring to FIG. 3F, a passivation film 120 for protecting the common electrode 137 is formed on the common electrode 137. The passivation film 120 may be formed by depositing an inorganic insulating material or an organic insulating material.

Next, the passivation film 120 may be patterned to form a first contact hole, for example, a passivation film hole 128c. Likewise, one wall of the passivation film hole 128c may be formed in a stepped shape having a step between the one wall of the corresponding color filter hole 128a and one wall of the planarization film hole 128b, whereby the green color filter 122b, A part of the planarization film 118 and a part of the planarization film 118 may be exposed. In other words, one wall of the color filter hole 128a and one wall of the planarization film hole 128b may be formed to overlap with the passivation film hole 128c.

The other wall of the passivation film hole 128c is formed to overlap the inside of the planarization film hole 128b so that the passivation film 120 covers the entire area of the red color filter 122a and the planarization film 118 .

A transparent conductive metal is deposited on the passivation film 120 and patterned to form the pixel electrode 131. [ The pixel electrode 131 can be connected to the drain electrode 114 of the thin film transistor through the first contact hole 128 including the color filter hole 128a, the planarization film hole 128b and the passivation film hole 128c . In addition, the pixel electrodes 131 may be formed to be spaced apart from each other while overlapping the common electrode 137 with the passivation film 120 interposed therebetween.

Referring to FIG. 3G, a column spacer 150 may be formed to maintain a gap between the array substrate 100 and the upper substrate (not shown). The column spacer 150 may be formed by applying a carbon black coloring agent or the like to the spacer resin, coating the resin on the substrate 100, and patterning the same. At this time, the column spacer 150 may be formed to fill the first contact hole 128 in the portion where the first contact hole 128 is formed.

4 is a cross-sectional view of a liquid crystal display including an array substrate according to an embodiment of the present invention.

3G and 4, the array substrate 100 manufactured through the processes of FIGS. 3A to 3G and the upper substrate 200 on which the black matrix 210 is formed may be cemented to form a liquid crystal display device .

As described above, the array substrate 100 includes a gate electrode 102, a gate insulating film 106, an active layer 108, a source electrode 112, a drain electrode 114, an organic insulating film 116, A color filter 122a and 122b, a planarization film 118, a common electrode 137, a passivation film 120, a pixel electrode 131 and a column spacer 150. [

The pixel electrode 131 is connected to the drain electrode 114 through the first contact hole 128 formed in the array substrate 100.

The upper substrate 200 is attached to the array substrate 100 by a column spacer 150 of the array substrate 100 while maintaining a predetermined gap therebetween.

A black matrix 210 is formed on the upper substrate 200 to prevent transmission and reflection of light. The black matrix 210 may be formed to cover the first contact hole 128 and the thin film transistor of the array substrate 100.

The first contact hole 128 of the array substrate 100 includes the color filter hole 128a, the planarization film hole 128b and the passivation film hole 128c as described above. Corresponding walls of each contact hole are formed in a stepped shape.

That is, since the first contact hole 128 is formed in a step shape, the size of the color filter hole 128a formed in the color filters 122a and 122b can be reduced compared to the conventional one.

Also, as the size of the color filter hole 128a is reduced, the size of the black matrix formed on the upper substrate 200 may be reduced so as to mask the hole. This can increase the pixel area of the array substrate 100, that is, the aperture area of the pixel, and improve the transmittance of the liquid crystal display device.

The green color filter 122b exposed by the first contact hole 128 of the array substrate 100 is electrically connected to the drain electrode 114 (not shown) by the column spacer 150 formed to fill the first contact hole 128. [ And the reliability of the liquid crystal display device can be improved.

FIG. 5 is a cross-sectional view of an array substrate for a liquid crystal display according to another embodiment of the present invention, and FIG. 6 is a sectional view of a liquid crystal display including an array substrate according to another embodiment of the present invention.

The array substrate 101 according to another embodiment of the present invention shown in Figs. 5 and 6 has the same configuration except for the column spacer 151 as compared with the array substrate according to the embodiment of the present invention shown in Fig. 3G Element.

Accordingly, in the present embodiment, the remaining components except for the column spacer 151 are denoted by the same reference numerals as those described above with reference to FIGS. 3A to 3F, and a detailed description thereof will be omitted.

5 and 6, an array substrate 101 according to another embodiment of the present invention includes a gate electrode 102 formed on a substrate 101, a gate insulating film 106, an active layer 108, A pixel electrode 131 and a column spacer 123. The pixel electrode 131 and the pixel electrode 131 are electrically connected to each other through the gate electrode 112, the drain electrode 114, the organic insulating film 116, the color filters 122a and 122b, the planarization film 118, the common electrode 137, (151).

The pixel electrode 131 is connected to the drain electrode 114 through the first contact hole 128 formed in the array substrate 101.

The first contact hole 128 may include a color filter hole 128a, a planarization film hole 128b, and a passivation film hole 128c, and the corresponding walls of each hole may be formed in a stepped shape.

The column spacer 151 can be formed by applying a resin for a spacer to which a carbon black colorant or the like is added onto the substrate 101 and then patterning the same. The column spacer 151 may be formed to extend over the passivation film 120 so as to fill the first contact hole 128 and have one side corresponding to the thin film transistor of the array substrate 101.

In this way, the column spacer 151 of the array substrate 101 is filled up to the portion corresponding to the thin film transistor while filling the first contact hole 128, so that the black matrix may be omitted in the upper substrate 201.

That is, in the present embodiment, the column spacer 151 has a function of maintaining a constant gap when the array substrate 101 and the upper substrate 201 are attached together, and may be formed of a black column spacer having a function of a black matrix have.

Further, as the first contact hole 128 is formed in a step-like shape, the size of the color filter hole 128a is reduced, which can reduce the size of the column spacer 151. [ As the size of the column spacer 151 decreases, the aperture area of the pixel of the array substrate 101 increases, which can increase the transmittance of the liquid crystal display device.

As the column spacer 151 is formed to fill the first contact hole 128, the green spacer color filter 122b exposed by the first contact hole 128 is prevented from flowing out toward the drain electrode 114 The reliability of the liquid crystal display device can be improved.

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

102: gate electrode 106: gate insulating film
108: active layer 112: source electrode
114: drain electrode 116: organic insulating film
122a, 122b: color filter 128: first contact hole
118: planarization film 137: common electrode
120: passivation film 131: pixel electrode
150, 151: Column spacer

Claims (9)

A thin film transistor formed on a substrate;
A color filter formed on the thin film transistor;
A planarizing film formed on the color filter;
A passivation film formed on the planarization film;
A contact hole formed in the color filter, the planarizing film, and the passivation film to expose a drain electrode of the thin film transistor, the contact hole having a wall formed in a stepped shape; And
And a column spacer formed to fill the contact hole on the passivation film. The method according to claim 1,
And the color filter and the planarizing film are exposed by one wall of the contact hole. The semiconductor device according to claim 1,
A passivation film hole formed in the passivation film and exposing the drain electrode, the color filter, and the planarization film;
A planarization film hole formed in the planarization film and exposing the drain electrode and the color filter, the planarization film hole having a wall overlapping the passivation film hole and formed in a stepped shape; And
And a color filter hole formed in the color filter to expose the drain electrode and having a wall overlapping the passivation film hole and the planarization film hole to form a stepped shape. The method according to claim 1,
A common electrode formed on the planarization film; And
And a pixel electrode formed on the passivation film and connected to the drain electrode through the contact hole and spaced apart from the common electrode and spaced apart from each other with the passivation film interposed therebetween. The method according to claim 1,
And the column spacer is filled with the contact hole, and one side of the column spacer is extended to correspond to the thin film transistor. A step of forming a stepped contact hole in the color filter, the planarizing film and the passivation film so as to expose the drain electrode of the thin film transistor, sequentially forming a thin film transistor, a color filter, a planarization film and a passivation film on the substrate step; And
And forming a column spacer to fill the contact hole. The method according to claim 6,
Wherein forming the contact hole comprises:
A color filter hole is formed in the color filter so as to expose the drain electrode,
Forming a flattening film hole in the flattening film so as to expose the drain electrode and the color filter at a position corresponding to the color filter hole so that one wall of the color filter hole is overlapped with the flattening film hole,
A passivation film hole is formed in the passivation film so as to expose the drain electrode, the color filter, and the planarization film at positions corresponding to the color filter hole and the planarization film hole, wherein one wall of the planarization film hole overlaps with the passivation film hole Wherein the step of forming the substrate is performed in a stepwise manner. The method according to claim 6,
Before forming the column spacer,
A common electrode is formed on the planarization film,
Further comprising forming a pixel electrode on the passivation film so as to be spaced apart from each other while overlapping with the common electrode. The method according to claim 6,
Wherein the forming of the column spacer includes forming the column spacer so as to fill the contact hole and to extend over the passivation film so that one side of the column spacer corresponds to the thin film transistor.

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