KR20140072372A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same and, more specifically, to a technique capable of solving a bridge between metal wirings by forming a metal wiring in a multi-layer form. The semiconductor device, according to an embodiment of the present invention, comprises: a first metal wiring layer including a first metal wiring shape in a damascene structure for supplying a first signal to at least one of a plurality of lower electrode that performs a same function on the upper part of a semiconductor substrate; and a second metal wiring layer which supplies a second signal to the other one of the plurality of lower electrodes, and includes a second metal wiring pattern in a stack structure formed on the upper part of the first metal wiring layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a technique capable of solving a bridge between metal wirings by forming metal wirings in a multilayer form.

In recent years, there has been a growing demand for a larger capacity of a semiconductor memory device, particularly a dynamic random access memory (DRAM) device. However, the capacity increase of the DRAM device is also limited by the limitation of the chip size increase. As the chip size increases, the number of chips per wafer decreases and the productivity of the device decreases. Therefore, in recent years, efforts have been made to change the cell layout to reduce the cell area, and to accumulate more memory cells on a single wafer.

Particularly, in the case of the peripheral region, the metal wiring for supplying power to the element formed in the lower layer is connected through the contact plug, and the area of the metal wiring also has to be reduced in order to satisfy the required degree of integration and reduction.

However, the metal wiring for the power supply must be capable of flowing a sufficient amount of current, and this requires a certain area or more. In the present semiconductor device, all the metal wiring lines for supplying power to the elements formed in the lower layer are formed on the same layer. Therefore, it is difficult to form the metal wiring with a sufficient area, and if the metal wiring is provided with a sufficient area, it can not be free from the interference problem between adjacent metal wirings.

In the present invention, it is desired to form a metal wiring in a multilayer form so as to solve a bridge between metal wirings.

Further, in the present invention, a metal wiring for applying a signal to a plurality of lower electrodes performing the same function is formed in a multilayer, and a lower layer is formed by a damascene process, thereby facilitating the connection between the lower layer and the upper layer, We want to be able to make various changes to the pattern.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a damascene structure for supplying a first signal to at least one of a plurality of lower electrodes, A first metal wiring layer including a first metal wiring pattern; And a second metal interconnection layer including a second metal interconnection pattern having a stack structure formed on the first metal interconnection layer and supplying a second signal to the other of the plurality of lower electrodes.

The semiconductor device further includes a third metal interconnection layer including a third metal interconnection pattern having a stack structure for supplying a third signal to at least one of the plurality of lower electrodes and the lower electrode having a different function.

A third metal interconnection layer including a third metal interconnection pattern of a damascene structure for supplying a third signal to at least one of the plurality of lower electrodes and the lower electrode having a different function; And a fourth metal interconnection layer including a fourth metal interconnection pattern having a stack structure for supplying a fourth signal to the other one of the lower electrodes having different functions from the plurality of lower electrodes.

A first metal contact connected to at least one of the first metal wiring pattern and the plurality of lower electrodes; And a second metal contact connected to the other of the second metal wiring pattern and the plurality of lower electrodes.

In addition, the first metal contact and the second metal contact are simultaneously formed.

The first metal interconnection patterns are formed in a line shape and / or a pad shape which are spaced apart from each other.

In addition, the second metal interconnection patterns may be connected to both ends of the pad-shaped first metal interconnection pattern.

And the first metal interconnection pattern and a part of the second metal interconnection pattern are connected to each other.

The first metal interconnection layer may include: a metal barrier film formed along a step on a sidewall of the trench; And a conductive film formed on the metal barrier film in the trench.

The first metal interconnection pattern not connected to the second metal interconnection pattern is characterized in that the metal barrier film is formed under both side walls of the conductive film and an insulating film is formed on both side walls of the conductive film.

The first metal interconnection pattern connected to the second metal interconnection pattern is characterized in that the metal barrier film is formed on the entire both side walls of the conductive film.

The second metal interconnection patterns are formed in a plurality of lines spaced apart from each other.

The second metal interconnection pattern may include: a metal barrier film formed on the first metal interconnection layer; A conductive film formed on the metal barrier film; And a dielectric film formed on the conductive film.

A method of fabricating a semiconductor device according to the present invention includes forming a first metal contact and a second metal contact which are respectively connected to different lower electrodes on the semiconductor substrate and performing the same function, Forming a first metal interconnection layer including a first metal interconnection pattern of a damascene structure to be connected; And forming a second metal interconnection layer including a second metal interconnection pattern of a stack structure connected to the second metal interconnection on the first metal interconnection layer.

The forming of the first metal interconnection layer may include: forming a second interlayer insulating film on the first interlayer insulating film after depositing a first interlayer insulating film including the lower electrode; Forming a first metal contact hole and a second metal contact hole such that the lower electrode is exposed by etching the first interlayer insulating film and the second interlayer insulating film; Forming a first metal wiring pattern hole by etching the second interlayer insulating film; And filling the first metal contact hole, the second metal contact hole, and the first metal wiring pattern hole with a conductive material to form the first metal contact, the second metal contact, and the first metal wiring pattern And a control unit.

The forming of the first metal wiring pattern holes may include forming metal wiring line pattern holes having a plurality of line shapes spaced apart from each other by a predetermined distance, And forming the first metal contact hole to be connected to the first metal contact hole.

The forming of the first metal wiring pattern hole may include forming a metal wiring line pattern hole having a line shape connected to the first metal contact hole; And forming a metal wiring pad pattern hole having a pad shape spaced apart from the metal wiring line pattern hole.

The forming of the first metal contact, the second metal contact, and the first metal interconnection pattern may include forming the first metal contact hole, the second metal contact hole, 1 metal barrier film; And filling the first metal barrier film with a conductive material to form the first metal contact, the second metal contact, and the first metal wiring pattern.

The forming of the second metal interconnection layer may include forming a second metal barrier layer on the first metal interconnection layer, Forming a conductive film over the second metal barrier film; Forming a dielectric layer on the conductive layer; And etching the second metal barrier layer, the conductive layer, and the dielectric layer to form a second metal interconnection pattern spaced apart by a predetermined distance.

When the metal barrier film, the conductive film, and the dielectric film are etched, portions of the first metal barrier film on both side walls of the first metal interconnection pattern are etched together to form a recess.

Further, the method may further include forming a third interlayer insulating film on the first metal interconnection pattern, the second metal interconnection pattern, and the second interlayer insulating film.

The forming of the first metal contact, the second metal contact, and the first metal wiring pattern may include forming the first metal contact hole, the second metal contact hole, the metal wiring line pattern hole, Forming a first metal barrier film in the pad pattern hole; And filling the first metal barrier film with a conductive material to form the first metal contact, the second metal contact, and the first metal wiring pattern.

In the etching step for forming the second metal interconnection pattern, recesses are formed by etching the upper portions of both side walls of the first metal barrier film in the metal interconnection line pattern holes, and a third interlayer insulating film The method comprising the steps of:

This technique has the following effects.

First, the present invention has the effect of improving the yield of a semiconductor device by forming a metal wiring in the form of a multilayer to solve a bridge between metal wirings.

Secondly, the present invention provides a method of forming a metal wiring by a multi-layer process, wherein a metal contact connected to a lower layer and a metal contact connected to an upper layer are simultaneously formed by forming a lower layer by a damascene process, .

Thirdly, the metal wiring is formed in a multilayer structure, and the lower layer is formed by a damascene process, thereby facilitating the connection between the lower layer and the upper layer, thereby changing the metal wiring pattern in various ways.

1 is a plan view and a cross-sectional view of a semiconductor device according to a first embodiment of the present invention,
FIG. 2 is a plan view and a cross-sectional view of the semiconductor device of FIG. 1 when misalignment occurs,
3 is a plan view and a cross-sectional view of a semiconductor device according to a second embodiment of the present invention,
4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention,
5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention,
6A to 6F are sectional views showing a method of forming a semiconductor device according to the first embodiment of the present invention,
7A to 7F are cross-sectional views illustrating a method of forming a semiconductor device according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

A metal interconnection layer for supplying a signal to a plurality of lower electrodes performing the same function is divided into a plurality of layers. The first layer forms a metal wiring pattern of a damascene structure. The second layer forms a metal interconnection pattern a technique of forming a second metal interconnection pattern of a stack structure, and this technical principle is applicable to all semiconductor devices having semiconductor elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to Figs. 1 to 7F.

1 is a top view (i) and a sectional view (ii) of a semiconductor device according to a first embodiment of the present invention.

A plurality of lower electrodes 102 performing the same function are formed on a semiconductor substrate 101 and a plurality of lower electrodes 102 and a semiconductor substrate 101 are formed, A first interlayer insulating film 103 is formed on the entire surface. An etching stopper film 104 and a second interlayer insulating film 105 are sequentially stacked on the first interlayer insulating film 103 and a first metal interconnection pattern 113 of a damascene structure is formed in the second interlayer insulating film 105 Are formed at a predetermined interval. At this time, the layer including the first metal interconnection pattern 113 and the second interlayer insulating film 105 is referred to as a first metal interconnection layer, and the layer including the second metal interconnection pattern 120 and the third interlayer insulating film 123 Is referred to as a second metal wiring layer.

The second metal interconnection pattern 120 is formed by forming a second metal interconnection pattern 120 having a stack structure in a line shape at a predetermined interval on the first metal interconnection layer, The first metal interconnection pattern 113 is formed on the second interlayer insulating film 105 so that the pattern 120 is separated. Further, the second metal interconnection pattern 120 is separated by the third interlayer insulating film 123. The first metal interconnection pattern 113 is connected to the lower electrode 102 by the first metal contact 111 and the second metal interconnection pattern 120 is connected to the lower electrode 102 by the second metal contact 112. [ 102). The first metal barrier film 110 is formed on the inner sidewalls of the first metal wiring pattern 113, the first metal contact 111 and the second metal contact 112, A part of the third interlayer insulating film 123 is filled, and the first metal interconnection pattern 113 and the second metal interconnection pattern 120 are separated. On the other hand, the stacked second metal interconnection pattern 120 has a structure in which the second metal barrier film 115, the conductive film 116, and the hard mask film 117 are stacked.

The semiconductor device according to the first embodiment having the above structure has a multilayer structure even when the misalignment A is generated and the interval between the metal wirings becomes narrow as shown in Fig. 2, Bridges and the like can be prevented.

3 is a top view (i) and a sectional view (ii) of a semiconductor device according to a second embodiment of the present invention.

The semiconductor device according to the second embodiment of the present invention includes a plurality of lower electrodes 102 performing the same function on the semiconductor substrate 101 as in the first embodiment of the present invention, 1 stack structure that is connected to the first metal contact 111, the second metal contact 112, the damascene first metal interconnection patterns 113a and 114, the second metal contact 112, and the pad metal interconnection pattern 114 The second metal interconnection pattern 120 may include a second metal interconnection pattern 120 of FIG. The first metal wiring patterns 113a and 114 are composed of a damascene structure line metal wiring pattern 113a connected to the first metal contact 111 and a pad metal wiring pattern 114 of a damascene structure. At this time, the layer including the line metal interconnection pattern 113a, the pad metal interconnection pattern 114, and the second interlayer insulating film 105 is referred to as a first metal interconnection layer, and the first metal interconnection patterns 120, 118, And the layer including the third interlayer insulating film 123 is referred to as a second metal wiring layer.

However, in the first embodiment, the first metal interconnection patterns 113 are formed so as to be spaced apart from each other by a predetermined distance in the form of a line. In contrast, in the second embodiment, And a pad metal wiring pattern (114). The lower pad metal wiring pattern 114 is formed to be connected to the upper second metal wiring patterns 119, 118.

In the present invention, both ends of one pad metal interconnection pattern 114 are connected to the second metal interconnection patterns 119 and 118, respectively. However, the present invention is not limited to this embodiment, 1 Flexible changes to the metal wiring allow the designer to make various changes to the metal wiring pattern in any way desired. For example, a plurality of pad metal wiring patterns may be formed and connected to the second metal wiring, respectively.

4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 shows a first metal wiring pattern 113 for applying a first signal to one of a plurality of lower electrodes 102 performing the same function, and a second metal wiring pattern 113 formed on the first metal wiring pattern 113 and performing the same function A second metal interconnection pattern 120 formed on the second metal interconnection pattern 120 to apply a second signal to the other of the plurality of lower electrodes 102, And a third metal wiring pattern 129 for applying a third signal to the lower electrode 102 connected to the second metal wiring pattern 120 and another lower electrode 202 performing a different function. At this time, the stack structure in which the third metal interconnection pattern 129, the third metal barrier film 126, the conductive film 127, and the hard mask film 128 are sequentially stacked is formed, and the fourth interlayer insulating film 130 . The layer including the first metal interconnection pattern 113 and the second interlayer insulating film 105 is referred to as a first metal interconnection layer and the layer including the second metal interconnection pattern 120 and the third interlayer insulating film 123 is referred to as a 2 metal wiring layer, and the layer including the third metal interconnection pattern 129 and the fourth interlayer insulating film 130 is referred to as a third metal interconnection layer.

That is, in the third embodiment, the metal wiring for applying the first signal and the second signal to the plurality of lower electrodes performing the same function is divided into the first metal wiring pattern 113 and the second metal wiring pattern 120 And a third signal is applied to the lower electrode 102 connected to the first metal interconnection pattern 113 and the second metal interconnection pattern 120 and another lower electrode 202 performing a different function And the third metal wiring pattern 129 is formed as one layer. For example, if the lower electrode 102 to which the first metal interconnection pattern 113 and the second metal interconnection pattern 120 are connected is a bit line electrode, another function connected to the third metal interconnection pattern 129 is performed The lower electrode 202 may be a gate electrode.

5 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a state in which a first metal interconnection pattern 113 and a second metal interconnection pattern 120 for applying a first signal and a second signal to a plurality of lower electrodes 102 performing the same function are formed in different layers A lower electrode 102 formed on the second metal wiring pattern 120 and connected to the first metal wiring pattern 113 and the second metal wiring pattern 120, A third metal interconnection pattern 133 and a fourth metal interconnection pattern 135 for applying a third signal and a fourth signal to the first metal interconnection pattern 202 are formed on different layers.

The third metal interconnection pattern 133 is formed in a damascene structure like the first metal interconnection pattern 113 and the fourth metal interconnection pattern 135 is formed in a stacked structure like the second metal interconnection pattern 120 . The third metal interconnection patterns 133 are separated from each other by the fourth interlayer insulating film 130 and the fourth metal interconnection patterns 135 are separated from each other by the fifth interlayer insulating film 136. For example, if the lower electrode 102 to which the first metal interconnection pattern 113 and the second metal interconnection pattern 120 are connected is a bit line electrode, the third metal interconnection pattern 133 and the fourth metal interconnection pattern The lower electrode 202 performing other functions connected to the gate electrode 135 may be a gate electrode. As described above, the fourth embodiment of the present invention can prevent the bridge between the metal wires by forming the metal wires into a plurality of layers of different layers. The layer on which the first metal interconnection pattern 113 is formed is referred to as a first metal interconnection layer and the layer on which the second metal interconnection pattern 120 is formed is referred to as a second metal interconnection layer while the third metal interconnection pattern 133 is formed Layer is referred to as a third metal wiring layer, and a layer in which a fourth metal wiring pattern 135 is formed is referred to as a fourth metal wiring layer.

Hereinafter, a method for forming a semiconductor device according to a first embodiment of the present invention will be described in detail with reference to FIGS. 6A to 6F. Here, (i) is a plan view of each step and (ii) is a cross-sectional view.

Referring to FIGS. 6A and 6B, a first interlayer insulating film 103 including a plurality of lower electrodes 102 separated on a semiconductor substrate 101 is formed on a first interlayer insulating film 103, The second interlayer insulating film 105 is deposited on the first etch stopping film 104 after the first interlayer insulating film 104 is deposited. Thereafter, the second interlayer insulating film 105, the first etch stopping film 104, and the first interlayer insulating film 103 are etched to form the first metal contact hole 106 and the second metal contact hole 106 so that the upper portion of the lower electrode 102 is exposed. Metal contact holes 107 are simultaneously formed. At this time, the lower electrode 102 may be a bit line electrode or a gate electrode.

Next, referring to FIGS. 6 (i) and 6 (ii), a photoresist (not shown) for forming the first metal interconnection pattern 113 is formed and then the second interlayer insulating film 105 is etched to form a damascene pattern Thereby forming a hole 108. At this time, one of the damascene pattern holes 108 is connected to the first metal contact hole 106. Thereafter, the photoresist (not shown) is removed. At this time, the damascene pattern holes 108 are formed in a line shape as shown in (i), and are formed with a predetermined spacing.

Referring to FIGS. 6 (i) and 6 (ii), the first metal contact hole 106, the second metal contact hole 107, the damascene pattern hole 108, and the second interlayer insulating film 105, The first metal barrier film 110 is deposited along the step on the front surface.

Thereafter, a conductive material is deposited on the entire upper surface of the first metal barrier film 110 to fill the first and second metal contact holes 106 and 107 and the damascene pattern hole 108 with a conductive material. Thereafter, planarization is performed so that the upper portion of the second interlayer insulating film 105 is exposed, and the first metal barrier film 110 is electrically connected to the first and second metal contact holes 106 and 107, the damascene pattern holes 108 ).

Thus, the first metal contact 111 and the second metal contact 112 and the first metal wiring pattern 113 are formed. A plurality of line metal interconnection patterns of the first metal interconnection pattern 113 are formed with a predetermined spacing. At this time, the first metal interconnection pattern 113 is formed to be connected to the first metal contact 111, and the second metal contact 112 is connected to the second metal interconnection pattern (not shown).

6D, the second metal barrier film 115, the conductive film 116, and the second metal barrier film 115 are formed on the first metal interconnection pattern 113 and the second interlayer insulating film 105, And a hard mask film 117 are sequentially deposited and deposited. The second barrier metal layer 115 may be formed of TiN or tantalum sodium and the conductive layer 116 may be formed of a metal such as copper (Cu), aluminum (Al), tungsten (W), or the like. And the hard mask film 117 may be formed of a nitride film or the like.

6E, a photoresist pattern (not shown) is formed on the hard mask film 117 and the hard mask film 117 (not shown) is formed using the photoresist pattern (not shown) as a mask, ), The conductive film 116, and the second metal barrier film 115 are sequentially etched to form the second metal wiring pattern 120. The second metal interconnection patterns 120 are formed in a line shape spaced apart from each other by a predetermined distance and are formed at positions not connected to the first metal interconnection patterns 113 at the bottom. During the etching process for forming the second metal interconnection pattern 120, the first metal barrier film 110 on both side walls of the first metal interconnection pattern 113 is partially etched to form the recess 121 . Accordingly, the lower first metal wiring pattern 113 and the upper second metal wiring pattern 120 are separated from each other by the recess 121. Then, referring to (i) and (ii) of FIG. 6F, a third interlayer insulating film 123 is deposited on the second metal interconnection pattern 120 and the second interlayer insulating film 105.

Hereinafter, a method of forming a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to FIGS. 7A to 7F. Here, (i) is a plan view of each step and (ii) is a cross-sectional view.

Referring to FIGS. 7A and 7B, a first interlayer insulating film 103 including a plurality of lower electrodes 102 separated from the upper surface of a semiconductor substrate 101, The second interlayer insulating film 105 is deposited on the first etch stopping film 104 after the first interlayer insulating film 104 is deposited. Thereafter, the second interlayer insulating film 105, the first etch stopping film 104, and the first interlayer insulating film 103 are etched to form the first metal contact hole 106 and the second metal contact hole 106 so that the upper portion of the lower electrode 102 is exposed. Metal contact holes 107 are simultaneously formed. At this time, the lower electrode 102 may be a bit line electrode or a gate electrode.

7B, a photoresist (not shown) for forming the first metal interconnection layer is formed, and then the second interlayer insulating film 105 is etched to form the damascene pattern holes 108, 109 are formed. Thereafter, the photoresist (not shown) is removed. At this time, the damascene pattern holes 108 and 109 include a line pattern hole 108 and a pad pattern hole 109 in the form of a pad, as shown in (i).

Next, referring to (i) and (ii) of FIG. 7C, the first metal contact hole 106, the second metal contact hole 107, the line pattern hole 108, the inside of the pad pattern hole 109, The first metal barrier layer 110 is deposited on the entire surface of the two-layer insulating film 105 along the step. Thereafter, a conductive material is deposited on the first metal barrier layer 110 to form a conductive material in the first and second metal contact holes 106 and 107, the line pattern hole 108, and the pad pattern hole 109 Landfill. The first metal barrier film 110 is then patterned to form first and second metal contact holes 106 and 107, a line pattern hole 108, And is formed only in the pad pattern hole 109.

The first metal contact 111 and the second metal contact 112 and the first metal wiring pattern (the line metal wiring pattern 113a and the pad metal wiring pattern 114) are formed. At this time, the line metal interconnection pattern 113a is formed to be connected to the first metal contact 111, and the second metal contact 112 is connected to the second metal interconnection pattern (not shown) to be formed subsequently.

7D, a second metal barrier film 115 is formed on the line metal interconnection pattern 113a, the pad metal interconnection pattern 114, and the second interlayer insulating film 105, A conductive film 116, and a hard mask film 117 are sequentially deposited and deposited. The second barrier metal layer 115 may be formed of TiN or tantalum sodium and the conductive layer 116 may be formed of a metal such as copper (Cu), aluminum (Al), tungsten (W), or the like. And the hard mask film 117 may be formed of a nitride film or the like.

7E, a photoresist pattern (not shown) is formed on the hard mask film 117 and a hard mask film 117 (not shown) is formed using the photoresist pattern (not shown) as a mask, The conductive film 116 and the second metal barrier film 115 are sequentially etched to form the second metal interconnection patterns 120, 119, and 118. The second metal interconnection patterns 120, 119 and 118 are formed in a line shape spaced apart from each other by a predetermined distance and the second metal interconnection patterns 119 and 118 are formed at a position connected to the lower pad metal interconnection pattern 114 In particular, the second metal wiring pattern 118 is formed to be connected to the second metal contact 112. At this time, the first metal barrier film 110 on both side walls of the lower line metal interconnection pattern 113a is partially etched to form the recess 121 in the etching process for forming the second metal interconnection patterns 120, 119, . Therefore, the lower line metal interconnection pattern 113a and the upper second metal interconnection pattern 120 are separated by the recess 121. [

Next, referring to (i) and (ii) of FIG. 7F, a third interlayer insulating film 123 is deposited on the second metal interconnection patterns 120, 119, and 118 and the second interlayer insulating film 105. A metal contact hole (not shown) is formed by etching the third interlayer insulating film 123 to be connected to a part of the second metal interconnection pattern 119 and a part of the pad metal interconnection pattern 113a, (Not shown) to perform planarization to form a third metal contact 124. At this time, the metal contact 124 may be used for connection to an external device or an element of another layer.

As described above, the present invention can prevent a bridge between metal wirings by forming a metal wiring for applying a signal to a lower electrode having the same function into at least one layer.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas falling within the scope of the same shall be construed as falling within the scope of the present invention.

101: semiconductor substrate 102: lower electrode
103: first interlayer insulating film 104: etch stop film
105: second interlayer insulating film 106: first metal contact hole
107: second metal contact hole 108: line pattern hole
109: pad pattern hole 110: first metal barrier film
111: first metal contact 112: second metal contact
113: first metal wiring pattern 115: second metal barrier film
113a: line metal wiring pattern 114: pad metal wiring pattern
116: conductive film 129, 133: second metal wiring pattern
118, 119, 120: second metal wiring layer 117: hard mask film
121: recess 123: third interlayer insulating film
124: third metal contact 133: third metal wiring pattern

Claims (23)

A first metal interconnection layer including a first metal interconnection pattern of a damascene structure for supplying a first signal to at least one of a plurality of lower electrodes performing the same function on a semiconductor substrate; And
And a second metal interconnection layer including a second metal interconnection pattern of a stack structure formed on the first metal interconnection layer, supplying a second signal to the other of the plurality of lower electrodes,
≪ / RTI > The method according to claim 1,
A third metal interconnection layer including a third metal interconnection pattern having a stack structure for supplying a third signal to at least one of the plurality of lower electrodes and the lower electrode having a different function,
The semiconductor device further comprising: The method according to claim 1,
A third metal interconnection layer including a third metal interconnection pattern of a damascene structure for supplying a third signal to at least one of the plurality of lower electrodes and the lower electrode having a different function; And
A fourth metal interconnection layer including a fourth metal interconnection pattern having a stack structure for supplying a fourth signal to the other one of the plurality of lower electrodes and the lower electrode having a different function,
And a semiconductor layer formed on the semiconductor substrate. The method according to claim 1,
A first metal contact connected to at least one of the first metal wiring pattern and the plurality of lower electrodes; And
And a second metal contact connected to the other of the plurality of lower electrodes,
And a semiconductor layer formed on the semiconductor substrate. The method of claim 4,
Wherein the first metal contact and the second metal contact are simultaneously formed. The method according to claim 1,
Wherein the first metal interconnection patterns are formed in a line shape and / or a pad shape which are spaced apart from each other. The method of claim 6,
And the second metal interconnection patterns are connected to both ends of the pad-shaped first metal interconnection patterns, respectively. The method according to claim 1,
And a part of the first metal interconnection pattern and the second metal interconnection pattern are connected to each other. The method of claim 8,
Wherein the first metal interconnection layer comprises:
A metal barrier film formed along the step on the side wall of the trench; And
The conductive film formed on the metal barrier film in the trench
And a semiconductor layer formed on the semiconductor substrate. The method of claim 9,
The first metal interconnection pattern not connected to the second metal interconnection pattern,
Wherein the metal barrier film is formed under both side walls of the conductive film, and an insulating film is formed on both side walls of the conductive film. The method of claim 9,
The first metal interconnection pattern connected to the second metal interconnection pattern,
Wherein the metal barrier film is formed on all the side walls of the conductive film. The method according to claim 1,
Wherein the second metal interconnection patterns are formed in a plurality of lines separated from each other. The method according to claim 1,
Wherein the second metal wiring pattern comprises:
A metal barrier film formed on the first metal wiring layer;
A conductive film formed on the metal barrier film; And
The dielectric film formed on the conductive film
≪ / RTI > Forming a first metal contact and a second metal contact which are respectively connected to different lower electrodes which perform the same function on the semiconductor substrate and which are connected to the first metal contact by a damascene process, Forming a first metal interconnection layer including a pattern; And
Forming a second metal wiring layer and a second metal wire pattern in the stack structure is connected to said second metal contact on the part of the first metal interconnection layer
Wherein the semiconductor device is a semiconductor device. 15. The method of claim 14,
Wherein forming the first metal interconnection layer comprises:
Depositing a first interlayer insulating film including the lower electrode, and forming a second interlayer insulating film on the first interlayer insulating film;
Forming a first metal contact hole and a second metal contact hole such that the lower electrode is exposed by etching the first interlayer insulating film and the second interlayer insulating film;
Forming a first metal wiring pattern hole by etching the second interlayer insulating film; And
Forming a first metal contact, a second metal contact, and a first metal wiring pattern by embedding a conductive material in the first metal contact hole, the second metal contact hole, and the first metal wiring pattern hole,
Wherein the semiconductor device is a semiconductor device. 16. The method of claim 15,
The forming of the first metal wiring pattern hole may include:
Forming a metal wiring line pattern hole having a plurality of line shapes spaced apart from each other by a predetermined distance and forming at least one of the metal wiring line pattern holes having a plurality of line shapes to be connected to the first metal contact hole Wherein the semiconductor device is a semiconductor device. 16. The method of claim 15,
The forming of the first metal wiring pattern hole may include:
Forming a metal wiring line pattern hole having a line shape connected to the first metal contact hole; And
Forming a metal wiring pad pattern hole having a pad shape apart from the metal wiring line pattern hole;
Wherein the semiconductor device is a semiconductor device. 16. The method of claim 15,
Wherein forming the first metal contact, the second metal contact, and the first metal interconnection pattern comprises:
Forming a first metal barrier film in the first metal contact hole, the second metal contact hole, and the first metal wiring pattern hole; And
Filling the first metal barrier film with a conductive material to form the first metal contact, the second metal contact, and the first metal wiring pattern
Wherein the semiconductor device is a semiconductor device. 19. The method of claim 18,
Wherein forming the second metal interconnection layer comprises:
Forming a second metal barrier layer on the first metal wiring layer;
Forming a conductive film over the second metal barrier film;
Forming a dielectric layer on the conductive layer; And
Etching the second metal barrier layer, the conductive layer, and the dielectric layer to form a second metal interconnection pattern spaced apart by a predetermined distance;
Wherein the semiconductor device is a semiconductor device. The method of claim 19,
Wherein a recess is formed by etching portions of the first metal barrier film on both side walls of the first metal interconnection pattern when the metal barrier film, the conductive film, and the dielectric film are etched. . The method of claim 20,
Further comprising the step of forming a third interlayer insulating film on the first metal interconnection pattern, the second metal interconnection pattern, and the second interlayer insulating film. 18. The method of claim 17,
Wherein forming the first metal contact, the second metal contact, and the first metal interconnection pattern comprises:
Forming a first metal barrier film in the first metal contact hole, the second metal contact hole, the metal wiring line pattern hole, and the metal wiring pad pattern hole; And
Filling the first metal barrier film with a conductive material to form the first metal contact, the second metal contact, and the first metal wiring pattern
Wherein the semiconductor device is a semiconductor device. 23. The method of claim 22,
In the etching process for forming the second metal wiring pattern,
Forming a recess by etching the upper portions of both side walls of the first metal barrier film in the metal wiring line pattern hole, and forming a third interlayer insulating film in the recess.

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