KR20140052450A - Thin film transistor substrate having oxide semiconductor and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate containing an oxide semiconductor and a method for manufacturing the same. The thin film transistor substrate containing the oxide semiconductor according to the present invention comprises: a substrate; a gate wiring and a data wiring which are arranged orthogonally to each other on the substrate while interposing an insulating film therebetween to define a pixel region; a thin film transistor including a gate electrode branched from the gate wiring, a channel layer overlapping with the gate electrode on the gate insulating film; a source electrode branched from the data wiring; and a drain electrode facing the source electrode; an etch stopper layer which covers the channel layer region except regions contacting with the source electrode and the drain electrode, and the thin film transistor region except the pixel region between the gate electrode and the source electrode; and a protective film for covering the thin film transistor.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor substrate including an oxide semiconductor, and a manufacturing method thereof. [0002]

The present invention relates to a thin film transistor (TFT) substrate for a flat panel display including an oxide semiconductor and a method of manufacturing the same. More particularly, the present invention relates to a method of manufacturing a semiconductor device, which comprises forming an etch stopper layer only in a necessary portion except for a pixel electrode region, protecting the oxide semiconductor channel layer from an etchant in a subsequent process and minimizing a parasitic capacitance between the gate electrode and the source electrode And a method of manufacturing the same.

The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device which are actively driven, the thin film transistor substrate includes thin film transistors arranged in pixel regions arranged in a matrix manner. A liquid crystal display displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device is divided into a vertical electric field type and a horizontal electric field type in accordance with the direction of the electric field driving the liquid crystal.

The vertical electric field type liquid crystal display device drives TN (Twisted Nematic) mode liquid crystal by a vertical electric field formed between a pixel electrode and a common electrode arranged opposite to upper and lower substrates. Such a vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is narrow to about 90 degrees.

A horizontal electric field type liquid crystal display device forms a horizontal electric field between a pixel electrode and a common electrode arranged in parallel to a lower substrate to drive an in-plane switching (IPS) mode liquid crystal. Such an IPS mode liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance. More specifically, in the IPS mode liquid crystal display device, in order to form an in-plane field (a horizontal electric field), the gap between the common electrode and the pixel electrode is formed wider than the gap (cell gap) between the upper substrate and the lower substrate And the common electrode and the pixel electrode are formed in a band shape having a constant width to obtain an electric field of an appropriate intensity. An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the liquid crystal above the pixel electrode and the common electrode having a constant width. That is, the liquid crystal molecules placed on the pixel electrode and the common electrode are not driven and maintain the initial alignment state. The liquid crystal that maintains the initial state can not transmit light, which causes a decrease in aperture ratio and transmittance.

A fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed to overcome the disadvantage of the IPS mode liquid crystal display device. The FFS type liquid crystal display device has a common electrode and a pixel electrode in each pixel region with an insulating film interposed therebetween. The common electrode and the pixel electrode overlap each other in the vertical direction, or even if they do not overlap, A fringe field of a parabolic shape is formed on the common electrode and the pixel electrode. The liquid crystal molecules interposed between the upper and lower substrates are operated by the fringe field, so that the aperture ratio and the transmittance can be improved.

In the fringe field type liquid crystal display device, since the common electrode and the pixel electrode overlap or are disposed at a considerably close position, an auxiliary capacitance is formed between the common electrode and the pixel electrode. Therefore, unlike the IPS mode, there is an advantage that the auxiliary capacitance need not be formed. However, when the large-screen display device is implemented by the fringe field method, the size of the pixel increases and thus the size of the storage capacitor increases. As the size of the thin film transistor increases, it is difficult to realize high density or high resolution.

In order to solve such a problem, a thin film transistor substrate having a metal oxide semiconductor layer having a high capacity driving characteristic without increasing the size of the thin film transistor has been applied. 1 is a plan view showing a thin film transistor substrate constituting a flat panel display device having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device. 2 is a cross-sectional view of the thin film transistor substrate for a flat panel display shown in FIG. 1, taken along the cutting line I-I '.

The thin film transistor substrate shown in FIGS. 1 and 2 includes a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB and a thin film transistor T). A pixel region is defined by the intersection structure of the gate line GL and the data line DL. The pixel region includes a pixel electrode PXL and a common electrode COM formed with a protective film PAS therebetween so as to form a fringe field. The pixel electrode PXL has a substantially rectangular shape corresponding to the pixel region, and the common electrode COM is formed into a plurality of parallel strips.

The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode PXL. To this end, the thin film transistor T opposes the source electrode S and the source electrode S branched from the gate electrode G branched from the gate line GL, the data line DL, and the pixel electrode PXL, And a semiconductor layer A which overlaps the gate electrode G on the gate insulating film GI and forms a channel between the source electrode S and the drain electrode D. The semiconductor layer A and the drain electrode D may further include an ohmic contact layer for ohmic contact between the semiconductor layer A and the source electrode S and between the semiconductor layer A and the drain electrode D. [

Particularly, when the semiconductor layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a high charging capacity due to high charge mobility characteristics. However, it is preferable that the oxide semiconductor material further includes an etch stopper layer (ES) for protecting from the etching solution on the upper surface in order to secure the stability of the device. Specifically, in the process of separating the source electrode S and the drain electrode D by the etching process, an etch stopper layer ES is formed to protect the semiconductor layer A from the etchant flowing through the source electrode S and the drain electrode D .

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad terminal GPT through the gate pad contact hole GPH passing through the gate insulating film GI and the protective film PAS. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the protective film PAS.

1, a TAB in which a gate driver GIC is mounted on one side of the left side of the display panel DP is attached to a gate pad terminal GPT, and a gate driver GIC applies a signal . A TAB on which the data driver DIC is mounted on one side of the upper side of the display panel DP is attached to the data pad terminal DPT and the data driver DIC supplies the video data signal to the data line DL.

The pixel electrode PXL is connected to the drain electrode D on the gate insulating film GI. On the other hand, the common electrode COM is formed so as to overlap the pixel electrode PXL with the protective film PAS covering the pixel electrode PXL interposed therebetween. An electric field is formed between the pixel electrode (PXL) and the common electrode (COM), and the liquid crystal molecules arranged in the horizontal direction between the TFT substrate and the color filter substrate rotate due to dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

In the thin film transistor substrate including the metal oxide semiconductor as described above, it is desirable to provide an etch stopper layer (ES), but other problems may arise accordingly. For example, after patterning the etch stopper layer ES, a dry etching process is further used to remove residues. In the substrate SUB, a pattern defect due to dry etching occurs in the contact hole area outside the display area . Such a defective pattern may cause defects in the laminated and patterned thin films in the subsequent process.

An object of the present invention is to provide a thin film transistor substrate for a display device having a structure in which an oxide semiconductor channel layer is not damaged in a subsequent etching process in a thin film transistor substrate including an oxide semiconductor . It is another object of the present invention to provide a structure and a method of manufacturing the same in which the etch stopper layer does not adversely affect the thin films formed in a subsequent process in a thin film transistor substrate having a structure in which the etch stopper layer protects the oxide semiconductor channel layer There is.

In order to accomplish the object of the present invention, a thin film transistor substrate including an oxide semiconductor layer according to the present invention includes a substrate; A gate wiring and a data wiring arranged on the substrate so as to be orthogonal to each other with a gate insulating film therebetween to define a pixel region; A thin film transistor including a gate electrode branched from the gate wiring, a channel layer overlapping the gate electrode on the gate insulating film, a source electrode branched in the data line, and a drain electrode opposing the source electrode; An etch stopper layer covering the channel layer region except regions contacting the source electrode and the drain electrode and the thin film transistor region excluding the pixel region between the gate electrode and the source electrode; And a protective film covering the thin film transistor.

A gate pad formed on one end of the gate wiring; And a data pad formed at one end of the data line, wherein the etch stopper layer is formed excluding the gate pad region.

A common electrode formed on the passivation layer to cover the pixel region in contact with the drain electrode; An insulating film covering the common electrode; And a pixel electrode formed on the insulating layer in the form of a plurality of line segments overlapping the common electrode.

And a planarizing film formed on the entire surface of the substrate between the protective film and the common electrode.

And the common electrode has a shape covering the pixel region and the data line arranged in the horizontal direction.

And the common electrode has a shape that covers the upper surface of the planarization film except the region where the thin film transistor is formed.

A thin film transistor substrate including an oxide semiconductor according to the present invention includes an etch stopper layer having a structure covering an entire substrate on an oxide semiconductor channel layer, and source-drain electrodes are formed on the oxide semiconductor channel layer As shown in Fig. The etch stopper layer according to the present invention can secure the performance of the channel layer by protecting the oxide semiconductor channel layer from being attacked by the etching material used in the subsequent process including the step of forming the source and drain electrodes . The etch stopper layer can be utilized as a function of the pattern protective layer to prevent pattern defects occurring in the thin film formation and patterning steps performed after the formation of the etch stopper layer. The thin film transistor substrate according to the present invention has a structure in which an etch stopper layer is interposed between a source electrode and a gate electrode together with a gate insulating film. Since the source electrode and the gate electrode are separated and insulated from each other by the two insulating material layers, generation of parasitic capacitance between the source and gate electrodes is reduced, and the load of each wiring is reduced.

1 is a plan view showing a thin film transistor substrate constituting a flat panel display panel having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device.
2 is a cross-sectional view taken along the cutting line I-I 'in the thin film transistor substrate of the flat panel display shown in FIG.
FIG. 3 is a plan view showing a thin film transistor substrate including a metal oxide semiconductor included in a fringe field type liquid crystal display according to a first embodiment of the present invention. FIG.
FIG. 4 is a cross-sectional view taken along line II-II 'of FIG. 3, showing a thin film transistor substrate according to a first embodiment of the present invention. FIG.
5 is a plan view showing a thin film transistor substrate including a metal oxide semiconductor included in a fringe field type liquid crystal display according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view taken along line III-III 'of FIG. 5, showing a thin film transistor substrate according to a second embodiment of the present invention. FIG.
7A to 7H are cross-sectional views taken along line III-III 'of FIG. 5, illustrating a process for fabricating a thin film transistor substrate including a metal oxide semiconductor of a fringe field method according to a second embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured.

Hereinafter, a first embodiment of the present invention will be described with reference to Figs. 3 and 4. Fig. 3 is a plan view of a thin film transistor substrate including a metal oxide semiconductor included in a fringe field type liquid crystal display according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view of the thin film transistor substrate according to the first embodiment of the present invention, taken along the cutting line II-II 'in FIG.

3 and 4, a thin film transistor substrate according to the present invention includes a gate line GL and a data line DL (hereinafter referred to as DL) crossing a gate insulating film GI and an etch stopper layer ES on a lower substrate SUB, ), And a thin film transistor T formed at each of the intersections. Further, the thin film transistor substrate defines a pixel region with an intersection structure of a gate line GL and a data line DL. The pixel region includes a pixel electrode PXL and a common electrode COM formed so as to overlap each other with a protective film PAS therebetween so as to form a fringe field. Here, the pixel electrode PXL has a substantially rectangular shape corresponding to the pixel region, and the common electrode COM is formed into a plurality of parallel strips.

The common electrode COM branches off from the common line CL arranged in parallel with the gate line GL. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode PXL. To this end, the thin film transistor T opposes the source electrode S and the source electrode S branched from the gate electrode G branched from the gate line GL, the data line DL, and the pixel electrode PXL, And an oxide semiconductor channel layer A which overlaps the gate electrode G on the gate insulating film GI and forms a channel between the source electrode S and the drain electrode D do.

The oxide semiconductor material preferably further includes an etch stopper layer (ES) for protecting the upper surface from an etchant to ensure stability of the device. More specifically, it is preferable to form the etch stopper layer ES so as to protect the oxide semiconductor channel layer A from the etchant flowing through the separated portion between the source electrode S and the drain electrode D. In addition, the shape of the oxide semiconductor channel layer A may have a shape exposed to the outside of the outline of the source electrode S and the drain electrode D. The exposed portion may be damaged by the attack by the etching material patterning the source electrode S and the drain electrode D. In order to prevent this, the etch stopper layer ES is preferably formed so as to cover the entire surface of the substrate SUB on which the oxide semiconductor channel layer A is formed.

The source electrode S is formed on the upper surface of one side of the semiconductor channel layer A through a source region contact hole SAH exposing a part of one side surface of the oxide semiconductor channel layer A formed on the etch stopper layer ES, / RTI > One side of the drain electrode D is exposed to the other side of the oxide semiconductor channel layer A through a drain region contact hole DAH exposing a part of the other side surface of the oxide semiconductor channel layer A formed in the etch stopper layer ES. And is in contact with the upper surface of the lateral side. And the other side of the drain electrode D has a structure in contact with the etched side face and the upper face of one side of the pixel electrode PXL.

At one end of the gate wiring GL, a gate pad GP for receiving a gate signal from the outside is formed. The gate pad GP is in contact with the gate pad terminal GPT through the gate pad contact hole GPH passing through the gate insulating film GI, the etch stopper layer ES and the protective film PAS. On one side of the data line DL, a data pad DP for receiving a pixel signal from the outside is formed. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the protective film PAS.

The pixel electrode PXL is formed on the etch stopper layer ES covering the oxide semiconductor channel layer A. [ The pixel electrode PXL is preferably formed of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The drain electrode D that contacts the upper surface of the other side of the oxide semiconductor channel layer A has a structure in which the other side thereof is in direct contact with the etched side surface and the upper surface of the one side of the pixel electrode PXL.

On the other hand, the common electrode COM is formed so as to overlap the pixel electrode PXL with the protective film PAS covering the pixel electrode PXL interposed therebetween. An electric field is formed between the pixel electrode PXL and the common electrode COM so that the liquid crystal molecules arranged in the horizontal direction between the TFT substrate and the color filter substrate rotate due to the dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

Particularly, when the semiconductor channel layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a high charging capacity due to its high charge mobility. Furthermore, in the case of the fringe field method, the region where the pixel electrode PXL overlaps with the common electrode COM forms the storage capacitor, and as the size of the pixel increases, the storage capacitor increases in proportion thereto. Therefore, the fringe field type thin film transistor substrate including the oxide semiconductor according to the present invention has an advantage of providing a high-definition flat panel display device having a large surface.

In the first embodiment of the present invention, the etch stopper layer (ES) has a structure for protecting the oxide semiconductor channel layer (A) having a high charge mobility from the attack of an etching material used in a subsequent process. Therefore, the oxide semiconductor channel layer (A) is completely protected, so that stable charge mobility can be secured.

The etch stopper layer ES is formed so as to cover the entire area of the substrate SUB on which the oxide semiconductor channel layer A is formed so that a gate insulating film is formed between the gate electrode G and the source- GI) and an etch stopper layer (ES) are stacked. Therefore, the parasitic capacitance between the gate electrode G and the source-drain electrodes S, D can be minimized. As a result, the wiring load on the gate wiring GL and the data wiring DL is reduced, ensuring good image quality.

As described above, the structure in which the etch stopper layer ES is formed over the entire surface of the substrate SUB and only the necessary portion is formed as a contact hole is exposed, which has an advantage of solving the problem caused by the conventional structure. However, it may cause other problems. For example, in the gate pad GP region, a contact hole for connecting the gate pad GP and the gate pad terminal GPT must be formed. This is because the passivation layer PAS and the etch stopper layer ES are etched . Therefore, more etching time is needed. In this case, an etching time for etching the passivation film PAS is excessively exposed in the contact hole portion for connecting the data pad DP and the data pad terminal DPT. This can damage the data pad (DP).

Another problem is that since the etch stopper layer ES is further included in the pixel region, that is, the region where the pixel electrode PXL and the common electrode COM are formed, there is a problem that the light amount of the backlight is reduced. This may cause a drawback that the luminance of the display device is lowered or more power is used to obtain the same luminance.

In addition, in order to realize a high aperture ratio and low power, a flattening film is formed on a substrate on which a thin film transistor is completed, a common electrode is first formed on a planarizing film, and an insulating film and a pixel electrode are stacked thereon. It may be undesirable that the etch stopper layer ES is added to the pixel region because the amount of light of the backlight is further reduced.

To further complicate the drawbacks that may occur in the first embodiment, a second embodiment of the present invention will be described with reference to Figs. 5 and 6. Fig. 5 is a plan view showing a thin film transistor substrate including a metal oxide semiconductor included in a fringe field type liquid crystal display according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view of a thin film transistor substrate according to a second embodiment of the present invention, taken along the cutting line III-III 'in FIG.

The thin film transistor substrate according to the second embodiment has substantially the same structure as the thin film transistor according to the first embodiment. The difference is that the etch stopper layer ES is not formed over the entire substrate SUB on which the semiconductor channel layer A is formed but is formed at a position corresponding to a region occupied by the thin film transistor including the source- As shown in Fig. In other respects, the etch stopper layer ES remains in the portion where the thin film transistor T including the source-drain metal layer and the gate metal layer is formed, while the etch stopper layer ES remains in the portion corresponding to the pixel region .

In comparison with the thin film transistor substrate according to the first embodiment, in the thin film transistor substrate according to the second embodiment, the etch stopper layer ES is formed only in the portion where the thin film transistor T is formed. The source region contact hole SAH and the drain region contact hole DAH formed in the etch stopper layer ES are formed on the semiconductor layer A for the purpose of the etch stopper layer ES itself, The source electrode S and the semiconductor layer A and the drain electrode D and the semiconductor layer A are in contact with each other. In addition, an etch stopper layer ES is interposed between the gate electrode G and the source-drain electrodes S, D. So that the semiconductor layer A can be protected from the etching solution forming the source-drain electrodes S and D. In addition, the parasitic capacitance that may occur between the source electrode S and the gate electrode G can be remarkably reduced.

However, there is no etch stopper layer ES in the pixel region, the gate pad GP, and the data pad (DP) region. Therefore, it is possible to prevent the light amount of the backlight passing through the pixel region from being reduced by the etch stopper layer ES. Since the etch stopper layer ES is not required to be etched in the process of forming the gate pad contact hole GPH and the data pad contact hole DPH for exposing the gate pad GP and the data pad DP, It is not necessary to secure a long time and etching failure due to the etch stopper layer ES can be prevented.

Hereinafter, a process for fabricating a fringe field type thin film transistor substrate including an oxide semiconductor according to a second embodiment of the present invention will be described. 7A to 7H are cross-sectional views taken along line III-III 'of FIG. 5, illustrating a process for fabricating a thin film transistor substrate including a metal oxide semiconductor of a fringe field method according to a second embodiment of the present invention.

A gate metal is deposited on the transparent lower substrate (SUB). The gate metal is patterned in a first mask process to form gate elements. The gate element includes a gate wiring GL, a gate electrode G branching from the gate wiring GL and a gate pad GP formed at one end of the gate wiring GL. (Fig. 7A)

The gate insulating film GI is entirely coated on the substrate SUB on which the gate elements are formed. The gate insulating film GI preferably includes silicon oxide (SiO2). Further, although not shown in detail in the drawing, the gate insulating film GI may have a structure in which silicon nitride (SiNx) and silicon oxide (SiO2) are sequentially stacked. The oxide semiconductor material is then deposited. In the second mask process, the semiconductor material is patterned to form the semiconductor layer (A). (Fig. 7B)

An insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is applied over the entire surface of the substrate on which the semiconductor layer (A) is formed. An insulating material is patterned by a third mask process to form an etch stopper layer (ES). The etch stopper layer ES is formed so as to have a shape covering all of the semiconductor layer (A). Particularly, it is preferable to have a shape covering the regions of the source electrode S and the drain electrode D to be formed later. On the other hand, it is preferable that no etch stopper layer ES remains in the pixel region where the pixel electrode PXL and the common electrode COM to be formed later are formed. It is also preferable that the etch stopper layer ES is not left in the region where the gate pad GP and the data pad DP are formed. At the same time, a source region contact hole (SAH) for opening the source region of the semiconductor layer (A) and a drain region contact hole (DAH) for opening the drain region are formed. (Fig. 7C)

A source-drain metal is deposited on a substrate SUB on which a semiconductor layer A and an etch stopper layer ES are formed. In a fourth mask process, the source-drain metal is patterned to form source-drain elements. The data line DL crosses the gate line GL in a vertical direction. The data pad DP is formed at one end of the data line DL. The data line DL branches from the source line DL to form a source region contact hole A source electrode S which is in contact with one side of the semiconductor layer A through a drain region contact hole DAH and a source electrode S which is in contact with the other side of the semiconductor layer A through a drain region contact hole DAH, And a drain electrode (D). In particular, the source electrode S and the drain electrode D are physically separated from each other, but have a structure connected through the semiconductor layer A. Thus, the thin film transistor T is completed.

The semiconductor layer A is etched by the etchant between the source electrode S and the drain electrode D in the process of patterning the source electrode S and the drain electrode D in the absence of the etch stopper layer ES, A back-etch phenomenon occurs. Particularly, when the semiconductor layer (A) includes an oxidized semiconductor material, if the back etch occurs, the stability of the device may be deteriorated. Therefore, it is preferable to include an etch stopper layer (ES) when forming a channel layer with an oxidized semiconductor material. (Figure 7d)

The first protective film PA1 is applied to the entire surface of the substrate SUB on which the thin film transistor T is completed. Then, the planarizing film (PAC) is coated with an organic material having a low dielectric constant. For example, the planarizing film (PAC) preferably comprises Nega Polyacrylate. The planarizing film (PAC) is patterned by the fifth mask process to form the first drain contact hole DH1. The first drain contact hole DH1 does not expose the drain electrode D. The second drain contact hole DH2 is formed to expose the drain electrode to the second protective film PA2 formed later. Since the thickness of the planarization film PAC is relatively thick, the formation of the second drain contact hole DH2 And to secure the exposed area of the drain electrode D in advance. The planarization layer PAC is removed from the gate pad GP and the data pad DP to expose the first passivation layer PA1. (Fig. 7E)

A transparent conductive material such as ITO (Indium Tin Oxide) is deposited on the entire surface of the substrate SUB on which the planarizing film PAC is formed. In the sixth mask process, the transparent conductive material is patterned to form the common electrode COM. It is preferable that the common electrode COM is formed to include a substantially rectangular shape corresponding to the shape of the pixel region. More preferably, the common electrode COM is formed to have a structure covering the data line DL. For example, the common electrode COM may be formed in a shape extending in the transverse direction so as to include all the pixel regions arranged in the horizontal direction. As another example, the common electrode COM may be formed so as to include the entire surface of the planarizing film (PAC) except for the thin film transistor (T) portion. The reason why the common electrode COM does not cover the thin film transistor T portion is that the pixel electrode PXL formed after the common electrode COM is connected to the drain electrode D of the thin film transistor T through the second drain To form the contact hole DH2. (Figure 7f)

The second protective film PA2 (or insulating film) is coated on the entire surface of the substrate SUB on which the common electrode COM is formed. In the seventh mask process, the second protective film PA2 and the first protective film PA1 are patterned to form a second drain contact hole DH2 exposing a part of the drain electrode D. At the same time, a data pad contact hole DPH exposing the data pad DP is formed. In the gate pad GP portion, a gate pad contact hole GPH exposing the gate pad GP by further etching the gate insulating layer GI with the second passivation layer PA2 and the first passivation layer PA1 is formed . (Fig. 7G)

A transparent conductive material such as ITO is further deposited on the second protective film PA2. In the eighth mask process, the transparent conductive material is patterned to form the pixel electrode PXL, the gate pad terminal GPT, and the data pad terminal DPT. The pixel electrode PXL is formed so as to overlap the common electrode COM with the second protective film PA2 interposed therebetween. In particular, they are formed as bars arranged in parallel at regular intervals. The pixel electrode PXL can be disposed as close as possible to the data line DL within the pixel region. Even if a part of the pixel electrode PXL overlaps with the data line DL, the pixel electrode PXL is connected to the data line DL by the common electrode COM disposed below and covering the data line DL, Lt; / RTI > The gate pad terminal GPT contacts the gate pad GP exposed through the gate pad contact hole GPH. The data pad terminal (DPT) contacts the data pad (GP) exposed through the data pad contact hole (DPH). (Fig. 7H)

Though not shown in the drawing, the thin film transistor substrate on which the pixel electrode PXL and the common electrode COM are formed is transferred to the alignment film processing chamber to apply the alignment film. Then, the liquid crystal layer is coated and adhered to the color filter substrate to complete the liquid crystal display panel.

In the second embodiment of the present invention, the surface of the substrate SUB on which the thin film transistor T is formed with the planarizing film PAC is flattened, and almost all the substrates except for the thin film transistor T SUB. And a pixel electrode PXL overlapping the common electrode COM with a second protective film PA2 being an insulating film interposed therebetween. Therefore, the area occupied by the common electrode COM and the pixel electrode PXL can be maximized, and the influence of the data line DL on the pixel electrode PXL can be minimized. As a result, a high quality thin film transistor substrate having a high aperture ratio and low power consumption is provided.

Furthermore, in the thin film transistor substrate having the same structure as that of the second embodiment, a plurality of insulating films and a protective film are stacked in the pixel region. The etch stopper layer ES is formed only in the thin film transistor region and is not formed in the pixel region. Accordingly, it is possible to obtain a structure in which the parasitic capacitance between the source electrode S and the gate wiring G is minimized, and the brightness of the backlight passing through the pixel region is not reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

T: Thin film transistor SUB: Substrate
GL: gate wiring CL: common wiring
DL: Data wiring PXL: Pixel electrode
COM: Common electrode GP: Gate pad
DP: Data pad GPT: Gate pad terminal
DPT: Data pad terminal
GPH: gate pad contact hole DPH: data pad contact hole
G: gate electrode S: source electrode
D: drain electrode A: semiconductor channel layer
GI: gate insulating film ES: etch stopper layer
SAH: source region contact hole DAH: drain region contact hole
PAS: protective film PAC: planarization film
PA1: first protective film PA2: second protective film (insulating film)
DH1: first drain contact hole DH2: second drain contact hole

Claims (6)

Board;
A gate wiring and a data wiring arranged on the substrate so as to be orthogonal to each other with a gate insulating film therebetween to define a pixel region;
A thin film transistor including a gate electrode branched from the gate wiring, a channel layer overlapping the gate electrode on the gate insulating film, a source electrode branched in the data line, and a drain electrode opposing the source electrode;
An etch stopper layer covering the channel layer region except regions contacting the source electrode and the drain electrode and the thin film transistor region excluding the pixel region between the gate electrode and the source electrode; And
And a protective film covering the thin film transistor.
The method according to claim 1,
A gate pad formed on one end of the gate wiring; And
And a data pad formed at one end of the data line,
Wherein the etch stopper layer is formed excluding the gate pad region.
The method according to claim 1,
A common electrode formed on the passivation layer to cover the pixel region in contact with the drain electrode;
An insulating film covering the common electrode; And
Further comprising: a pixel electrode formed on the insulating layer in the form of a plurality of line segments overlapping the common electrode.
The method of claim 3,
Further comprising a planarization layer formed on the entire surface of the substrate between the protective layer and the common electrode.
The method of claim 3,
Wherein the common electrode has a shape covering the pixel region and the data line arranged in the transverse direction.
The method of claim 3,
Wherein the common electrode has a shape covering the upper surface of the planarizing film except the region where the thin film transistor is formed.

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