KR101366916B1 - Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a liquid crystal display device which can prevent static electricity and at the same time improve the transmittance and reduce the cost.
A liquid crystal display according to the present invention comprises: an upper array substrate on which a conductive black matrix is formed; A lower array substrate bonded to the upper array substrate and having an electrostatic discharge line formed thereon; And a conductive sealant for bonding the upper array substrate and the lower array substrate to each other and electrically connecting the conductive black matrix and the electrostatic discharge line.

Description

[0001] The present invention relates to a liquid crystal display device,

The present invention relates to a liquid crystal display device.

In general, a liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal display panel in which liquid crystal cells are arranged in a matrix form by adjusting light transmittance of liquid crystal cells according to a video signal. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and driving circuits for driving the liquid crystal display panel.

Such liquid crystal displays are roughly classified into twisted nematic (TN) mode and in plan switch (IPS) mode using a vertical electric field according to the electric field driving the liquid crystal.

The TN mode is a mode in which a liquid crystal is driven by a vertical electric field between a pixel electrode and a common electrode arranged to face the upper substrate. The TN mode has an advantage that the aperture ratio is large while the viewing angle is folded. The IPS mode is a mode in which a liquid crystal is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate, and has a large viewing angle, but a small aperture ratio.

1 is a cross-sectional view showing a liquid crystal display panel of a conventional IPS mode.

Referring to FIG. 1, the liquid crystal display panel 90 in the IPS mode includes a black matrix 4, a color filter 6, a planarization layer 7, a spacer 13, and an upper part sequentially formed on the upper substrate 2. An upper array substrate (or color filter array substrate) 70 composed of an alignment layer 8, a thin film transistor (hereinafter referred to as " TFT ") 15 formed on the lower substrate 32, a common electrode 18, Liquid crystal injected into an inner space between the lower array substrate (or thin film transistor array substrate) 80 composed of the pixel electrode 16 and the lower alignment layer 38, and the upper array substrate 70 and the lower array substrate 80. (51) is provided.

In the upper array substrate 70, the black matrix 4 is formed to overlap the TFT 15 region of the lower substrate 2 and the region of gate lines and data lines not shown, and the color filter 6 is formed. Partition the cell area to be used. The black matrix 4 prevents light leakage and absorbs external light to enhance the contrast. The color filter 6 is formed in the cell region separated by the black matrix 4. The color filter 6 is formed for each of R, G, and B to implement R, G, and B colors. The planarization layer 7 is formed to cover the color filter 6 to planarize the upper substrate 2. The spacer 13 serves to maintain a cell gap between the upper substrate 2 and the lower substrate 32.

In the lower array substrate 80, the TFT 15 includes a gate electrode 9 formed on the lower substrate 32 together with a gate line (not shown), the gate electrode 9 and the gate insulating film 44. Semiconductor layers 14 and 47 overlapping each other, and source / drain electrodes 40 and 42 formed together with data lines (not shown) with semiconductor layers 14 and 47 interposed therebetween. The TFT 15 supplies the pixel signal from the data line to the pixel electrode 16 in response to the scan signal from the gate line. The pixel electrode 16 is a transparent conductive material having a high light transmittance and is in contact with the drain electrode 42 of the TFT 15 with the protective film 50 interposed therebetween. The common electrode 18 is formed in a stripe shape so as to alternate with the pixel electrode 16. The common electrode 18 supplies a common voltage which is a reference when driving the liquid crystal. The liquid crystal rotates with respect to the horizontal direction by the horizontal electric field between the common voltage and the pixel voltage supplied to the pixel electrode 16.

The upper and lower alignment layers 8 and 38 for liquid crystal alignment are formed by applying an alignment material such as polyimide and then performing a rubbing process.

On the other hand, in the TN mode liquid crystal display panel, the liquid crystal is driven by the vertical electric field between the upper array substrate and the lower array substrate, so that an equipotential loop can be formed between the upper array substrate and the lower array substrate. Small and easy discharge of static electricity. On the other hand, the liquid crystal display panel 90 in the IPS mode is driven by the liquid crystal 51 by a horizontal electric field so that the upper array substrate 70 and the lower array substrate 80 are electrically isolated from each other, and thus the amount of static electricity generated is relatively high. Emissions are also not easy.

In order to solve the problem of static electricity generation, as shown in FIG. 2, the transparent electrode pattern 3 is formed on the rear surface of the upper array substrate 70 and the Kate top 54 is formed using the conductive material 11. A structure for electrically connecting has been proposed. However, there is a disadvantage in that the light transmittance is lowered by the transparent electrode pattern 3 shown in FIG. 2 and the process and the cost are increased by forming the transparent electrode pattern 3.

Accordingly, as shown in FIG. 3, a structure for discharging static electricity to the outside through the case top 54 using the conductive polarizing plate 54 has been proposed. However, the structure shown in FIG. 3 also requires a significant amount of cost to produce a conductive polarizing plate. In addition, when the polarizing plate is formed on the rear surface of the lower array substrate 80, the lower conductive polarizing plate 56 is used to prevent static electricity generated when the protective layer of the polarizing plate is removed. However, such a structure has an increased cost due to the addition of a process for forming a conductive layer and an electrostatic treatment layer in addition to the protective layer (tri acetate cellulose: TAC) and the flatter (Poly Vinyl Alcohol (PVA)). There is.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device which can prevent static electricity and at the same time improve the transmittance and reduce the cost.

According to an exemplary embodiment of the present invention, an LCD device includes: an upper array substrate on which a conductive black matrix is formed; A lower array substrate bonded to the upper array substrate and having an electrostatic discharge line formed thereon; And a conductive sealant for bonding the upper array substrate and the lower array substrate to each other and electrically connecting the conductive black matrix and the electrostatic discharge line.

The upper array substrate and the lower array substrate form an equipotential loop by the electrostatic discharge line and the conductive sealant.

The static electricity discharge line is electrically connected to a ground.

The black matrix comprises chromium.

The lower array substrate is divided into a display area in which a thin film transistor array is formed and a non-display area except the display area, and the electrostatic discharge line is formed in the non-display area.

At least one insulating layer formed on the non-display area of the lower array substrate to cover the electrostatic discharge line; A first contact hole penetrating the insulating layer to expose the electrostatic discharge line; And a transparent conductive pattern contacting the electrostatic discharge line through the first contact hole and directly contacting the conductive sealant.

A gate driver integrated circuit for supplying a gate driving signal to a gate line of a thin film transistor array in the display area, and a data driver for supplying a data driving signal to a data line of the thin film transistor array in a non-display area of the lower array substrate; The circuit is mounted.

A printed circuit board for supplying control signals and direct current voltages to the data driver integrated circuit and the gate driver integrated circuit; A flexible printed circuit (FPC) electrically connecting the printed circuit board to the data driver integrated circuit and the gate driver integrated circuit, and the electrostatic discharge line is connected to the printed circuit board via the FPC. It is electrically connected to the ground formed on the top.

The thin film transistor array formed in the display area of the lower array substrate may include a gate line and a data line formed to cross each other; A thin film transistor positioned at the cross region; A pixel electrode in contact with the thin film transistor; And a common electrode forming a horizontal electric field with the pixel electrode.

The liquid crystal display according to the embodiment of the present invention forms an electrostatic discharge line positioned on the lower array substrate and electrically connected to the ground, and electrically connects the electrostatic discharge line and the conductive black matrix of the upper array substrate by using a conductive sealant. Turn on.

Accordingly, the upper array substrate and the lower array substrate may form an equipotential structure, and static electricity generated in the upper and lower array substrates may be discharged to the outside through the ground. As a result, eliminating the need for a conventional transparent electrode pattern while preventing static electricity, process reduction and cost are reduced, and the light transmittance is improved. In addition, by eliminating the need for a conductive polarizing plate or the like, the cost is reduced and the structure is simplified.

1 is a cross-sectional view showing a conventional IPS liquid crystal display panel.
2 is a view showing a static discharge structure using a transparent electrode pattern and a Kate top.
3 is a view showing a static discharge structure using a conductive polarizing plate and a Kate top.
FIG. 4 is a view showing specifically the structure of the conductive polarizer formed on the rear surface of the lower array substrate. FIG.
5 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 6 is a cross-sectional view illustrating a plane taken along the line II ′ of FIG. 5. FIG.
7A to 7D are process diagrams sequentially illustrating a manufacturing process of a lower array substrate.

Other objects and features of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 7D.

5 is a plan view schematically illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line II ′ of FIG. 5.

First, FIG. 5 illustrates a COG (Chip On Glass) type liquid crystal display as an example.

In the COG type liquid crystal display, a data driver and a gate driver are integrated into a plurality of integrated circuits (ICs), and each of the integrated data drive IC and the gate drive IC is mounted on a liquid crystal display panel.

That is, as shown in FIG. 5, the data drive integrated circuit (IC) 220 and the gate drive integrated circuit 230 are mounted on the non-display area P2 of the lower substrate 102 of the liquid crystal display device. The circuit 220 and the gate drive integrated circuit 230 are control signals input from the outside through signal lines mounted on a printed circuit board (PCB) 250 through a flexible printed circuit (FPC) 235. And DC voltages are supplied.

The structure of the liquid crystal display device of the present invention will be described in detail with reference to the cross-sectional view shown in FIG. 6. It is divided into a non-display area P2.

The display area P1 has a structure substantially the same as that shown in FIG. 1. That is, an upper array substrate (or color filter) including a black matrix 104, a color filter 106, a planarization layer 107, a spacer 113, and an upper alignment layer 108 sequentially formed on the upper substrate 102. Array substrate) 170, a lower array substrate (or thin film transistor array substrate) composed of a TFT 115, a common electrode 118, a pixel electrode 116, and a lower alignment layer 138 formed on the lower substrate 132; ) 180 and a liquid crystal (not shown) injected into an inner space between the upper array substrate 170 and the lower array substrate 180.

In the upper array substrate 170, the black matrix 14 is formed to overlap the TFT 115 region, the gate lines (not shown), and the data lines 104 of the lower substrate 102. 106 defines a cell region to be formed. The black matrix 104 prevents light leakage and absorbs external light to increase contrast. Here, the black matrix 104 is formed of a conductive metal material such as chromium (Cr).

The color filter 106 is formed in the cell region separated by the black matrix 104. The color filter 106 is formed for each of R, G, and B to implement R, G, and B colors. The planarization layer 107 is formed to cover the color filter 106 to planarize the upper substrate 102. The spacer 113 serves to maintain a cell gap between the upper substrate 102 and the lower substrate 132.

In the lower array substrate 180, the TFT 115 includes a gate electrode 109 formed on the lower substrate 132 along with a gate line (not shown), the gate electrode 109, and the gate insulating layer 144. Semiconductor layers 114 and 147 overlapping each other, and source / drain electrodes 140 and 142 formed together with the data lines 104 with the semiconductor layers 114 and 147 interposed therebetween. The TFT 115 supplies a pixel signal from the data line to the pixel electrode 116 in response to a scan signal from the gate line. The pixel electrode 116 is a transparent conductive material having a high light transmittance and contacts the drain electrode 142 through the first contact hole 117 of the TFT 115 with the passivation layer 150 therebetween. The common electrode 118 is formed in a stripe shape so as to alternate with the pixel electrode 116. The common electrode 118 supplies a common voltage which is a reference when driving the liquid crystal. The liquid crystal rotates with respect to the horizontal direction by the horizontal electric field between the common voltage and the pixel voltage supplied to the pixel electrode 116.

The upper and lower alignment layers 108 and 138 for liquid crystal alignment are formed by applying an alignment material such as polyimide and then performing a rubbing process. Meanwhile, in the present invention, although the common electrode 118 is formed at the same time as the gate electrode 109 as the gate metal layer, the common electrode 118 may be formed of a transparent electrode material simultaneously with the pixel electrode 116 as necessary. When the pixel electrode 116 and the common electrode 118 are formed of a transparent electrode material, the common electrode 118 is positioned on the passivation layer 150 on the same plane as the pixel electrode 116.

Only the black matrix 104 is positioned on the upper substrate 102 in the upper array substrate 170 in the non-display area P2, and the electrostatic discharge line 240 is disposed on the lower substrate 132 in the lower array substrate 180. ), A second contact penetrating through the gate insulating layer 144 and the passivation layer 150, the gate insulating layer 144 and the passivation layer 150 sequentially stacked on the electrostatic discharge line 240 to expose the electrostatic discharge line 240. The transparent conductive pattern 216 is in contact with the static electricity discharge line 240 through the hole 219. The static electricity discharge line 24 is electrically connected to the dummy ground pad 237 of the FPC 235. The dummy ground pad 237 is electrically connected to a ground located on the PCB 250.

The black matrix 104 of the upper array substrate 170 and the transparent conductive pattern 216 of the lower array substrate 180 in the non-display area P2 are electrically connected to each other through the conductive sealant 218. Accordingly, since the upper array substrate 170 and the lower array substrate 180 may have an equipotential structure, the static electricity generated in the upper array substrate 170 may pass through the FPC via the sealant 218 and the static discharge line 240. It is possible to be discharged to the outside through the dummy ground pad 237 of 235.

In the liquid crystal display according to the present invention having the above structure, the static electricity may be removed from the upper array substrate 170 as well as the lower array substrate 180.

In more detail, the liquid crystal display of the IPS mode is conventionally driven by the liquid crystal by a horizontal electric field, and compared with the liquid crystal display of the TN mode. It is relatively large and not easy to discharge. In order to solve this problem, in the present invention, the black matrix 104 of the upper array substrate 170 is formed of a conductive metal, the lower array substrate 180 is formed of an electrostatic discharge line 240, and the conductive sealant 218. ) To electrically connect the electrostatic discharge line 240 of the lower array substrate 180 and the conductive black matrix 104 of the upper array substrate 170. Accordingly, the upper array substrate 170 and the lower array substrate 180 may have an equipotential structure, and static electricity generated in the upper and lower array substrates 170 and 180 may be accumulated in the dummy ground pad 237 of the FPC 235. Can be discharged to the outside.

As a result, the transparent electrode pattern 3, which has been pointed out as a cause of the decrease in transmittance in the conventional antistatic structure, is eliminated, thereby reducing the process and the cost, and improving the light transmittance. In addition, since the conductive polarizing plate 53 is not required, the cost is reduced and the structure is simplified. That is, the present invention can improve the yield by reducing the static electricity, and at the same time improve the transmittance and reduce the cost.

5 and 6 illustrate a structure in which static electricity can be discharged from a COG structure, but this is only one embodiment, and any existing structure such as a structure in which a drain integrated circuit is mounted in a conventional TCP or the like is provided in the upper array. Technical features of the present invention may be utilized in which the substrate 170 and the lower array substrate 180 may be electrically conductive.

5 and 6 exemplarily illustrate that the static discharge line 240 is formed of a gate metal at the same time as the gate electrode 109 and the gate line, but the present invention is not limited thereto. The metal may be formed simultaneously with the data line 104 or the like.

When the static discharge line 240 is formed at the same time as the data line 104 and the like, the gate insulating layer 144 is positioned below the static discharge line 240, and the protective layer 150 is disposed on the static discharge line 240. The second contact hole 219 penetrates only the passivation layer 150 to expose the static electricity discharge line 240.

Hereinafter, a manufacturing process of the liquid crystal display shown in FIG. 6 by a four mask process will be described with reference to FIGS. 7A to 7D.

First, a gate metal layer is formed on the lower substrate 132 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, so that the gate electrode 109, the gate line (not shown), and the common electrode 118 of the TFT 115 are illustrated as shown in FIG. 7A. In the non-display area P2, a gate pattern such as an electrostatic discharge line 240 is formed.

As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

The gate insulating layer 144, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 132 on which the gate patterns are formed by a deposition method such as PECVD or sputtering.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the TFT as the second mask, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern to form a drain electrode 142 integrated with the data line 104, the source electrode 140 of the TFT 115, and the source electrode 140. do.

Then, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 148 and the active layer 114 of the TFT 115.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer of the channel portion are etched by a dry etching process. Accordingly, the active layer 114 of the channel portion of the TFT 115 is exposed to separate the source electrode 140 and the drain electrode 142.

Then, the photoresist pattern remaining on the source / drain pattern portion in the strip process is removed. As shown in FIG. 7B, a semiconductor pattern such as the active layer 114 and the ohmic contact layer 48 is formed by the second mask process, and the source electrode 140, the drain electrode 142, and the data line 104 are formed. A source / drain pattern such as) is formed.

As a material of the gate insulating film 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

The passivation layer 150 is formed entirely on the gate insulating layer 44 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 150 is patterned by a photolithography process and an etching process using a third mask to form first and second contact holes 117 and 219 as shown in FIG. 7C. The first contact hole 117 penetrates the passivation layer 150 to expose the drain electrode 142 of the TFT 115, and the second contact hole 219 forms the passivation layer 150 and the gate insulating layer 144. Through it, the static electricity discharge line 240 of the non-display area P2 is exposed.

As the material of the protective film 150, an inorganic insulating material such as the gate insulating film 144, an acryl based organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB is used.

The transparent electrode material is completely deposited on the protective film 150 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through the photolithography process and the etching process using the fourth mask, thereby forming the pixel electrode 116 and the transparent conductive pattern 216 as shown in FIG. 7D. The pixel electrode 116 is in contact with the drain electrode 142 of the TFT 115 through the first contact hole 117 to form a horizontal electric field with the common electrode 118, and the transparent conductive pattern 216 has a second contact hole. In contact with the static electricity discharge line 240 through 219.

As the transparent electrode material, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used.

The upper array substrate 170 on which the conductive black matrix 104, the color filter 106, the planarization layer 107, and the like are formed is provided separately from the lower array substrate 180 formed as described above. Thereafter, the upper array substrate 170 and the lower array substrate 180 are bonded to each other using the conductive sealant 218 containing a conductive ball or the like. Thus, the liquid crystal display panel is completed. On the other hand, in the case of the COG type liquid crystal display device, the gate drain integrated circuit 230 and the data drain integrated circuit 220 are mounted on the non-display area P2 of the lower array substrate 180. The inv integrated circuit 230 and the data draft integrated circuit 220 are supplied with a control signal and a voltage from the PCB 250 using the FPC 235.

Meanwhile, a method of removing static electricity by forming an equipotential loop between the upper array substrate and the lower array substrate using the static discharge line 240 and the conductive sealant 218 may be performed in the TN mode as well as in the liquid crystal display panel of the IPS mode. The liquid crystal display panel can be easily applied to a liquid crystal display panel, an ECB (Electric Controlled Birefringence), and a liquid crystal display panel in a VA (Vertical Alignment) mode.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

2,102: upper substrate 4,104: black matrix
3: transparent electrode pattern 52: polarizing plate
53: conductive polarizer 54: case top
18,118: common electrode 32,132: lower substrate
6,106 color filter 7,107 flattening layer
13,113: spacer 70,170: upper array substrate
80,180: lower array substrate 218: conductive sealant
240: static electricity discharge line 220: data draft integrated circuit
230: gate drive integrated circuit
235: FPC 250: PCB
219: transparent conductive pattern 237: FPC dummy pad

Claims (9)

An upper array substrate on which a conductive black matrix is formed;
A lower array substrate bonded to the upper array substrate and having an electrostatic discharge line formed thereon;
A conductive sealant bonding the upper array substrate to the lower array substrate and electrically connecting the conductive black matrix and the electrostatic discharge line, wherein the conductive sealant is continuously formed at an edge of the upper array substrate, and the conductive black A surface contact is made without a contact hole with a matrix, and only the conductive black matrix is positioned in a non-display area of the upper array substrate, and the electrostatic discharge line is electrically connected to a dummy ground pad of a flexible printed circuit (FPC). Liquid crystal display device characterized in that. The method of claim 1,
The upper array substrate and the lower array substrate
And forming an equipotential loop by the electrostatic discharge line and the conductive sealant. The method of claim 1,
The electrostatic discharge line is characterized in that the liquid crystal display device electrically connected to the ground (Ground). The method of claim 1,
And the black matrix comprises chromium. The method of claim 1,
The lower array substrate
Divided into a display area where a thin film transistor array is formed and a non-display area except the display area,
And the electrostatic discharge line is formed in the non-display area. The method of claim 5, wherein
In the non-display area of the lower array substrate
At least one insulating layer formed to cover the electrostatic discharge line;
A first contact hole penetrating the insulating layer to expose the electrostatic discharge line;
And a transparent conductive pattern in contact with the electrostatic discharge line through the first contact hole and in direct contact with the conductive sealant. The method of claim 5, wherein
In the non-display area of the lower array substrate
And a gate driver integrated circuit for supplying a gate driving signal to a gate line of the thin film transistor array in the display area, and a data driver integrated circuit for supplying a data driving signal to a data line of the thin film transistor array. Display. The method of claim 7, wherein
A printed circuit board for supplying control signals and direct current voltages to the data driver integrated circuit and the gate driver integrated circuit;
A flexible printed circuit (FPC) electrically connecting the printed circuit board with the data driver integrated circuit and the gate driver integrated circuit,
And the electrostatic discharge line is electrically connected to a ground formed on the printed circuit board via the FPC. The method of claim 5, wherein
The thin film transistor array formed in the display area of the lower array substrate
A gate line and a data line formed to cross each other;
A thin film transistor positioned at the cross region;
A pixel electrode in contact with the thin film transistor;
And a common electrode forming a horizontal electric field with the pixel electrode.

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