KR20140042354A - Display device and data processing method thereof - Google Patents

Abstract

The present invention relates to a display device and a data processing method thereof. The display device comprises a timing controller which receives input timing signals with pixel data of an input image, stores the pixel data in a memory based on the input timing signals, and reads the pixel data stored in the memory based on an inner timing signal to transfer to a display panel operating circuit. The inner timing signal is generated in the timing controller in a fixed timing irrelevant to the input timing signal.

Description

DISPLAY APPARATUS AND DATA PROCESSING METHOD THEREOF

The present invention relates to a display device and a data processing method thereof.

Input video data and a timing signal synchronized with the input video data are input to the display device. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock CLK, as shown in FIG. The vertical synchronization signal (Vsync) has a period of one frame period, and the vertical synchronization signal (Hsync) and the data enable signal (DE) have a period of one horizontal period. The pixel data of the input image is input in synchronization with the pulse of the data enable signal DE. In Fig. 1, "FP" indicates a vertical front porch from the polling edge of the last data enable signal DE synchronized with the last line data (the last line of the screen) to the polling edge where the vertical synchronizing signal Vsync starts Porch, FP). "VSW" is a vertical synchronization width (VSW) "BP" between the rising edge of the vertical synchronization signal Vsync and the rising edge immediately after the rising edge of the vertical synchronization signal Vsync, (Vertical Back, BP) to the start of the enable signal (DE, the first line of the screen). "Vblank" is a time obtained by adding a vertical front porch (FP), a vertical sync window (VSW), and a vertical back porch (BP), and is a vertical blank time without pixel data of an input image. Quot; Hblank "is a horizontal blank time in which there is no pixel data from the falling edge of the data enable signal DE to the rising edge immediately thereafter.

The timing controller of the display device counts the timing signals as shown in Fig. 1 and controls the operation timing of the display panel driving circuit. The timing signal can be temporarily shaken when the input interface is switched or when switching between 2D mode and 3D mode. When the timing signal is shaken, an abnormal screen is displayed on the display panel. These problems are also occurring in other display devices, but they are becoming more serious in organic light emitting displays. This is because a large number of thin film transistors (TFT) are included in each of the pixels of the organic light emitting display and gate signals for turning on and off the switch TFTs are applied to the pixels as many as the number of switch TFTs .

For example, if the gate signals required for the pixels of the organic light emitting diode display device are A to F as shown in FIG. 2, the timing controller generates a vertical signal Vsync from the start point of the vertical back- Counts the synchronous signal to the main clock CLK and generates gate signals A to F to be applied to the pixels based on the count value. When the timing signals (Vsync, Hsync, DE) input from the outside are shaken, the vertical back / front positives (BP, FP) are shaken and the count start timing is shaken. As a result, F) is shaking. Further, other gate signals (A to C) are generated before the first scan signal (D) to be synchronized with the pixel data in the first line of the screen. During this time, some data enable signals (DE) and The effective pixel data synchronized with the effective pixel data may be omitted in the sampling process.

3 shows a state in which the gate signals A to C are generated before the first scan signal D to be synchronized with the pixel data to be written in the first line of the screen and the gate signals A to C are generated Pulses of the first and second data enable signals and two lines of pixel data synchronized with the pulses are omitted. In this case, the pixel data to be written in the first and second lines of the screen are lost, and the pixel data of the third line is written in the first line of the pixel array to shift the screen upward.

Since the liquid crystal display device does not need any other gate signals other than the scan signal, there is a time margin for sampling the pixel data so as to follow the shaking timing signal even if the timing signal is shaken. On the other hand, in order to initialize the pixels and to sample and compensate the threshold voltages of the driving elements, many organic light emitting display devices must input a large number of gate signals to the pixels before the scan signals. The organic light emitting display device generates different gate signals A to C for several to several ten horizontal periods prior to the scan signal so that pixel data input during the generation of the gate signals A to C are not displayed on the screen It is easy to be lost.

The present invention provides a display device capable of normally displaying an input image on a screen even when input timing signals are shaken, and a data processing method thereof.

A display device of the present invention includes: a display panel for displaying an input image; A display panel driving circuit for writing pixel data of the input image on the display panel; A memory for storing pixel data of the input image; And a controller for receiving input timing signals together with pixel data of the input image, storing the pixel data in the memory on the basis of the input timing signals, reading the pixel data stored in the memory on the basis of an internal timing signal, To the display panel drive circuit.

The internal timing signal is generated in the timing controller at a fixed timing regardless of the input timing signal.

A data processing method of the display device includes the steps of receiving input timing signals together with pixel data of an input image to a timing controller and generating an internal timing signal in the timing controller; Storing the pixel data in a memory based on the input timing signals under the control of the timing controller; And reading the pixel data stored in the memory based on the internal timing signal under the control of the timing controller and transmitting the read pixel data to a display panel driving circuit for driving the display panel.

According to the present invention, pixel data is stored in a memory on the basis of an input timing signal input together with pixel data of an input image from the outside, and based on an internal timing signal generated in the timing controller at a fixed timing regardless of the input timing signal And reads pixel data from the memory. As a result, the present invention can display pixel data of the input image normally on the screen of the display device even if the input timing signals swing.

1 is a waveform diagram showing input timing signals.
2 is a diagram illustrating an example in which pixel data of a first line is synchronized with a first scan signal when input timing signals are fixed.
3 is a diagram illustrating an example in which pixel data of a third line is synchronized with a first scan signal when input timing signals are fixed.
4 is a block diagram schematically illustrating a display device according to an embodiment of the present invention.
5 and 6 are views illustrating a data processing method according to an embodiment of the present invention.
7 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention.
8 is a block diagram showing a circuit configuration of the timing controller shown in FIG.
9 is a circuit diagram showing an example of the pixel shown in Fig.
10 is a waveform diagram showing the operation of the pixel shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The display device of the present invention may be applied to a liquid crystal display (LCD), an organic light emitting display, a field emission display (FED), a plasma display panel (PDP) , An electrophoresis (EPD) display device, or the like. In the following embodiments, an organic light emitting display device is exemplified as an example of a flat panel display device, but it should be noted that the display device of the present invention is not limited to the organic light emitting display device.

Referring to FIG. 4, a display device according to an embodiment of the present invention includes a display panel 10, a display panel driving circuit 100, a timing controller 11, a memory 20, and the like.

In the display panel 10, data lines to which data signals are applied, gate lines to which gate signals are sequentially applied, and pixel arrays in which pixels are arranged in a matrix type defined by data lines and gate lines that are orthogonal to each other . The gate signal includes a scan signal (D in Fig. 5) synchronized with the data signal. In addition, the gate signal may further include gate signals (A to C, F) other than the scan signal as shown in FIG. For example, gate signals such as an initialization signal, a light emission control signal, and the like must be input to pixels in an organic light emitting display device in addition to a scan signal. The display panel driving circuit 100 includes a data driving circuit for supplying a data signal to the data lines and a gate driving circuit for sequentially supplying gate signals to the gate lines, And writes to the pixels.

The timing controller 11 receives pixel data (digital video data) of an input image on the basis of an input timing signal such as a vertical synchronization signal Vsync and a data enable signal DE input from an external host system And stores write pixel data in the memory 20. [ The timing controller 11 reads the pixel data stored in the memory 20 on the basis of an internal timing signal generated internally using the internal timing signal generator, and transmits the read pixel data to the data driving circuit. In addition, the timing controller 11 generates timing control signals for controlling the operation timing of the display panel driving circuit 100 on the basis of the internal timing signal. The timing control signals are divided into a data timing control signal for controlling the operation timing of the data driving circuit and a gate timing control signal for controlling the operation timing of the gate driving circuit.

The host system may be implemented by any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system transmits the input timing signals (Vsync, Hsync, CLK, DE) to the timing controller 11 together with the pixel data (digital video data) of the input image.

5 and 6 are views illustrating a data processing method according to an embodiment of the present invention.

5 and 6, the timing controller 11 stores the pixel data of the input image in the memory 20 based on the input timing signals Vsync and DE, and then outputs the internal timing signals Vs_gen, De_gen The data stored in the memory 20 is read. Internal timing signals Vs_gen and De_gen are generated in the timing controller 11 regardless of input timing signals Vsync and DE input from the outside. Therefore, the internal timing signals Vs_gen and De_gen are generated at a fixed timing even if the input timing signals Vsync and DE are fluctuated. "Vs_gen" is an internal vertical synchronizing signal generated in the timing controller 11, and "De_gen" is an internal data enable signal generated in the timing controller 11. The internal vertical synchronizing signal Vs_gen has a period of one frame period in the same manner as the input receiving synchronizing signal Vsync. The internal data enable signal De_gen is synchronized with one line of pixel data stored in the memory 20. [

The timing controller 11 stores, in the memory 20, effective pixel data synchronized with a data enable signal DE input from the outside. Then, the timing controller 11 reads the pixel data stored in the memory 20 based on the internal timing signals Vs_gen and De_gen, which are always generated at a fixed timing regardless of the input timing signal. Therefore, even if the pixel data of the first line is input before the first scan signal is generated in the timing controller 11, the pixel data is stored in the memory 20, so that even if the input timing signals are shaken, Can be synchronized with the first scan signal.

As a memory 20, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) having a high read and write speed can be selected. In order to simultaneously perform parallel reading and writing, the first and second memories 20a , 20b. For example, the pixel data of the Nth (N is a positive integer) -1 frame stored in the first memory 20a is the pulse timing of the internal data enable signal De_gen during the Nth frame period FR (N) And is transmitted to the timing controller 11. [ At the same time, the pixel data of the Nth frame input during the Nth frame period FR (N) is written into the second memory 20b in accordance with the pulse timing of the input data enable signal DE. Then, the pixel data of the (N + 1) -th frame inputted during the (N + 1) -th frame period FR (N + 1) is written into the first memory 20a in accordance with the pulse timing of the input data enable signal DE. At the same time, the pixel data of the Nth frame stored in the first memory 20a is read in accordance with the pulse timing of the internal data enable signal De_gen for the (N + 1) -th frame period FR (N + 1) 11).

7 and 8 show an OLED display according to an embodiment of the present invention.

7 and 8, an OLED display according to an exemplary embodiment of the present invention includes a display panel 10, a panel driving circuit for writing data to the display panel 10, a timing controller 11, and the like do. The panel driving circuit includes a data driving circuit (12) and a gate driving circuit (13).

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 are crossed, and the pixels P are arranged in a matrix form. The gate lines 15 are divided into scan lines 15a, emission lines 15b, and initialization lines 15c. Each of the pixels P may be connected to the data line 14, the scan line 15a, the emission line 15b, and the initialization line 15c as shown in FIG. Each of the pixels P may be formed of a circuit including an organic light emitting diode (OLED), a driving TFT, four switch TFTs, and two capacitors as shown in FIG. 9 But is not limited thereto. For example, the pixels P include an OLED, a driving element for adjusting the current flowing in the OLED according to the data voltage, one or more switching elements, one or more capacitors, and the like, And then emit the OLED in response to the emission control signal.

The timing controller 11 writes the digital video data RGB input from the external host system into the memory 20 based on the input timing signals Vsync, Hsync, DE, and CLK, (Vs_gen, De_gen), and transfers the read pixel data to the data driving circuit 12. The timing controller 11 counts internal timing signals Vs_gen and De_gen and compares the count value with previously stored waveform information to generate a data timing control signal DDC for controlling the operation timing of the data driving circuit 12 ) And a gate timing control signal (GDC) for controlling the operation timing of the gate drive circuit (13). The waveform information may be stored in advance in an EEPROM (Electrically Erasable Programmable Read-Only Memory) connected to the timing controller 11. [ Rising timing information and on-duty timing information of the data timing control signal and the gate timing control signal are included in the waveform information as a count value. The timing controller 11 includes a memory control unit 2, a timing control signal generating unit 4, an internal timing signal generating unit 6, and the like. The memory control unit 2 controls the reading and writing operations of the memory 20 in the same manner as in Figs. The timing control signal generator 4 generates a gate timing control signal GDC and a data timing control signal DDC on the basis of the internal timing signals Vs_gen and De_gen. The internal timing signal generator 6 generates internal timing signals Vs_gen and De_gen at fixed timings irrespective of the input timing signals as shown in FIG. 5 and FIG.

The data driving circuit 12 converts the pixel data (digital video data, RGB) input from the timing controller 11 into a gamma compensation voltage to generate an analog data voltage, supplies the data voltage to the data lines 14 do. The gate driver circuit 13 generates gate signals under the control of the timing controller 11 and sequentially shifts the gate signals in units of row lines of the pixel array.

Fig. 9 is a circuit diagram showing an example of the pixel P. Fig. FIG. 10 is a waveform diagram showing the operation of the pixel P shown in FIG.

9 and 10, the pixel P includes an OLED, a driving TFT DT, first to fourth switch TFTs ST1 to ST4, a compensation capacitor Cgss, and a storage capacitor Cst.

Each of the pixels P is supplied with pixel driving power such as a high potential power supply voltage EVDD, a low potential power supply voltage EVSS, a reference voltage Vref, and an initialization voltage Vinit. The reference voltage Vref and the initialization voltage Vinit may be set to be lower than the low potential power supply voltage EVSS. The reference voltage Vref is set higher than the initializing voltage Vinit. The difference between the reference voltage Vref and the initialization voltage Vinit can be set to be larger than the threshold voltage of the driving TFT.

The OLED emits light by the current supplied from the driving TFT DT. Organic compound layers are deposited between the anode and the cathode of the OLED. The organic compound layers of the OLED include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer layer, EIL). However, the present invention is not limited thereto and can be applied to any known OLED structure. The OLED emits light when electrons and holes are combined in the organic layer by causing current to flow through the fluorescent or phosphorescent organic thin film.

The driving TFT DT adjusts the current flowing in the OLED with its own gate-source voltage. The gate electrode of the driving TFT DT is connected to the node B, the drain electrode is connected to the high potential cell drive voltage (EVDD) input terminal, and the source electrode is connected to the node C, respectively.

The first switch TFT (ST1) switches the current path between the node A and the node B in response to the emission control signal EM. The first switch TFT (ST1) is turned on to transfer the data voltage (Vdata) stored in the node A to the node B. The gate electrode of the first switch TFT (ST1) is connected to the emission line 15b, the drain electrode to the node A, and the source electrode to the node B, respectively.

The second switch TFT (ST2) switches the current path between the input terminal of the initializing voltage (Vinit) and the node C in response to the initialization signal INIT. The second switch TFT (ST2) is turned on to supply the initialization voltage (Vinit) to the node C. The gate electrode of the second switch TFT (ST2) is connected to the initialization line 15c, the drain electrode is connected to the input terminal of the initialization voltage (Vinit), and the source electrode is connected to the node C, respectively.

The third switch TFT (ST3) switches the current path between the input terminal of the reference voltage (Vref) and the node B in response to the initialization signal INIT. The third switch TFT (ST3) is turned on to supply the reference voltage (Vref) to the node B. The gate electrode of the third switch TFT (ST3) is connected to the initialization line (15c), the drain electrode is connected to the input terminal of the reference voltage (Vref), and the source electrode is connected to the node B.

The fourth switch TFT (ST4) switches the current path between the data line 14 and the node A in response to the scan signal (SCAN). The fourth switch TFT (ST4) is turned on to supply the data voltage (Vdata) to the node A. [ The gate electrode of the fourth switch TFT (ST4) is connected to the scan line (15a), the drain electrode to the data line (14) and the source electrode to the node A, respectively.

A compensation capacitor (Cgss) is connected between node B and node C. The compensation capacitor Cgss enables a source follower scheme when detecting the threshold voltage of the driving TFT DT and contributes to improvement of the compensation ability against the threshold voltage.

The storage capacitor Cst is connected between node A and node C. The storage capacitor Cst stores the data voltage Vdata input to the node A and transfers the data voltage Vdata to the node C.

The operation of the pixel P includes an initializing period Ti for initializing the nodes A, B and C to a specific voltage, a sensing period Ts for detecting and storing a threshold voltage of the driving TFT DT, The programming period Tp for applying the data voltage Vdata to the pixel P and the driving TFT DT driven according to the data voltage Vdata unaffected by the threshold voltage of the driving TFT DT And a light emission period Te for supplying the light emission period Te. The light emission period Te can be divided into the first and second light emission periods Te1 and Te2.

In the initialization period Ti, the second and third switch TFTs ST2 and ST3 are simultaneously turned on in response to the initialization signal INIT of a high logic level. The first switch TFT ST1 is turned on in response to the first pulse P1 of the emission control signal EM in the setup period Ti. The first pulse P1 of the emission control signal EM overlaps with the initialization signal INIT. It is preferable that the pulse of the initialization signal INIT is set wider than the first pulse Pl of the emission control signal EM to stabilize the initialization. As a result, the initializing voltage Vinit is supplied to the node C and the reference voltage Vref is supplied to the node B during the initialization period Ti. In addition, the reference voltage Vref is supplied to the node A via the first and third switch TFTs ST1 and ST3. The fourth switch TFT (ST4) maintains the off state in the initialization period (Ti). The reference voltage Vref is set to be higher than the initialization voltage Vinit in order to make the gate voltage of the driving TFT DT higher than the source voltage and make the drain-source current path of the driving TFT DT conductive.

The initialization voltage Vinit is appropriately set to a low value so that the OLED is not prevented from being emitted in the remaining periods Ti, Ts and Tp except for the emission period Te. For example, when the high potential cell drive voltage EVDD is set to 20V and the low potential cell drive voltage EVSS is set to 0V, the reference voltage Vref and the initialization voltage Vinit can be set to -1V and -5V, respectively have.

The scan signal SCAN, the emission control signal EM and the initialization signal INIT are supplied to the scan line 15a, the emission line 15b, and the initialization line 15b for selecting one line of the pixel array, 15c. ≪ / RTI > These signals SCAN, EM and INIT are supplied to the gate lines 15 while being shifted by a row line unit of the pixel array.

In the sensing period Ts, the emission control signal EM and the initialization signal INIT are inverted to a low logic level. The scan signal SCAN is also held at the low logic level in the sensing period Ts. As a result, the first to fourth switch TFTs ST1, ST2, ST3, and ST4 maintain the off state during the sensing period Ts, and the current Idt flowing through the drive TFT DT is gradually reduced. When the gate-source voltage of the driving TFT DT reaches the threshold voltage Vth of the driving TFT DT, the driving TFT DT is turned off. At this time, the threshold voltage Vth of the driving TFT DT becomes Is detected in the source follower manner and charged to the node C.

In the programming period Tp, the fourth switch TFT ST4 is turned on by the high logic level scan signal SCAN synchronized with the data voltage Vdata of the input image. At this time, the data voltage (Vdata) is supplied to the node A. The first to third switch TFTs ST1, ST2, and ST3 remain off during the programming period Tp. In the programming period Tp, since the nodes B and C are separated from the node A by the TFT or the capacitor, the potentials in the sensing period Ts are almost maintained.

In the first light emission period Te1, the first switch TFT ST1 is turned on by the second pulse P2 of the light emission control signal EM. At this time, the data voltage (Vdata) charged in the node A is transferred to the node B. The second to fourth switch TFTs ST2, ST3, and ST4 maintain the off state during the first emission period Te1. The driving TFT DT supplies a current proportional to the data voltage Vdata to the OLED in the first emission period Te1. During the first light emission period Te1, when the potential of the node C rises due to the current flowing through the driving TFT DT and the potential thereof rises above the threshold voltage of the OLED, it is increased to "Voled" , So that the OLED is turned on and emits light.

In the second light emission period Te2, the first to fourth switch TFTs ST1, ST2, ST3, and ST4 are kept off. The second light emission period Te2 is set for preventing deterioration of the first switch TFT ST1 to which the light emission control signal EM is applied. To this end, the emission control signal EM is inverted to a low logic level during the second emission period Te2 to compensate the gate bias stress of the first switch TFT (ST1).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

2: memory control unit 4: timing control signal generating unit
6: internal timing signal generator 10: display panel
11: timing controller 12: data driving circuit
13: gate drive circuit 14: data line
15: gate line 100: display panel driving circuit

Claims (5)

A display panel for displaying an input image;
A display panel driving circuit for writing pixel data of the input image on the display panel;
A memory for storing pixel data of the input image; And
And a control circuit for receiving the input timing signals together with the pixel data of the input image, storing the pixel data in the memory based on the input timing signals, reading the pixel data stored in the memory on the basis of the internal timing signal, And a timing controller for transmitting to the panel drive circuit,
Wherein the internal timing signal is generated in the timing controller at a fixed timing regardless of the input timing signal. The method according to claim 1,
Wherein the internal timing signal includes an internal vertical synchronizing signal having a period of one frame period and an internal data enable signal synchronized with one line of pixel data stored in the memory. 3. The method of claim 2,
The display panel driving circuit includes:
A data driving circuit for converting the pixel data into data voltages and supplying the data voltages to the data lines of the display panel;
And a gate driving circuit for supplying gate signals to the gate lines of the display panel,
The timing controller includes:
And generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the internal timing signal. The method of claim 3,
The gate signals,
A scan signal applied to the pixel in synchronization with the data voltage, an initialization signal applied to the pixel before the scan signal to initialize the pixel, and a light emission control signal,
Wherein the emission control signal includes a first pulse generated before the scan signal, and a second pulse delayed from the scan signal. The input timing signals are received by the timing controller together with the pixel data of the input image, and an internal timing signal is generated in the timing controller;
Storing the pixel data in a memory based on the input timing signals under the control of the timing controller; And
And reading the pixel data stored in the memory based on the internal timing signal under control of the timing controller and transmitting the read pixel data to a display panel driving circuit for driving the display panel,
Wherein the internal timing signal is generated in the timing controller at a fixed timing regardless of the input timing signal.

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