KR20170034265A - Organic light emitting diode display device - Google Patents

Abstract

The organic light emitting diode display device of the present invention includes a display panel having a plurality of pixels, a timing controller for modulating an input timing control signal defined by a vertical blank period and setting an extension vertical blank period by rearranging at least two vertical blank periods in parallel, and a display panel for driving the signal lines of the display panel within the extension vertical blank period and sensing the electrical characteristics of pixels. So, sufficient sensing time can be secured.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

Since the organic light emitting diode display device is a self-luminous device, power consumption is lower than that of a liquid crystal display device requiring a backlight, and thus the organic light emitting diode display device can be made thinner. In addition, the organic light emitting diode display device has a wide viewing angle and a high response speed. Organic light emitting diode (OLED) display devices are expanding their market by competing with liquid crystal display devices by developing process technology up to the level of large-screen mass production technology.

The pixels of the organic light emitting diode display include organic light emitting diodes (OLEDs), which are self-luminous elements. 1, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (EML) are formed between an anode and a cathode, a transport layer (ETL), and an electron injection layer (EIL). The organic light emitting diode display reproduces an input image by using a phenomenon in which electrons and holes are emitted from an organic layer in a pixel OLED through a current flow in a fluorescent or phosphorescent organic thin film.

The organic light emitting diode display device can be divided into various types according to kinds of light emitting materials, light emitting systems, light emitting structures, driving systems, and the like. The organic light emitting diode display device can be divided into a fluorescent emission and a phosphorescent emission according to a light emission method, and can be divided into a top emission structure and a bottom emission structure according to a light emission structure. In addition, the organic light emitting diode display device can be divided into PMOLED (Passive Matrix OLED) and AMOLED (Active Matrix OLED) according to the driving method.

The pixels of the organic light emitting diode display include a driving TFT (Thin Film Transistor) for adjusting a driving current flowing in the OLED according to data of an input image. Though the electrical characteristics of the driving TFT, such as the threshold voltage and the mobility, should be designed to be the same in all the pixels, the characteristics of the driving TFT are not uniform in accordance with the process variation, the driving time, and the driving environment. For similar reasons, the operating point voltage of the OLED between the pixels is also non-uniform. Accordingly, a technology for sensing the difference in electrical characteristics between pixels and appropriately changing and compensating input digital video data according to a sensing result is applied to the organic light emitting diode display device.

The electrical characteristics of the pixels during the normal operation of the organic light emitting diode display can be made within a vertical blank period in which data of the input image is not written to the pixels. The vertical blank period means a period during which the data enable signal (Data Enable, DE) is maintained at a low logic level, and is arranged between vertical active periods in which data of the input image is written to the pixels.

The vertical blank period is significantly shorter than the vertical active period.

It takes a long time to sense the electrical characteristics of the pixels, and it is difficult to secure the sensing time during normal driving. In particular, as the OLED display becomes larger or resolution increases, the number of pixels and the load within the panel increase. As a result, the time for sensing the electrical characteristics of the pixels is further increased.

Thus, since the time required to sense the electrical characteristics of the pixels in the vertical blank period during normal driving is prolonged, there is a great difficulty in sufficiently securing the sensing time for sensing the electrical characteristics of the pixels.

An object of the present invention is to provide an organic light emitting diode display device capable of sufficiently securing a sensing time.

The organic light emitting diode display device of the present invention includes a display panel having a plurality of pixels, a timing controller for modulating a timing control signal defining a vertical blanking period to set at least two vertical blanking periods to be neighbingly rearranged to set an extended vertical blanking period And a display panel driving circuit for driving the signal lines of the display panel within the controller and the extended vertical blank period to sense the electrical characteristics of the pixels.

The extended vertical blanking period is arranged every N (N is a positive integer equal to or larger than 2) frames.

The input timing control signal is a data enable signal, and the timing controller modulates the data enable signal to define an extended vertical blank period and a modulation vertical active period.

After the vertical active period N (N is a positive integer of 2 or more) are successively arranged in order, the extended vertical blank period N is sequentially arranged in order (N is a positive integer of 2 or more).

The timing controller includes a frame memory for storing input digital video data for image display and outputting the input digital video data to the display panel drive circuit during the modulation vertical active period.

The electrical characteristic of the pixel represents at least one of the operating point voltage of the organic light emitting diode included in the pixels, the threshold voltage of the driving TFT included in the pixels, and the electric mobility of the driving TFT included in the pixels.

The timing controller compensates the luminance by varying the gain between the frame including the extended vertical blank period and the frame for which the extended vertical blank period is skipped.

The present invention modulates an input timing control signal that defines a vertical blank period to rearrange at least two or more vertical blank periods neighbely. As a result, the present invention can sufficiently assure the real time sensing time by merging the vertical blank periods. As described above, by sufficiently securing the sensing time, the compensation performance can be improved and the lifetime of the panel can be increased.

Further, since the present invention can secure a sufficient sensing time, it is possible to sense the electrical characteristics of a pixel even at a low gradation with a low pixel current, and it is possible to provide a high resolution, . As a result, the present invention can be effectively applied to a high resolution, fixed three organic light emitting display.

1 is a view showing an OLED structure and its light emitting principle.
2 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention.
3 is an equivalent circuit diagram of a pixel.
4 is a waveform diagram showing signals for sensing changes in electrical characteristics of a pixel.
5 is a waveform diagram showing a comparison between a display timing according to an input timing signal and a display timing reset according to the present invention.
6 is a block diagram illustrating a timing controller according to an embodiment of the present invention,
FIGS. 7 and 8 are views showing that the vertical blanking period according to the embodiment of the present invention is rearranged and expanded.
FIG. 9 is a diagram illustrating a vertical blanking period according to another embodiment of the present invention rearranged and expanded. FIG.
FIG. 10 is a diagram showing that an inter-frame emission period varies while an extended vertical blank period is implemented for every N frames.
11 is a flowchart for compensating for a luminance variation caused by a difference of an inter-frame emission period.
12 is a flowchart for generating a gain for compensating for a luminance variation caused by a difference of an inter-frame emission period.
FIG. 13 is a diagram illustrating a vertical blanking period according to an embodiment of the present invention rearranged and expanded through simulation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

2 to 4, an organic light emitting diode display device according to an embodiment of the present invention includes a display panel 10, a timing controller 11, and a display panel driving circuit.

In the pixel array of the display panel 10, data of the input image is displayed. The pixel array of the display panel 10 includes a plurality of data lines 14 and a plurality of scan lines 15 intersecting the data lines 14 and pixels P arranged in a matrix form . Each of the pixels P may be divided into a red subpixel R, a green subpixel G and a blue subpixel B for color implementation.

Reference lines 16 for sensing the electrical characteristics of the pixels P are formed on the display panel 10. A pair of scan lines may be connected to each of the subpixels so that first and second scan signals (Scan A, Scan B) may be applied.

The electrical characteristics of the pixel include the operating point voltage of the organic light emitting diode, the threshold voltage of the driving TFT, the mobility of the driving TFT, and the like.

Each of the pixels P may include, but is not limited to, three TFTs T1, T2, and T3, one storage capacitor Cst, and an OLED, as shown in FIG. As shown in FIG. 1, the OLED may include organic compound layers including a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The first TFT T1 applies a data voltage input through the data line 14 to the gate of the second TFT T2 via the first node A in response to the first scan pulse Scan A. The gate of the first TFT (T1) is connected to the first scan line (15) to which the first scan pulse (Scan A) is applied.

The drain of the first TFT T1 is connected to the data line 14 and the source of the first TFT T1 is connected to the gate of the second TFT T2 via the first node A. The second TFT T2 is a driving TFT and adjusts the current flowing in the OLED according to the gate voltage. And the high-potential pixel power supply voltage VDD is applied to the drain of the second TFT T2. The source of the second TFT (T2) is connected to the anode of the OLED via the second node (B). The third TFT T3 couples the second node B and the third node C in response to the second scan pulse ScanB. The third node C is connected to the reference line 16. A sensing unit 17 may be connected to the reference line 16. The sensing unit 17 may sample the voltage of the second node B as a sensing voltage for a predetermined sensing time after supplying the reference voltage to the second node B for a predetermined initialization period.

The drain of the third TFT (T3) is connected to the second node (B), and the source thereof is connected to the third node (C). The gate of the third TFT T3 is connected to a second scan line 15 to which a second scan pulse (Scan B) is applied. The storage capacitor Cst is connected between the gate and source of the second TFT T2 through the first and second nodes A and B. [ The anode of the OLED is connected to the source of the second TFT (T2), and the cathode of the OLED is connected to the ground voltage source (GND).

The display panel drive circuit includes a data drive circuit (12) and a scan drive circuit (13). The display panel drive circuit writes the data of the input image to the pixel array of the display panel 10. [ The display panel drive circuit drives the signal lines (14, 15) of the display panel within the extended vertical blank period to sense the electrical characteristics of the pixels.

The data driving circuit 12 includes one or more source drive ICs (integrated circuits). The data driving circuit 12 converts the modulated pixel data DATA 'of the input image input from the timing controller 11 into an analog gamma And generates a data voltage and outputs the data voltage to the data lines 14. [ Each of the modulated pixel data (DATA ') reworked in consideration of the extended vertical blank period includes red data, green data, and blue data.

The data driving circuit 12 further includes a sensing unit 17 connected to the reference line 16 and an analog-to-digital converter (ADC) connected to the sensing unit 17 do. The sensing unit 17 supplies the reference voltage to each pixel through the reference line 16 and samples the electrical characteristic of each pixel as the sensing voltage through the reference line 16 and then outputs the analog sensing value to the ADC Supply. The ADC converts the analog sensing value input from the sensing unit 17 into a digital sensing value and transmits the digital sensing value to the timing controller 11. Here, the sensing unit 17 may be connected to each of the reference lines 16 in a plurality of ways.

The scan driver circuit 13 supplies the scan lines 15 with a scan pulse (or gate pulse) synchronized with the data voltage output from the data driving circuit 12 during the vertical active period under the control of the timing controller 11 . The scan driver circuit 13 supplies the scan lines 15 with a scan pulse for sensing a change in electrical characteristics during the extended vertical blank period VB. The scan driver circuit 13 sequentially shifts the scan pulses during the vertical active period to sequentially select, on a line-by-line basis, pixels to which data of the input image is written. In addition, the scan driver circuit 13 can apply the scan pulse to the pixels whose electrical characteristic changes are to be sensed during the extended vertical blank period.

The timing controller 11 receives pixel data (DATA) and input timing signals of an input image from a host system (not shown). The input timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock DCLK, and the like. The timing controller 11 modulates an input timing control signal, for example, a data enable signal DE, which defines a vertical blank period to rearrange at least two or more vertical blank periods neighbely.

As a result, the present invention connects two or more vertical blanking periods. The timing controller 11 modulates the data enable signal DE, which is one of the input timing control signals, to define an extended vertical blank period and a modulation vertical active period. The timing controller 11 generates timing control signals DDC and GDC for controlling the operation timings of the data driving circuit 12 and the scan driving circuit 13 in accordance with the extended vertical blank period and the modulation vertical active period.

The host system may be implemented by any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The present invention increases the yield and lifetime of the organic light emitting diode display by applying an external compensation method that compensates the electrical characteristics of pixels using the timing controller 11 and the display panel driving circuits 12 and 13. [ In addition, the present invention can simplify the pixels as shown in FIG. 3 by omitting or minimizing the internal compensation circuit in the pixel by applying the external compensation method, thereby increasing the aperture ratio and yield of the pixel.

4 is a waveform diagram showing signals for sensing changes in electrical characteristics of a pixel.

Referring to FIGS. 3 and 4, the gate drive circuit 13 is connected to scan lines 15 (Scan A, Scan B, and Scan B) through the scan lines 15 during the extended vertical blank period under the control of the timing controller 11. ) To the pixels to be sensed. The electrical characteristic of the pixel represents at least one of the operating point voltage of the organic light emitting diode included in the pixels, the threshold voltage of the driving TFT included in the pixels, and the electric mobility of the driving TFT included in the pixels.

The data driving circuit 12 supplies the data lines 14 with a predetermined data voltage for sensing in order to sense the electrical characteristics of the pixels during the extended vertical blank period. The sensing data voltage is a voltage set to a predetermined voltage regardless of the data voltage of the input image.

The gate-source voltage of the second TFT T2 is set to a constant level during the initialization period in which the first and second scan pulses Scan A and Scan B are applied at the ON level. The third TFT T3 is turned on in response to the second scan pulse Scan B to connect the second and third nodes B and C at the sensing time subsequent to the initialization period. The voltage of the second node B at the sensing time can be changed by the current flowing in the second TFT T2. The voltage of the second node B is applied to the sensing unit through the third TFT T3 and the reference line 16 at the sensing time. The ADC converts the voltage change of the second node (B) to a digital value during the sensing time. The electrical characteristics of these pixels are transmitted to the timing controller 11.

5 is a waveform diagram showing a comparison between a display timing according to an input timing signal and a display timing reset according to the present invention.

Referring to FIG. 5, one frame period defined by the input timing signal is divided into a vertical active period AA and a vertical blank period VB.

The data enable signal DE is synchronized with the data of the input image. One pulse period of the data enable signal DE is one horizontal period, and the high logic period of the data enable signal DE, that is, the pulse width represents one line data timing. One horizontal period is the horizontal address time required to write data to pixels of one line in the display panel 10. [

The data of the input image is input during the vertical active period AA and not input to the vertical blank period VB. The data enable period AA is a time required for displaying one frame of pixel data in all the pixels of the pixel array (vertical address time).

The vertical blanking period VB includes a vertical sync period VS, a vertical front porch FP and a vertical back porch BP. The vertical sync period VS is the time from the polling edge to the rising edge of Vsync, and represents the start (or end) timing of one screen.

The vertical front porch (FP) is the time from the falling edge of the last pulse of the data enable signal (DE) to the falling edge of Vsync. The vertical back porch BP is the time from the rising edge of Vsync to the rising edge of the first pulse of the data enable signal DE.

5, one frame period defined by the modulated input timing signal in the present invention includes a modulation vertical active period AA ', or a modulation vertical active period AA' and at least two And a vertical blank period VB 'that is continuously rearranged.

The extended vertical blanking period is a period in which at least two vertical blanking periods VB 'are adjacently connected, and the modulated data enable signal DE' is an internal data enable signal regenerated by the timing controller 11.

FIG. 6 is a block diagram illustrating a timing controller according to an exemplary embodiment of the present invention. FIGS. 7 and 8 illustrate a vertical blanking period according to an exemplary embodiment of the present invention.

6 to 8, the timing controller 11 of the present invention includes a frame memory 11a, a DE modulator 11b, and a luminance compensator 11c. The timing controller 11 continuously rearranges the vertical blank periods to sufficiently ensure a sensing time required to sense the electrical characteristics of the pixels.

A frame memory 11a receives pixel data DATA and input timing signals of an input image from a host system (not shown). The frame memory 11a writes pixel data (DATA) of the input image according to input timing signals. The frame memory 11a reads out the pixel data DATA of the stored image in synchronization with the modulated data enable signal DE '.

The DE modulator 11b receives input timing signals from a host system (not shown). The DE modulating unit 11b receives the input timing signals and checks the position occupied by the vertical blanking period VB 'in each frame. Then, the DE modulating unit 11b modulates the vertical blanking period VB' so that at least two vertical blanking periods VB ' Thereby modulating the Able signal.

The luminance compensation unit 11c receives pixel data DATA of an image from a frame memory 11a and at least two vertical blanking periods VB are neighbely rearranged from the DE modulation unit 11b Information on a frame is received and a luminance deviation generated due to a difference of an emission period between frames according to the presence or absence of a vertical blank period is compensated. The luminance compensating unit 11c compensates for the difference between the emission period of the first frame Frame1 that does not include the extended vertical blanking period VB1 and the emission period of the second frame Frame2 including the extended vertical blanking period VB ' And generates different gains corresponding to the first frame (Frame 1) and the second frame (Frame 2) in order to compensate for the luminance deviation caused by the period difference. The luminance compensating unit 11c compensates for the difference between the emission period of the first frame Frame1 that does not include the extended vertical blanking period VB1 and the emission period of the second frame Frame2 including the extended vertical blanking period VB ' The gain generated by the time difference is applied to the pixel data (DATA ') of the modulated input image to be displayed in the corresponding frame. A detailed description of the luminance compensation unit 11c for generating different gains corresponding to the first frame (Frame1) and the second frame (Frame2) will be described later with reference to FIG. 11 and FIG.

The timing controller 11 arranges the extended vertical blanking period every N (N is a positive integer equal to or larger than 2) frames. For example, if an extended vertical blanking period is arranged every two frames, the first frame includes a first modulated vertical active period AA'1 and the second frame comprises a second modulated vertical active period AA'2, And an extended vertical blanking period VB'1 + VB'2, and the third frame includes a third modulated vertical active period AA'3. The timing controller 11 outputs a first vertical blanking period VB'1 arranged between the first modulation vertical active period AA'1 and the second modulation vertical active period AA'2 to the modulated data enable Can be rearranged between the second modulation vertical active period AA'2 and the third modulation vertical active period AA'3 in accordance with the signal DE '. The first vertical blanking period VB'1 is skipped between the first modulation vertical active period AA'1 and the second modulation vertical active period AA'2. Accordingly, the first modulated vertical active period AA'1 and the second modulated vertical active period AA'2 are continuously arranged. The first vertical blanking period VB'1 and the second vertical blanking period VB'2 are continuously arranged between the second modulated vertical active period AA'2 and the third modulated vertical active period AA'3 do. That is, between the second modulation vertical active period AA'2 and the third modulation vertical active period AA'3, the first vertical blanking period VB'1 and the second vertical blanking period VB'2 are adjacent to each other The extended vertical blanking period VB'1 + VB'2 is arranged.

The timing controller 11 outputs the pixel data DATA of the input image stored in the frame memory 11a in synchronization with the modulated data enable signal DE '. The timing controller 11 transmits the pixel data DATA 'of the input image modulated in synchronization with the modulated data enable signal DE' to the data driving circuit 12.

As described above, according to the present invention, the extended vertical blanking period is set for every N frames on the basis of the modulated data enable signal DE ', thereby sufficiently securing the insufficient sensing time.

Referring to FIG. 9, the timing controller 11 disposes the extended vertical blanking period every three frames. The first frame Frame 1 includes a first modulated vertical active period AA'1, the second frame Frame 2 includes a second modulated vertical active period AA'2, Includes a third modulated vertical active period AA'3 and an extended vertical blanking period VB'1 + VB'2 + VB'3.

The present invention provides three vertical blanking periods (VB'1 to VB'3) arranged in a first modulated vertical active period (AA'1) to a third modulated vertical active period (AA'3) with a modulated data enable signal Can be rearranged between the third modulation vertical active period (AA '3) and the fourth modulation vertical active period (not shown) in accordance with the first modulation dead angle (DE'). Accordingly, the first modulation vertical active period AA'1 and the second modulation vertical active period AA'2 and the second modulation vertical active period AA'2 and the third modulation vertical active period AA ' 3, the first and second vertical blanking periods VB'1 and VB'2 are skipped. As a result, the first modulation vertical active periods AA'1 to the third modulation vertical active periods AA'3 are successively arranged. The first vertical blanking period VB'1 to the third vertical blanking period VB'3 are successively arranged between the third modulation vertical active period AA'3 and the fourth modulation vertical active period . That is, between the third modulation vertical active period (AA'3) and the fourth modulation vertical active period (not shown), the first vertical blank period (VB'1) to the third vertical blank period (VB'3) The rearranged extended vertical blanking periods VB'1 + VB'2 + VB'3 are arranged. Herein, the extended vertical blanking period VB'1 + VB'2 + VB'3 includes the first vertical blanking period VB'1, the second vertical blanking period VB'2, and the third vertical blanking period VB'3 ) Are substantially the same period.

By extending the number of vertical blanking periods that are continuously rearranged by the present invention, the sensing time can be more sufficiently secured.

As described so far, the present invention modulates a data enable signal to rearrange at least two vertical blanking periods when an extended vertical blanking period and a modulation vertical active period are defined. Thus, N vertical blanking periods are rearranged next to each other in N frames to implement the extended vertical blanking period.

Although the timing controller 11 described above includes one frame memory 11a, the present invention is not limited thereto. The timing controller 11 may include a plurality of frame memories 11a. The frame memory 11a stores the input digital video data for image display in synchronism with the input timing signal and then supplies the input digital video data to the modulation timing signal (i.e., the modulation data enable signal DE ') during the modulation vertical active period. To the data driving circuit 12. [ The frame memory 11a may be implemented as a double data rate synchronous dynamic random access memory (DDR SDRAM). One or more frame memories 11a may be provided in the timing controller 11. For example, when only one frame memory 11a is provided, the maximum number of vertical blanking periods that are continuously rearranged may be 1079 based on Full High Definition (FHD). The present invention is not limited to this, and the maximum number of vertical blanking periods that are continuously rearranged when one or more frame memories 11a are provided may be 1079 or more.

FIG. 10 is a diagram illustrating that an inter-frame emission period varies while an extended vertical blanking period is implemented for every N frames, and FIG. 11 is a flowchart showing compensation of a luminance deviation caused by a difference of inter- , And FIG. 12 is a flowchart for generating a gain for compensating for the luminance deviation caused by the difference of the inter-frame emission periods.

10 shows an A frame and a C frame including an extended vertical blanking period and a B frame not including an extended vertical blanking period.

10 to 12, an A frame including an extended vertical blanking period (VB'a), a B frame including no extended vertical blanking period, and a C frame including an extended vertical blanking period (VB'c) . Here, the extended vertical blanking period VB'a is skipped without being inserted between the B frame and the C frame.

The emission time period is a period during which the OLED emits light sequentially for each of the lines to display an input image. In the A frame including the extended vertical blanking period VB'a, the first emission time period is longer than the second emission time period which does not include the extended vertical blanking period.

In this manner, if an extended vertical blanking period is implemented for every N (N is a natural number) frame, an emission period is different between a frame including the extended vertical blanking period and a frame including no extended vertical blanking period. When the emission time is changed, a flicker occurs on the screen.

As shown in Fig. 10, the timing controller 11 controls the timing of the first emission period (first emission period) of the A frame including the extended vertical blank period and the second emission period (second emission period) of the B frame not including the extended vertical blank period And generates different gains corresponding to the A frame and the B frame in order to compensate for the luminance deviation caused by the difference in the second emission time. The luminance compensating unit 11c of the timing controller 11 compares the gain generated by the difference between the first emission period and the second emission period to the input digital video data .

As shown in Fig. 11, the timing controller 11 can check the position and temporal length of the extended vertical blanking period based on the modulation data enable signal (S110). The timing controller 11 can check the temporal position and the temporal length of the frame in which the extended vertical blanking period is arranged, so that the emission period of the corresponding frame can be known. Accordingly, the timing controller 11 individually generates the gains corresponding to the A frames including the extended vertical blanking period and the B frames not including the extended vertical blanking period (S120). In order to compensate for the luminance deviation caused by the difference of the emission period between the A frame including the extended vertical blanking period and the B frame not including the extended vertical blanking period, the timing controller 11 outputs, for each input digital video data, The generated gains are individually applied (S130).

A method of separately generating the gains corresponding to the A frame including the extended vertical blank period and the B frame not including the extended vertical blank period will be described below with reference to FIG.

Referring to FIGS. 10 and 12, a first emission time period and a second emission time period sequentially emit light for each line to display an input image.

As shown in FIGS. 10 and 12, the first emission time period necessarily includes an extended vertical blank period because the light emission is sequentially performed line by line in the A frame.

In the first line of the A frame, the extended vertical blanking period is arranged at the end of the first emission time period. In the nth line of the A frame, the extended vertical blanking period is arranged in the front part of the first emission time. On the other hand, as shown in FIG. 10, the second emission period (Second Emission Time) does not include the extended vertical blank period because it sequentially emits light for each line in the B frame. For example, the first emission period corresponding to the A frame includes the extended vertical blank period 600us (one vertical blank period is 300us). Accordingly, the total duration of the first emission time corresponding to the A frame is 8.9 ms. On the other hand, the second emission period corresponding to the B frame does not include the extended vertical blank period 600us (one vertical blank period is 300us). Thus, the total duration of the second emission time period corresponding to the B frame is 8.3 ms.

In this manner, since the emission period is longer than the period including the extended vertical blank period, the second emission period is realized to be shorter than the first emission period (S121).

As the first emission time is longer than the second emission time, the brightness of the A frame becomes brighter than the brightness of the B frame (S122).

Since the brightness of the A frame is different from the brightness of the B frame, the timing controller 11 determines that the first gain corresponding to the pixel data of the input image to be displayed in the A frame and the second gain corresponding to the pixel data of the input image to be displayed on the B frame Generate the gains differently. The timing controller 11 can generate the first gain and the second gain using the luminance compensation unit 11c (S123).

The first gain calculated by dividing the gain corresponding to the emission period of 8.9 ms to the reference gain is applied to the pixel data of the input image supplied to the A frame (1st frame), while the input supplied to the B frame (2nd Frame) The second gain calculated by dividing the gain corresponding to the emission period of 8.3 ms to the reference gain can be applied to the pixel data of the image (S123). Here, the second gain may be larger than the first gain.

The timing controller differentially applies the generated first gain and second gain to digital video data to be displayed in the A frame and digital video data to be displayed in the B frame, respectively. Accordingly, the brightness deviation due to the difference between the first emission time of the A frame and the second emission time of the B frame can be relaxed (S124).

The present invention computes the generated gain and the digital video data of the frame to compensate for the luminance deviation according to the difference of the emission period so that the brightness of the first frame and the brightness of the second frame are substantially equal can do. Therefore, it is possible to efficiently remove the flicker due to the luminance difference between the frames.

Also, in the present invention, the brightness difference of a specific sensing line (Sensing Line) can remove the perception through a random sensing method. Such a random sensing method is fully known through the identification numbers [0034] to [0040] and FIG. 5 of the application No. 10-2013-0166678 filed in 2013 of the present application, and a detailed description thereof will be omitted .

The present invention described so far modulates an input timing control signal defining a vertical blank period to rearrange at least two or more vertical blank periods neighbely, and the simulation result is as shown in FIG.

Referring to FIG. 13, a conventional frame is shown at the top, and a frame according to the present invention is shown at the bottom.

Conventional first to fifth frames include vertical blank periods every frame. Accordingly, each of the first to fifth frames in the related art is implemented so that the emission period is substantially the same. On the other hand, the extended vertical blanking period is arranged in the first frame, the third frame and the fifth frame, and the extended vertical blanking period is not arranged in the second frame and the fourth frame. Accordingly, the emission period of the first frame, the third frame, and the fifth frame of the present invention is longer than the emission period of the second frame and the fourth frame.

Since the vertical blanking periods are extended to sufficiently secure the sensing time, the present invention enables real-time sensing. As described above, by sufficiently securing the sensing time, the compensation performance can be improved and the lifetime of the panel can be increased.

Further, since the present invention can secure a sufficient sensing time, it is possible to sense the electrical characteristics of a pixel even at a low gradation with a low pixel current, and it is possible to provide a high resolution, . As a result, the present invention can be effectively applied to a high resolution, fixed three organic light emitting display.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
11a: frame memory 11b: DE modulation section
11c: luminance compensation unit 12: data driving circuit
13: Scan driving circuit

Claims (7)

A display panel having a plurality of pixels;
A timing controller for modulating an input timing control signal in which a vertical blank period is defined to set an extended vertical blank period by rearranging at least two vertical blank periods neighbely; And
And a display panel driving circuit driving signal lines of the display panel within the extended vertical blank period to sense electrical characteristics of the pixels. The method according to claim 1,
Wherein the extended vertical blanking period is arranged for every N (N is a positive integer equal to or larger than two) frames. The method according to claim 1,
The input timing control signal indicating a data enable signal,
Wherein the timing controller modulates the data enable signal to define the extended vertical blank period and the modulation vertical active period. The method of claim 3,
(N is a positive integer equal to or greater than 2) are successively arranged in sequence, and the extended vertical blank period is also N (N is a positive integer not less than 2) Display device. The method according to claim 1,
Wherein the timing controller further comprises a frame memory for storing input digital video data for image display and outputting the input digital video data to the display panel driving circuit during the modulation vertical active period. The method according to claim 1,
Wherein the electrical characteristics of the pixel indicate at least one of an operating point voltage of the organic light emitting diode included in the pixels, a threshold voltage of the driving TFT included in the pixels, and an electric mobility of the driving TFT included in the pixels The organic light emitting diode display device. The method according to claim 1,
Wherein the timing controller compensates for luminance by varying a gain between a frame in which the extended vertical blanking period is arranged and a frame in which the extended vertical blanking period is skipped.

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