KR20140028611A - Semiconductor integrated circuit apparatus - Google Patents

Semiconductor integrated circuit apparatus Download PDF

Info

Publication number
KR20140028611A
KR20140028611A KR1020120095212A KR20120095212A KR20140028611A KR 20140028611 A KR20140028611 A KR 20140028611A KR 1020120095212 A KR1020120095212 A KR 1020120095212A KR 20120095212 A KR20120095212 A KR 20120095212A KR 20140028611 A KR20140028611 A KR 20140028611A
Authority
KR
South Korea
Prior art keywords
sense amplifier
amplifier region
gate
conductive line
nmos transistor
Prior art date
Application number
KR1020120095212A
Other languages
Korean (ko)
Inventor
천덕수
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120095212A priority Critical patent/KR20140028611A/en
Publication of KR20140028611A publication Critical patent/KR20140028611A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Abstract

A semiconductor integrated circuit device comprises: a first sense amplifier region and a second sense amplifier region placed adjacent in a row direction; and a PMOS transistor and an NMOS transistor which are formed in the first and the second sense amplifier region, respectively, and are sequentially arranged in a column direction perpendicular to the row direction. A PMOS transistor gate of the first sense amplifier region and an NMOS transistor gate of the second sense amplifier region include gate extension portions, respectively.

Description

Semiconductor Integrated Circuit Apparatus

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor memory device including a latch block.

The semiconductor memory device is provided with a sense amplifier to detect the state of the stored data. These sense amplifiers depend on fast sensing, fast data driving and low leakage current.

In addition, at present, as the integration density increases, the semiconductor memory device is layered into not only a bit line pair but also a global input / output line pair and a local input / output line pair, and a sense amplifier may be provided between upper and lower input / output line pairs. . The sense amplifier generally includes a latch block, and the general latch block has a configuration as shown in FIG.

Referring to FIG. 1, the latch block 10 includes first and second PMOS transistors P1 and P2 and first and second connected between a bit line (BL) and a bit line bar (hereinafter, / BLB). 2 NMOS transistors N1 and N2.

The gate of the first PMOS transistor P1 is connected to the gate and / BL of the first NMOS transistor N1, and the gate of the second PMOS transistor P2 is connected to the gate and BL of the second NMOS transistor N2. .

The latch block of the sense amplifier may be provided for each column, and in order to improve the integration density, the latch block of the sense amplifier may be disposed symmetrically with the latch block of the adjacent column.

However, when the latch blocks are arranged symmetrically with each column as described above, the bit lines and the metal wires having the same function are also arranged to face symmetrically. For this reason, there exists a problem that coupling capacitance increases.

Accordingly, the present invention is to provide a semiconductor integrated circuit device capable of reducing the coupling capacitance.

A semiconductor integrated circuit device according to an embodiment of the present invention is formed in each of the first sense amplifier region and the second sense amplifier region, and the first and second sense amplifier regions, which are disposed adjacent to each other in the row direction. And a PMOS transistor and an NMOS transistor sequentially arranged in a column direction perpendicular to each other, wherein the PMOS transistor gate of the first sense amplifier region and the NMOS transistor gate of the second sense amplifier region each include a gate extension.

In addition, a semiconductor integrated circuit device according to another exemplary embodiment of the present invention may include a first sense amplifier region including a first PMOS transistor and a first NMOS transistor sequentially disposed in a column direction, the first sense amplifier region, and a row direction. And a second sense amplifier region including a second PMOS transistor disposed adjacent to the first PMOS transistor, the second PMOS transistor disposed substantially corresponding to the first PMOS transistor, and a second NMOS transistor disposed substantially corresponding to the first NMOS transistor. A second sense amplifier region, a first gate extension part connected to the gate of the first PMOS transistor and extending toward the first NMOS transistor, and a second connected to the gate of the second NMOS transistor and extending toward the second PMOS transistor A gate extension, a source of the first PMOS transistor, and the first NMOS transistor A first conductive line connecting between the gates of the master, a second conductive line connecting the first gate extension and a drain of the first NMOS transistor, and connecting the source of the second PMOS transistor and the second gate extension; And a fourth conductive line connecting the gate of the second PMOS transistor and the drain of the second NMOS transistor.

According to this embodiment, in forming the latch circuit portion of the sense amplifier, an extension portion is selectively provided in the gate of the PMOS transistor and the gate of the NMOS transistor. As a result, the length of the conductive line connecting the transistor elements can be reduced, thereby reducing the coupling capacitance.

1 is a circuit diagram illustrating a latch block of a general sense amplifier.
FIG. 2 is a schematic layout diagram illustrating arrangement of transistors constituting a latch block of a sense amplifier according to an exemplary embodiment of the present invention.
3 is an enlarged layout view of a part of the latch block of FIG. 2.
FIG. 4 is a layout diagram illustrating only the gate structure of FIG. 3.
5 is a layout diagram illustrating a part of a general latch block.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments are to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to fully understand the present invention, the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

Referring to FIG. 2, the semiconductor memory device may include a plurality of mats MAT_up and MAT_dn, and each of the mats MAT_up and MAT_dn is a plurality of word lines (not shown) and a plurality of bits that are cross-aligned. Lines BLn-1, BLn, BLn + 1, BLn + 2, / BLn-1, / BLn, / BLn + 1, / BLn + 2.

The plurality of sense amplifiers are disposed in a space between the upper mat MAT_up and the lower mat MAT_dn. The plurality of sense amplifiers are provided with a plurality of bit lines BLn-1, BLn, BLn + 1, and BLn + 2 from the upper mat MAT_up to take the form of an open bit line sense amplifier, and from the lower mat MAT_dn. A plurality of bit line bars (/ BLn-1, / BLn, / BLn + 1, / BLn + 2) are provided.

Each unit sense amplifier may be provided for each bit line pair, and in the present embodiment, n-1 to n + 2 sense amplifiers will be described as an example.

The nth sense amplifier S / An may be disposed between the nth bit line BLn of the upper mat MAT_up and the nth bit line bar / BLn of the lower mat MAT_dn. The nth sense amplifier S / An may include a latch block as described above.

In the nth sense amplifier S / An, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 are sequentially arranged along the y direction of the drawing. Can be integrated.

In addition, the n-th sense amplifier S / An-1 may be located below the y-direction of the n-th sense amplifier S / An, and the n-1th sense amplifier S / An-1 is formed of The n sense amplifier S / An may be arranged to have fold symmetry with respect to the x axis.

The n + 1th sense amplifier S / An + 1 may be disposed adjacent to the nth sense amplifier S / An in the x direction and symmetrical with respect to the y direction. The n + 2th sense amplifier S / An + 2 is located below the y direction of the n + 1th sense amplifier S / An + 1, similarly to the n-1th sense amplifier S / An-1. Can be.

3 is a detailed layout diagram illustrating a part of the latch block 300 in FIG. 2. In FIG. 3, the second PMOS transistor P2 and the first NMOS transistor N1 are enlarged in the nth and n + 1 sense amplifier regions S / An and S / An + 1: 300 of FIG. 2. It was. However, in order to explain the layout relationship and the symmetrical relationship between the elements, FIG. 3 further illustrates an n + m sense amplifier region adjacent to the other side of the n + 1 sense amplifier region.

Referring to FIG. 3, an nth sense amplifier region S / An, an n + 1 sense amplifier region S / An + 1, and an n + m sense amplifier region S are formed on a semiconductor substrate (not shown). / An + m) is limited. The n, n + 1 and n + m sense amplifier areas S / An, S / An + 1 and S / An + m may correspond to circuit areas between the mats, which are adjacent in the x direction. Can be arranged.

In each of the nth, n + 1th and nth + m sense amplifier areas S / An, S / An + 1, S / An + m, the second PMOS transistor P2 is active along the y direction of the drawing. Regions 100a (hereinafter, first active region) and active regions 100b (hereinafter, second active region) of the first NMOS transistor N1 are formed.

In each of the nth, n + 1 and n + m sense amplifier areas S / An, S / An + 1, S / An + m, the first active area 100a and the second active area 100b are respectively provided. A gate Gp2 of the second PMOS transistor P2 and a gate Gn1 of the first NMOS transistor N1 are formed to pass through the upper portion.

Here, the gate structure will be described in more detail with reference to FIG. 4. For reference, FIG. 4 will only show the gate structures of the n-th and n-th sense regions S / An and S / An + 1.

Referring to FIG. 4, the second PMOS transistor P2 gate Gp2 of the nth sense amplifier region S / An may include a first PMOS main gate 120a-1 and a gate extension 125. have. The first PMOS main gate 120a-1 may have a substantially “C” structure, and the gate extension portion 125 may move in the y direction (ie, from the first PMOS main gate 120a-1). Extending to the first NMOS transistor of the nth sense amplifier), and may be designed to have at least one bent portion 127.

The first NMOS transistor N1 gate Gn1 of the nth sense amplifier S / An may be configured as a first NMOS main gate 120b-1. The first NMOS main gate 120b-1 may also have a substantially letter “C” structure and may be disposed to be rotated 180 ° with respect to the structure of the first PMOS main gate 120a-1.

In an n + 1 sense amplifier S / An + 1 positioned in a column adjacent to the nth sense amplifier S / An, the second PMOS transistor P2 gate Gp2 'is a second PMOS main gate. And 120a-2. The second PMOS main gate 120a-2 is rotated 180 ° with respect to the first PMOS main gate 120a-1 and is disposed to face the first PMOS main gate 120a-1.

In addition, the gate Gn2 ′ of the first NMOS transistor N1 of the n + 1th sense amplifier S / An + 1 includes the second NMOS main gate 120b-2 and the second NMOS main gate 120b-2. ) And a gate extension 125 '. The gate extension 125 ′ is toward the second PMOS main gate 120b-2 to have at least one bent portion 127 similarly to the gate extension 125 of the nth sense amplifier S / An. Can be extended. The second NMOS main gate 120b-2 may be rotated 180 ° with respect to the first NMOS main gate 120b-1, and may be disposed to face the first NMOS main gate 120b-1. have. However, except for an example in which the gates of the transistor disclosed herein include gate extension parts 125 and 125 ′, the shape and direction thereof may be variously considered.

That is, in the present exemplary embodiment, the gate extension of the gate Pp2 of the second PMOS transistor P2 is in one sense amplifier area S / An of two adjacent sense amplifier areas S / An and S / An + 1. The part 125 is provided, and the gate extension part 125 'is provided in the gate Gn1' of the first NMOS transistor N1 in the other sense amplifier area S / An + 1.

Accordingly, when compared with the adjacent sense amplifier regions, the structure of the transistor having the same function, preferably the gate structure of the transistor, does not have the folded symmetry as before, and has a substantially diagonal symmetry.

3, between the source of the second PMOS transistor P2 and the gate Gn1 of the first NMOS transistor in each sense amplifier region S / An, S / An + 1, S / An + m. First conductive lines 130a and 130a 'are formed to connect the second conductive lines 130a and 130a' to connect the drains of the first NMOS transistor N1 and the gates Gp2 and Gp2 'of the second PMOS transistor P2. 130b and 130b 'are formed.

In addition, in order to achieve a latch structure of the sense amplifier, the bit lines BLn are connected to the second PMOS transistor P2 gates Gp2 and Gp2 'in the sense amplifier regions S / An and S / An + 1. And BLn + 1 are disposed, and bit line bars / BLn and / BLn + 1 are connected to gates Gn1 and Gn1 'of the first NMOS transistor N1, respectively.

The first and second conductive lines 130a, 130a ', 130b, and 130b', the bit lines BLn and BLn + 2, and the bit line bars BLBn and BLBn + 2 are all disposed on the same plane. The metal lines may have a structure in which the gates and the insulating layer are stacked therebetween.

Here, reference numeral 100c denotes an n well pick-up area for supplying power to the n well 101, and 100d indicates a p well pick-up area for supplying power to the p well 102. In addition, reference numeral 150 denotes a shielding line electrically connected to the n-well pick-up region 100c and the p-well pick-up region 100d, and CT denotes an electrical connection region.

In this case, the shielding line 150 is located in a region where the wiring density is relatively low, and is provided to reduce the inter-line coupling facing each other.

In the related art, as illustrated in FIG. 5, the gates gp2 and gn1 of the transistors in the adjacent sense amplifier regions are formed to be substantially symmetrical. In this case, the conductive lines 13a and 13b electrically connecting the transistors P2 and N1 are also symmetrical. For this reason, there existed a problem that the area which the conductive lines 13a and 13b face is increased, and coupling capacitance increases.

However, in the present embodiment, as described above, when the gates of the transistors formed in the adjacent sense amplifier regions are asymmetrically configured, that is, when the gate extension units are alternately provided for each sense amplifier region, the sense functions the same. The conductive lines of the amplifier differ in length by sense amplifier area.

That is, the first conductive line 130a of the nth sense amplifier region S / An has a general length, but the first conductive line 130a 'of the n + 1 sense amplifier region S / An + 1 has a general length. The gate tension portion 125 ′ connected to the first NMOS main gate 120b-2 of the n + 1 sense amplifier region S / An + 1 has a length shorter than that of the first conductive line 130a. .

Therefore, the first conductive line 130a of the nth sense amplifier region S / An and the first conductive line 130a 'of the n + 1th sense amplifier region S / An + 1 have the same front surface as before. You will not face. As a result, the wiring margin of the n + 1 sense amplifier region S / An + 1 facing the first conductive line 130a is relatively improved, and the shielding line 150 is disposed at the portion where the wiring margin is improved. ) Can be installed more.

Similarly, although the second conductive line 130b 'of the n + 1th sense amplifier region S / An + 1 has a general length, the nth and n + m sense amplifier regions S / An, S / An + The second conductive line 130b of m) may be connected to a gate tension portion connected to the second PMOS main gate 120a-1 of the nth and n + m sense amplifier regions S / An and S / An + m. 125 may have a length shorter than that of the second conductive line 130b '.

Therefore, the second conductive line 130b of the n + 1 sense amplifier region S / An and the second conductive line 130b 'of the n + m sense amplifier region S / An + m are the same as before. The front will not face. As a result, the wiring margin of the n + 3 sense amplifier region S / An + m facing the second conductive line 130b 'is relatively improved. 150) can be installed more.

That is, in the present exemplary embodiment, gate extension portions may be alternately provided to transistors in adjacent sense regions, and thus the length of the conductive lines may be selectively reduced based on the length of the gate extension portion.

As a result, the facing sections of the conductive lines 130a, 130a ', 130b, and 130b' having the same function can be reduced, thereby reducing the coupling capacitance. In addition, by reducing the length of the conductive lines 130a, 130a ', 130b, and 130b', the metal shielding line 150 may be further disposed in a space where wiring margin is improved, thereby further reducing the coupling phenomenon. Can be.

As described in detail above, according to the present embodiment, an extension portion is selectively provided in the gate of the PMOS transistor and the gate of the NMOS transistor in configuring the latch circuit portion of the sense amplifier. As a result, the length of the conductive line connecting the transistor elements can be reduced, thereby reducing the coupling capacitance.

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that it can be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100a: PMOS active area 100b: NMOS active area
100c: n-well pick-up area 100d: p-well pick-up area
101: n well 102: p well
120a-1,120a-2: main gate of second PMOS transistor
120b-1,120b-2: main gate of first NMOS transistor
130a, 130a: 130: conductive line

Claims (16)

A first sense amplifier region and a second sense amplifier region disposed adjacent in the row direction; And
A PMOS transistor and an NMOS transistor formed in each of the first and second sense amplifier regions and sequentially arranged in a column direction perpendicular to the row direction;
And the PMOS transistor gate of the first sense amplifier region and the NMOS transistor gate of the second sense amplifier region each include a gate extension portion. The method of claim 1,
The PMOS transistors in the first sense amplifier region are arranged to face each other with the PMOS transistors in the second sense amplifier region,
And the NMOS transistor of the first sense amplifier region is disposed to face the NMOS transistor of the second sense amplifier. 3. The method of claim 2,
And the gate extension portion of the first sense amplifier region extends toward the NMOS transistor of the first sense amplifier region. 3. The method of claim 2,
And the gate extension of the second sense amplifier region extends toward the PMOS transistor of the second sense amplifier region. The method of claim 1,
Each of the first and second sense amplifier regions,
A first conductive line connecting between the source of the PMOS transistor and the gate of the NMOS transistor; And
And a second conductive line connecting the gate of the PMOS transistor and the drain of the NMOS transistor. The method of claim 5, wherein
The first conductive line of the second sense amplifier region is connected to the source of the PMOS transistor of the second sense amplifier region and the gate extension of the NMOS transistor of the second sense amplifier region, so that the first sense line of the first sense amplifier region A semiconductor integrated circuit device having a length different from that of the first conductive line. The method of claim 5, wherein
The second conductive line of the first sense amplifier region is connected with the gate extension of the PMOS transistor of the first sense amplifier region and the drain of the NMOS transistor of the first sense amplifier region, thereby providing the second sense amplifier region. 12. A semiconductor integrated circuit device having a length different from that of a second conductive line. The method of claim 7, wherein
A first conductive line of the first sense amplifier region and a first conductive line of the second sense amplifier region are disposed to face each other,
And a second conductive line of the first sense amplifier region and a second conductive line of the second sense amplifier region face each other. The method of claim 8,
And a shielding line is further formed in the line clearance space caused by the length difference between the first conductive lines and the length difference between the second conductive lines. A first sense amplifier region including a first PMOS transistor and a first NMOS transistor sequentially arranged in a column direction;
A second PMOS transistor disposed adjacent to the first sense amplifier region in a row direction, the second PMOS transistor disposed to substantially correspond to the first PMOS transistor, and a second NMOS transistor disposed to substantially correspond to the first NMOS transistor; A second sense amplifier region including a second sense amplifier region;
A first gate extension connected to the gate of the first PMOS transistor and extending toward the first NMOS transistor;
A second gate extension connected to the gate of the second NMOS transistor and extending toward the second PMOS transistor;
A first conductive line connecting between the source of the first PMOS transistor and the gate of the first NMOS transistor;
A second conductive line connecting the first gate extension and a drain of the first NMOS transistor;
A third conductive line connecting the source of the second PMOS transistor and the second gate extension; And
And a fourth conductive line connecting the gate of the second PMOS transistor and the drain of the second NMOS transistor. 11. The method of claim 10,
And the first conductive line and the third conductive line are disposed to substantially face each other, wherein the length of the third conductive line is shorter than the length of the first conductive line. The method of claim 11,
And a shielding line disposed in the second sense amplifier region so as to face the first conductive line. 11. The method of claim 10,
And the second conductive line and the fourth conductive line are disposed to substantially face each other, wherein the length of the second conductive line is shorter than the length of the fourth conductive line. 14. The method of claim 13,
And a shielding line disposed in the first sense amplifier region so as to face the second conductive line. A first sense amplifier region and a second sense amplifier region disposed adjacent in the row direction; And
A PMOS transistor and an NMOS transistor formed in each of the first and second sense amplifier regions and sequentially arranged in a column direction perpendicular to the row direction;
The PMOS transistor of the first sense amplifier region is arranged symmetrically with the NMOS transistor of the second sense amplifier region,
The NMOS transistor of the first sense amplifier region is disposed symmetrically with the PMOS transistor of the second sense amplifier region.
The PMOS transistor gate of the first sense amplifier region and the NMOS transistor gate of the second sense amplifier region each include a gate extension. The method of claim 15,
The PMOS transistor gate of the first sense amplifier region and the NMOS transistor gate of the second sense amplifier region further include a gate extension part extending by a predetermined length toward another transistor of the sense amplifier region.
KR1020120095212A 2012-08-29 2012-08-29 Semiconductor integrated circuit apparatus KR20140028611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120095212A KR20140028611A (en) 2012-08-29 2012-08-29 Semiconductor integrated circuit apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120095212A KR20140028611A (en) 2012-08-29 2012-08-29 Semiconductor integrated circuit apparatus

Publications (1)

Publication Number Publication Date
KR20140028611A true KR20140028611A (en) 2014-03-10

Family

ID=50641982

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120095212A KR20140028611A (en) 2012-08-29 2012-08-29 Semiconductor integrated circuit apparatus

Country Status (1)

Country Link
KR (1) KR20140028611A (en)

Similar Documents

Publication Publication Date Title
US10636458B2 (en) Sense amplifier layout for FinFET technology
JP2002118172A (en) Basic cell, integrated circuit layout section, integrated circuit layout, integrated circuit device and method for designing signal line of integrated circuit
TWI533321B (en) Semiconductor integrated circuit device
US8884349B2 (en) Semiconductor device
JP2009094201A (en) Semiconductor integrated circuit device
US9406352B2 (en) Semiconductor memory with sense amplifier
JP4623885B2 (en) Semiconductor memory device
US8507994B2 (en) Semiconductor device
KR101223539B1 (en) Semiconductor Integrated Circuit Device
US20070267760A1 (en) Semiconductor apparatus
JP5653001B2 (en) Semiconductor device and method of arranging compensation capacitance of semiconductor device
JP2009033099A (en) Semiconductor memory device
JP6390299B2 (en) Integrated circuit device design method, integrated circuit device manufacturing method, and integrated circuit device
KR20140028611A (en) Semiconductor integrated circuit apparatus
JPH1041393A (en) Semiconductor standard cell and method for layout and wiring
KR101086883B1 (en) Semiconductor memory apparatus having sense amplifier
JP2002343939A (en) Layout method of sense amplifier for semiconductor memory element, and semiconductor memory element using the method
KR20120004711A (en) Semiconductor memory device
US9406663B2 (en) Semiconductor devices
KR101788726B1 (en) Semicomductor Memory Apparatus having shielding patterns
JP4583326B2 (en) Semiconductor device
JP5715716B2 (en) Semiconductor memory device
JP2016046479A (en) Semiconductor device, semiconductor device design method and program
JP4441541B2 (en) Semiconductor device
KR20110012691A (en) Method for forming an unit block circuit in a semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination