KR20140020946A - Solid-state imaging element and imaging device - Google Patents

Abstract

Provided is a stacked solid-state imaging device that does not fail even when excessive light is incident.
The solid-state imaging device 100 includes a plurality of pixels 101 including a photoelectric conversion unit P above the substrate 10 and a circuit S for reading a signal corresponding to a charge generated in the photoelectric conversion unit P. Have The circuit S includes a charge accumulation unit 10 formed in the substrate 10 and in which holes moved to the pixel electrode 21 are accumulated, and an output transistor for outputting a signal corresponding to the potential of the charge accumulation unit 10 ( 32). The charge accumulation unit 10 includes a charge accumulation region 11 electrically connected to the pixel electrode 21, a charge accumulation region 13 formed spaced apart from the region 11, a region 11 and a region. The output transistor 32 is constituted by a region 12 in which the cross section potential is electrically separated at a potential higher than a predetermined potential and electrically connected at a potential below the predetermined potential. Outputs a signal corresponding to the potential of the region 13.

Description

Solid-state imaging device and imaging device {SOLID-STATE IMAGING ELEMENT AND IMAGING DEVICE}

The present invention relates to a solid-state imaging device and an imaging device.

In order to cope with the recent high sensitivity and multiplexing of the solid-state imaging device, a photoelectric conversion layer stacked solid-state imaging device having a photoelectric conversion section including a pair of electrodes and a photoelectric conversion layer sandwiched therebetween is noted. have. This solid-state imaging device moves and accumulates charges generated in the photoelectric conversion layer from one of the pair of electrodes to the silicon substrate, and reads out the signal corresponding to the accumulated charges in a signal reading circuit formed on the silicon substrate (patent See Document 1).

Patent document 1, in a solid-state imaging device of the photoelectric conversion layer stacked type, a hole in the charge generated in the photoelectric conversion layer above the silicon substrate accumulates in the charge accumulation portion in the silicon substrate, the signal according to the holes accumulated in this charge accumulation portion Discloses a configuration of reading by a signal reading circuit. By such a structure, even when an organic material is used for a photoelectric conversion layer, the fall of a sensitivity and broadening of spectral sensitivity can be prevented.

Japanese Unexamined Patent Publication No. 2007-81137

The solid-state imaging device described in Patent Literature 1 accumulates the holes generated in the photoelectric conversion layer in the charge accumulation portion formed of the p-type impurity layer in the silicon substrate, and reads the signal corresponding to the holes by the p-channel MOS transistor. Various methods can be considered for reading a signal due to a hole. For example, a configuration may be considered in which holes generated in the photoelectric conversion layer are accumulated in the charge accumulation portion formed of the n-type impurity layer in the silicon substrate, and the signal corresponding to the holes is read by the n-channel MOS transistor. Hereinafter, this structure is demonstrated with reference to FIG.

It is a figure which shows the structural example of the reading circuit of one pixel of the solid-state image sensor of a photoelectric conversion layer laminated type.

The photoelectric conversion part above a semiconductor substrate is comprised of the pixel electrode 1, the counter electrode 2, and the photoelectric conversion layer 3 between the pixel electrode 1 and the counter electrode 2. As shown in FIG. The semiconductor substrate includes a floating diffusion 4 made of an n-type impurity layer electrically connected to the pixel electrode 1, an n-channel reset transistor 5 for resetting the potential of the floating diffusion 4, and a floating. An n-channel output transistor 6 for outputting a voltage signal in accordance with the potential of the diffusion 4 is formed. The gate electrode of the output transistor 6 is connected to the floating diffusion 4.

A bias voltage (about 5 to 20 V, for example 10 V) higher than the power supply voltage VDD (for example, 3 V) supplied to the read circuit is applied to the counter electrode 2 shown in FIG. An electric field is generated between the pixel electrode 1 and the counter electrode 2 by this bias voltage. Due to this electric field, holes in the charge generated in the photoelectric conversion layer 3 move to the pixel electrode 1, and holes moved to the pixel electrode 1 are accumulated in the floating diffusion 4. When holes accumulate in the floating diffusion 4, the potential of the floating diffusion 4 rises.

When excessive light enters the photoelectric conversion layer, the potential of the floating diffusion 4 rises to the same extent as the bias voltage applied to the counter electrode 2 at the maximum. When such an overvoltage is applied to the floating diffusion 4, the floating diffusion 4 is broken and a failure such as burn-in occurs.

In addition, such a failure also occurs in a configuration in which electrons generated in the photoelectric conversion layer accumulate in a charge accumulation portion formed of a p-type impurity layer in a silicon substrate, and a signal corresponding to the electrons is read by a p-channel MOS transistor. do.

This invention is made | formed in view of the said situation, and an object of this invention is to provide the solid-state image sensor of the photoelectric conversion layer laminated type which does not fail even when excessive light enters, and the imaging device provided with it.

In the solid-state imaging device of the present invention, a pixel including a photoelectric conversion portion formed above the semiconductor substrate and a MOS type signal reading circuit formed on the semiconductor substrate for reading out a signal according to the charge generated in the photoelectric conversion portion is arranged in an array. A solid-state image sensor disposed, wherein the photoelectric conversion unit is formed between the pixel electrode formed above the semiconductor substrate and divided for each pixel, the counter electrode formed above the pixel electrode, and the pixel electrode and the counter electrode. A bias voltage higher than a power supply voltage of the signal reading circuit is applied to the counter electrode so that a hole in the charge generated in the photoelectric conversion layer moves to the pixel electrode, and the signal reading circuit includes: A charge accumulation part is formed in the semiconductor substrate and accumulates holes moved to the pixel electrode. And an output transistor for outputting a signal corresponding to the potential of the charge accumulation portion, and a reset transistor for resetting the potential of the charge accumulation portion to a predetermined reset potential, wherein the charge accumulation portion is electrically connected to the pixel electrode. A second charge accumulation region consisting of a first charge accumulation region comprising a type impurity region, an n-type impurity region formed apart from the first charge accumulation region, and the first charge accumulation region and the second charge accumulation region The amount of holes moved to the pixel electrode is constituted by a separation / connection region which is electrically separated at a potential higher than a predetermined potential in the cross-sectional potential and electrically connected at a potential below the predetermined potential. Up to this predetermined amount, the first charge accumulation region, the second charge accumulation region, and the Holes that move from the pixel electrode are accumulated in each of the isolation / connection regions, and holes that move from the pixel electrode only in the first charge accumulation region after the amount of holes that move to the pixel electrode exceeds the predetermined amount. The output transistor outputs a signal corresponding to the potential of the second charge accumulation region.

In the solid-state imaging device of the present invention, a pixel including a photoelectric conversion portion formed above the semiconductor substrate and a MOS type signal reading circuit formed on the semiconductor substrate for reading out a signal according to the charge generated in the photoelectric conversion portion is arranged in an array. A solid-state image sensor disposed, wherein the photoelectric conversion unit is formed between the pixel electrode formed above the semiconductor substrate and divided for each pixel, the counter electrode formed above the pixel electrode, and the pixel electrode and the counter electrode. A bias voltage lower than a reference voltage of the signal readout circuit is applied to the counter electrode to include a photoelectric conversion layer, and to transfer electrons among charges generated in the photoelectric conversion layer to the pixel electrode, and the signal readout circuit includes: A charge accumulation part formed in the semiconductor substrate and storing electrons moved to the pixel electrode And an output transistor for outputting a signal corresponding to the potential of the charge accumulation portion, and a reset transistor for resetting the potential of the charge accumulation portion to a predetermined reset potential, wherein the charge accumulation portion is electrically connected to the pixel electrode. A second charge accumulation region consisting of a first charge accumulation region comprising a type impurity region, a p-type impurity region formed apart from the first charge accumulation region, and the first charge accumulation region and the second charge accumulation region Is constituted by a separation / connection region which is electrically separated at a potential lower than a predetermined potential in the cross-sectional potential and electrically connected at a potential higher than the predetermined potential, and the amount of electrons moving to the pixel electrode Up to a predetermined amount, the first charge accumulation region, the second charge accumulation region, and the Electrons moving from the pixel electrode are accumulated in each of the isolation / connection regions, and electrons moving from the pixel electrode only in the first charge accumulation region after the amount of electrons moving to the pixel electrode exceeds the predetermined amount. The output transistor outputs a signal corresponding to the potential of the second charge accumulation region.

The imaging device of this invention is equipped with the said solid-state image sensor.

According to this invention, the solid-state image sensor of the photoelectric conversion layer laminated type which does not fail even when excessive light enters, and the imaging device provided with the same can be provided.

1 is a schematic plan view of a solid-state imaging device 100 of the photoelectric conversion layer stacked type for explaining one embodiment of the present invention.
FIG. 2: is a figure which shows schematic structure of the pixel 101 in the solid-state image sensor 100 shown in FIG.
FIG. 3 is a cross-sectional schematic diagram showing a schematic configuration of a pixel 101 in the solid-state imaging device 100 shown in FIG. 1.
FIG. 4 is a timing chart for explaining the imaging operation (when the incident light amount is small) for one pixel row of the solid-state imaging device 100 shown in FIG. 1.
FIG. 5: is a figure which shows the potential transition in the semiconductor substrate 30 at the time of imaging operation (when there is little incident light quantity) for one pixel row of the solid-state image sensor 100 shown in FIG.
FIG. 6: is a figure which shows the potential transition in the semiconductor substrate 30 at the time of imaging operation (when there is little incident light quantity) for one pixel row of the solid-state image sensor 100 shown in FIG.
FIG. 7 is a timing chart for explaining the imaging operation (when the amount of incident light is large) for one pixel row of the solid-state imaging device 100 shown in FIG. 1.
FIG. 8: is a figure which shows the potential transition in the semiconductor substrate 30 at the time of imaging operation (when there is much incident light quantity) for one pixel row of the solid-state image sensor 100 shown in FIG.
FIG. 9 is a diagram showing potential transitions in the semiconductor substrate 30 during the imaging operation (when the amount of incident light is large) for one pixel row of the solid-state imaging device 100 shown in FIG. 1.
FIG. 10: is a figure which shows the potential transition in the semiconductor substrate 30 at the time of imaging operation (when there is much incident light quantity) for one pixel row of the solid-state image sensor 100 shown in FIG.
FIG. 11: is a figure which shows the image obtained by light-shielding this solid-state image sensor and performing dark image pick-up after imaging the sun using the solid-state image sensor which arrange | positioned the pixel of the structure shown in FIG. 14 in the array form. FIG.
FIG. 12: is a figure which shows the image obtained by light-shielding this solid-state image sensor, performing image pick-up, after imaging the sun using the solid-state image sensor which arrange | positioned the pixel of the structure shown in FIG. 2 in the array form. FIG.
FIG. 13: is a figure which shows the modification of the solid-state image sensor 100 shown in FIG.
It is a figure which shows the structural example of the reading circuit of one pixel of the solid-state image sensor of a photoelectric conversion layer laminated type.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a schematic plan view of a solid-state imaging device 100 of the photoelectric conversion layer stacked type for explaining one embodiment of the present invention. The solid-state imaging device 100 is used by mounting on an imaging module such as a digital camera or a digital video camera, an electronic endoscope, a mobile phone with a camera, or the like.

The solid-state imaging device 100 shown in FIG. 1 includes a plurality of pixels 101 arranged in a two-dimensional array image (a square lattice shape in the example of FIG. 1) in a row direction and a column direction orthogonal thereto, and a pixel 101. ), A scanning circuit 102 for controlling the reading of the signal from the signal, a signal processing unit 103 for processing the signal output from each pixel 101, and a control unit 104 for collectively controlling the solid-state imaging device 100. It is provided.

The scanning circuit 102 is connected to a signal reading circuit described later included in each pixel 101 via each of the reset line RS and the row selection line RW. The signal processing unit 103 is connected to each pixel 101 via the output signal line OS.

FIG. 2: is a figure which shows schematic structure of the pixel 101 in the solid-state image sensor 100 shown in FIG. FIG. 3 is a cross-sectional schematic diagram showing a schematic configuration of a pixel 101 in the solid-state imaging device 100 shown in FIG. 1.

As shown to FIG. 2, 3, the pixel 101 is formed above the semiconductor substrate 30 which consists of the p-type silicon substrate 30b and the p-type well layer 30a formed on the p-type silicon substrate 30b. The photoelectric conversion part P and the MOS type signal reading circuit S formed in the semiconductor substrate 30 are provided.

The photoelectric conversion unit P is disposed between the pixel electrode 21 formed above the semiconductor substrate 30, the counter electrode 23 formed above the pixel electrode 21, and the pixel electrode 21 and the counter electrode 23. It includes a photoelectric conversion layer 22 formed in.

Light is incident on the counter electrode 23 from above. Since the counter electrode 23 needs to make light enter the photoelectric conversion layer 22, it is comprised from electroconductive materials, such as ITO, which are transparent with respect to incident light. Although the counter electrode 23 is one piece structure common to all the pixels 101, it may be divided | segmented for every pixel 101. FIG.

The pixel electrode 21 is a thin film electrode divided for every pixel 101. The pixel electrode 21 is comprised by the transparent or opaque electroconductive material (ITO, aluminum, titanium nitride, etc.).

The photoelectric conversion layer 22 is a layer comprised of the organic or inorganic photoelectric conversion material which absorbs a specific wavelength range among incident light, and generate | occur | produces the electric charge according to the absorbed light quantity. The charge blocking layer which suppresses the injection of electric charge into the photoelectric conversion layer 22 from an electrode between the photoelectric conversion layer 22 and the counter electrode 23 or between the photoelectric conversion layer 22 and the pixel electrode 21. This may be formed.

A bias voltage is applied to the counter electrode 23 so that holes among the charges generated in the photoelectric conversion layer 22 move to the pixel electrode 21 and electrons move to the counter electrode 23. In order for the photoelectric conversion layer 22 to exhibit a sufficiently high sensitivity, the bias voltage includes a voltage higher than the power supply voltage VDD (for example, 3 V) that is the maximum value of the voltage supplied to the signal reading circuit S (for example, 3 to 20 V). V degree, for example 10 V) is used.

As shown in FIG. 2, the signal reading circuit S includes a charge storage unit 10 and a reset transistor for resetting the electric potential of the electric charge storage unit 10 to a predetermined reset potential (for example, 0.5 V). 31, an output transistor 32, and a row select transistor 33. The charge accumulation section 10 has a portion where the first charge accumulation region 11, the second charge accumulation region 13, the first charge accumulation region 11 and the second charge accumulation region 13 are deep in potential. In the electrical separation, and in the part where the electric potential is shallow, it is comprised by the isolation | separation / connection area | region 12 which connects electrically. Hereinafter, with reference to FIG. 3, the detail of the signal reading circuit S is demonstrated.

As shown in FIG. 3, the first charge accumulation region 11 is constituted by an n-type impurity region formed in the surface portion of the p-type well layer 30a in the semiconductor substrate 30. The first charge storage region 11 is electrically connected to the pixel electrode 21 by a contact portion 24 made of a conductive material formed on the semiconductor substrate 30.

In the p-type well layer 30a, next to the first charge accumulation region 11, a second charge accumulation region 13, which is slightly spaced apart and formed of an n-type impurity region, is formed.

On the semiconductor substrate 30 between the first charge accumulation region 11 and the second charge accumulation region 13, an electrode 12a is formed via an insulating film (not shown). A fixed voltage (in FIG. 3, a power supply voltage VDD (for example, 3 V) supplied to the signal reading circuit S) is applied to the electrode 12a. The region of the p-type well layer 30a overlapping with the electrode 12a is the isolation / connection region 12. The isolation / connection region 12 electrically separates the first charge accumulation region 11 and the second charge accumulation region 13 at a potential higher than a predetermined potential in the cross-sectional potential of the semiconductor substrate 30. Then, at a potential below the predetermined potential, the electrical connection is performed.

In the p-type well layer 30a, an impurity region 15 composed of an n-type impurity region is formed slightly apart from the second charge accumulation region 13. On the semiconductor substrate 30 between the second charge accumulation region 13 and the impurity region 15, a gate electrode 14 is formed via an insulating film (not shown). The reset line RS shown in FIG. 1 is connected to this gate electrode 14. The impurity region 15 is connected to a power supply for supplying a reset voltage (for example, 0.5 V). The reset transistor 31 shown in FIG. 2 is configured by the second charge accumulation region 13, the impurity region 15, the gate electrode 14, and the channel region below the gate electrode 14.

By controlling the voltage applied to the gate electrode 14 and making the potential of the channel region of the reset transistor 31 deeper than the potential (reset potential) of the impurity region 15, the charge accumulation portion 10 is removed from the impurity region 15. Electrons can be injected to reset the electric potential of the charge accumulation portion 10 to the reset electric potential.

In the p-type well layer 30a, an impurity region 20 composed of an n-type impurity region is formed slightly apart from the impurity region 15. In the p-type well layer 30a, an impurity region 17 composed of an n-type impurity region is formed slightly apart from the impurity region 20. On the semiconductor substrate 30 between the impurity region 20 and the impurity region 17, a gate electrode 16 is formed via an insulating film (not shown). The output transistor 32 shown in FIG. 2 is comprised by the impurity region 20, the impurity region 17, the gate electrode 16, and the channel region below the gate electrode 16. As shown in FIG.

The gate electrode 16 of the output transistor 32 is connected to the second charge accumulation region 13 by wiring. A power supply for supplying a power supply voltage VDD is connected to the impurity region 20 of the output transistor 32. The output transistor 32 outputs a signal corresponding to the potential of the second charge accumulation region 13 determined in accordance with the amount of holes accumulated in the second charge accumulation region 13 to the row select transistor 33.

In the p-type well layer 30a, an impurity region 19 composed of an n-type impurity region is formed slightly apart from the impurity region 17. On the semiconductor substrate 30 between the impurity region 17 and the impurity region 19, a gate electrode 18 is formed via an insulating film (not shown). The row select transistor 33 shown in FIG. 2 is formed by the impurity region 17, the impurity region 19, the gate electrode 18, and the channel region under the gate electrode 18.

The row select line RW shown in FIG. 1 is connected to the gate electrode 18 of the row select transistor 33. The output signal line OS shown in FIG. 1 is connected to the impurity region 19 of the row select transistor 33. When the row select transistor 33 is turned on, the signal output from the output transistor 32 is output to the output signal line OS.

The operation of the solid-state imaging device 100 configured as described above will be described. The solid-state imaging device 100 differs in operation depending on the amount of incident light by the function of the separation / connection region 12 included in the charge storage unit 10. For this reason, below, the operation | movement of the solid-state image sensor 100 is demonstrated dividing into the case where the quantity of incident light is small and when it is large.

FIG. 4 is a timing chart for explaining the imaging operation (when the incident light amount is small) for one pixel row of the solid-state imaging device 100 shown in FIG. 1. In FIG. 4, "RW" has shown the voltage waveform supplied to the row select line RW. In addition, "RS" has shown the voltage waveform supplied to the reset line RS. In addition, "accumulation part 1" has shown the electric potential of the 1st charge accumulation area | region 11. As shown in FIG. In addition, "barrier" has shown the electric potential of the isolation | separation / connection area | region 12. As shown in FIG. In addition, "accumulation part 2" has shown the electric potential of the 2nd charge accumulation area | region 13. As shown in FIG.

5 and 6 are diagrams showing potential transitions in the semiconductor substrate 30 during the imaging operation (when the incident light amount is small) for one pixel row of the solid-state imaging device 100 shown in FIG. 1. FIG. 5: (a)-(c) and FIG. 6 (d)-(f) are potential diagrams in the semiconductor substrate 30 in each period of (a)-(f) shown in FIG. In FIG. 5 and FIG. 6, "accumulation 1" represents the potential of the first charge accumulation region 11. In addition, "barrier" has shown the potential of the isolation | separation / connection area | region 12. FIG. In addition, "accumulation 2" represents the potential of the second charge accumulation region 13. "RG" represents the potential of the channel region of the reset transistor 31. Moreover, "RD" has shown the potential of the impurity region 15 of the reset transistor 31. 5 and 6, the potential becomes higher as it goes downward.

In the solid-state imaging device 100, during operation, as shown in FIG. 4, the charge accumulation period for accumulating charges in the charge accumulation portion 10 and the second charge accumulation of the charge accumulation portion 10 during the charge accumulation period. The frame period (frame) consisting of a signal readout period for reading out a signal in accordance with the charge accumulated in the region 13 is repeated.

Upon the start transition of the frame period, the scanning circuit 102 switches the voltage applied to the gate electrode 14 of the reset transistor 31 from the low level to the high level. Fig. 5A shows the potential state during the reset. As shown in FIG. 5A, when the voltage applied to the gate electrode 14 is at a high level, the potential of the channel region of the reset transistor 31 becomes the potential of the impurity region 15 of the reset transistor 31. Higher than (reset potential). As a result, electrons are injected from the impurity region 15 of the reset transistor 31 to the charge accumulation section 10, so that the first charge accumulation region 11, the isolation / connection region 12, and the second charge accumulation region are All potentials of (13) are reset to the reset potentials.

Next, the scanning circuit 102 switches the voltage applied to the gate electrode 14 of the reset transistor 31 from the high level to the low level to complete the reset. Fig. 5B shows the potential state after the reset is completed. As shown in FIG. 5B, when the voltage applied to the gate electrode 14 is at a low level, the potential of the channel region of the reset transistor 31 becomes the potential of the impurity region 15 of the reset transistor 31. It becomes shallower. At this time, due to the capacitive coupling, the potential of the charge accumulation portion 10 becomes slightly shallower than in the case of Fig. 5A.

After the completion of reset, the signal (reset signal) corresponding to the potential of the second charge accumulation region 13 in the state of FIG. 5B is output from the row select transistor 33 to the output signal line OS. This signal is held by the signal processing unit 103 as a reset signal included in the image pickup signal of the previous frame. Subsequently, the signal processing unit 103 performs a process of subtracting the reset signal from the image pickup signal of the previous frame. When the reset signal is output, the scanning circuit 102 turns off the row select transistor 33.

The potential of the disconnection / connection area 12 is determined by the power supply voltage VDD applied to the electrode 12a, and as shown in FIGS. 5A and 5B, the disconnection / connection area 12 Is at a position deeper than the reset potential. For this reason, electrons injected from the impurity region 15 of the reset transistor 31 are also accumulated in the isolation / connection region 12. Therefore, during the reset and at the completion of the reset, all potentials of the first charge accumulation region 11, the disconnection / connection region 12, and the second charge accumulation region 13 become the same potential.

Since light is always reaching the photoelectric conversion unit P during the imaging operation, the charge accumulation period is started after the reset of FIG. 5B is completed. During this charge accumulation period, holes in charges generated in the photoelectric conversion layer 22 move to the pixel electrode 21 and move from the pixel electrode 21 to the first charge accumulation region 11. The first charge accumulation region 11, the isolation / connection region 12, and the second charge accumulation region 13 are the isolation / connection region 12 determined by the power supply voltage VDD applied to the electrode 12a. Conduction at an electric potential lower than the electric potential of. For this reason, the holes moved to the first charge accumulation region 11 are also accumulated in the separation / connection region 12 and the second charge accumulation region 13. Therefore, all the potentials of the first charge accumulation region 11, the separation / connection region 12, and the second charge accumulation region 13 rise uniformly.

Fig. 5C is a diagram showing the potential state during the charge accumulation period. As shown in Fig. 5 (c), incident light is applied to a region (charge accumulating portion 10) in which the first charge accumulation region 11, the separation / connection region 12, and the second charge accumulation region 13 are combined. Holes H along are accumulated.

At the end timing of the charge accumulation period, the scanning circuit 102 turns on the row select transistor 33 (Figs. 4 (d) and 6 (d)). When the row select transistor 33 is turned on, a signal (imaging signal) corresponding to the potential of the second charge accumulation region 13 is transferred from the output transistor 32 to the output signal line OS via the row select transistor 33. Is output. And this imaging signal is hold | maintained in the signal processing part 103.

Next, the scanning circuit 102 switches the voltage applied to the gate electrode 14 of the reset transistor 31 from the low level to the high level, and resets the potential of the charge accumulation unit 10. Fig. 6 (e) shows the potential state during the reset. When the scanning circuit 102 returns the voltage applied to the gate electrode 14 of the reset transistor 31 to the low level, the reset is completed. The potential at this time is as shown in Fig. 6 (f). When the reset is completed, the signal (reset signal) corresponding to the potential of the second charge accumulation region 13 in the state of FIG. 6 (f) is output from the row select transistor 33 to the output signal line OS. . This signal is held by the signal processing unit 103. After the output of the reset signal, the scanning circuit 102 turns off the row select transistor 33.

The signal processing unit 103 obtains an image pickup signal from which noise is removed by subtracting the reset signal held in Fig. 4F from the image pickup signal held in Fig. 4D.

FIG. 7 is a timing chart for explaining the imaging operation (when the amount of incident light is large) for one pixel row of the solid-state imaging device 100 shown in FIG. 1. Each mark (RW, RS, storage part 1, barrier, storage part 2) in FIG. 7 is the same as that of FIG.

8 to 10 are diagrams showing potential transitions in the semiconductor substrate 30 during the imaging operation (when the amount of incident light is large) for one pixel row of the solid-state imaging device 100 shown in FIG. 1. (A)-(c) of FIG. 8, (d)-(f) of FIG. 9, and (g) of FIG. 10 are the semiconductor substrates in each period of (a)-(g) shown in FIG. 30 is a potential diagram. Each notation (accumulation (1), barrier, accumulation (2), RG, RD) in FIGS. 8-10 is the same as that of FIGS. 8 to 10, the dislocation becomes higher toward the lower side.

Upon the start transition of the frame period, the scanning circuit 102 switches the voltage applied to the gate electrode 14 of the reset transistor 31 from the low level to the high level. Fig. 8A shows the potential state during the reset.

Next, the scanning circuit 102 switches the voltage applied to the gate electrode 14 of the reset transistor 31 from the high level to the low level to complete the reset. The potential state after completion of reset is shown in Fig. 8B. As shown in Fig. 8 (b), after the completion of reset, the potential of the charge storage unit 10 becomes slightly shallower than that in Fig. 8 (a) due to capacitive coupling.

After the completion of the reset, the signal (reset signal) corresponding to the potential of the second charge accumulation region 13 in the state of FIG. 8B is output from the row select transistor 33 to the output signal line OS. This signal is held in the signal processing unit 103 as a reset signal included in the image pickup signal of the previous frame. Then, the signal processing unit 103 performs a process of subtracting the reset signal from the image pickup signal of the previous frame. When the reset signal is output, the scanning circuit 102 turns off the row select transistor 33.

Since light always comes into contact with the photoelectric conversion unit P during the imaging operation, the charge accumulation period is started after the reset of FIG. 8B is completed. During this charge accumulation period, holes in charges generated in the photoelectric conversion layer 22 move to the pixel electrode 21 and move from the pixel electrode 21 to the first charge accumulation region 11. The first charge accumulation region 11, the isolation / connection region 12, and the second charge accumulation region 13 are the isolation / connection region 12 determined by the power supply voltage VDD applied to the electrode 12a. Is conducted at potentials below the potential of. For this reason, the holes moved to the first charge accumulation region 11 are also accumulated in the separation / connection region 12 and the second charge accumulation region 13. Therefore, all the potentials of the first charge accumulation region 11, the separation / connection region 12, and the second charge accumulation region 13 rise uniformly.

FIG. 8C is a diagram showing the potential state in the charge accumulation period when the amount of holes moved to the pixel electrode 21 is equal to or less than the threshold value. As shown in Fig. 8 (c), incident light is applied to a region (charge accumulator 10) in which the first charge accumulation region 11, the separation / connection region 12, and the second charge accumulation region 13 are combined. Holes H along are accumulated.

As shown in Fig. 9 (d), the holes move further to the pixel electrode 21, so that potentials of the first charge accumulation region 11 and the second charge accumulation region 13 are transferred to the electrode 12a. When the potential of the second charge accumulation region 13 is higher than the potential of the isolation / connection region 12 (hereinafter referred to as a barrier potential) determined by the applied power supply voltage VDD, the potential is slightly higher than the barrier potential. Is constant and no more. This cancels the current flowing from the semiconductor substrate 30 into the second charge accumulation region 13 and the current flowing out of the second charge accumulation region 13 into the first charge accumulation region 11 beyond the barrier potential. Because it becomes.

Therefore, when the potential of each of the first charge accumulation region 11 and the second charge accumulation region 13 becomes higher than the barrier potential, holes that have moved to the pixel electrode 21 are only in the first charge accumulation region 11. Accumulate. Then, only the potential of the first charge accumulation region 11 continues to rise to the same degree as the bias voltage applied to the counter electrode 23 at the maximum.

When the end of the charge accumulation period is reached, the scanning circuit 102 turns on the row select transistor 33 (Figs. 7 (e) and 9 (e)). When the row select transistor 33 is turned on, a signal (imaging signal) corresponding to the potential (potential slightly higher than the barrier potential) of the second charge accumulation region 13 causes the row select transistor 33 to be output from the output transistor 32. Via the output signal line OS. This captured image signal is held by the signal processing unit 103.

Next, the scanning circuit 102 switches the voltage applied to the gate electrode 14 of the reset transistor 31 from the low level to the high level, and resets the potential of the charge accumulation unit 10. Fig. 9 (f) shows the potential state during the reset. When the scanning circuit 102 returns the voltage applied to the gate electrode 14 of the reset transistor 31 to the low level, the reset is completed. The potential at this time is as shown to Fig.10 (g). When the reset is completed, the signal (reset signal) corresponding to the potential of the second charge accumulation region 13 in the state of FIG. 10G is output from the row select transistor 33 to the output signal line OS. . This signal is held by the signal processing unit 103.

The signal processing unit 103 obtains an image pickup signal from which noise is removed by subtracting the reset signal held in Fig. 7G from the image pickup signal held in Fig. 7E.

As described above, according to the solid-state imaging device 100, the amount of holes accumulated in the charge storage unit 10 is a predetermined amount (the charge storage unit when the potential of the second charge storage region 13 is equal to the barrier potential). When the amount of holes accumulated in (10) is exceeded, no further hole accumulation is performed in the second charge accumulation region 13, but hole accumulation is performed only in the first charge accumulation region 11. For this reason, even when excessive light enters the solid-state imaging device 100, the potential of the second charge accumulation region 13 is slightly lower than the potential at which the second charge accumulation region 13 may be destroyed (barrier potential). High value) can be prevented.

FIG. 11: is a figure which shows the image obtained by light-shielding this solid-state image sensor and performing dark image pick-up after imaging the sun using the solid-state image sensor which arrange | positioned the pixel of the structure shown in FIG. 14 in the array form. FIG. FIG. 12: is a figure which shows the image obtained by light-shielding this solid-state image sensor, performing image pick-up, after imaging the sun using the solid-state image sensor which arrange | positioned the pixel of the structure shown in FIG. 2 in the array form. FIG.

In the image shown in FIG. 11, black circular burn-in occurred in the position corresponding to the part irradiated with sunlight, whereas burn-in did not occur in any part in the image shown in FIG.

In the solid-state imaging device having the pixel having the configuration shown in FIG. 14, the potential of the floating diffusion 4 rises excessively rapidly by very strong sunlight, causing the floating diffusion 4 to be destroyed, and the floating diffusion 4 to be destroyed. The dark current (electron) increased sharply in the pixel containing. 11 and 12, when holes are generated as signals, they are displayed in white on the image. For this reason, as the electrons increase due to the failure, it is considered that the failure point appears as a black circular burn-in, as shown in FIG. On the other hand, according to the solid-state image sensor 100, the separation / connection area | region 12 suppresses significant electric potential rise of the 2nd charge accumulation area | region 13, and it can prevent that a failure arises. For this reason, in FIG. 12, burn-in as shown in FIG. 11 does not generate | occur | produce and it is thought that uniform output was obtained.

In addition, the isolation / connection region 12 electrically connects the first charge accumulation region 11 and the second charge accumulation region 13 at a position deeper than a predetermined potential (for example, the power supply voltage VDD). What is necessary is just to have a function of isolate | separating and electrically connecting at the position below the said predetermined electric potential. For example, as shown in FIG. 13, it can also form by the impurity region formed in the semiconductor substrate 30. FIG.

FIG. 13: is a figure which shows the modification of the solid-state image sensor 100 shown in FIG. FIG. 13 is a diagram corresponding to FIG. 3.

In the pixel 101 shown in FIG. 13, except that the isolation / connection region 12 and the electrode 12a are removed and the p-type impurity region 120 and the n-type impurity region 121 are added, It is the same structure as the pixel 101 shown in FIG.

The n-type impurity region 121 is formed in the p-type well layer 30a between the first charge accumulation region 11 and the second charge accumulation region 13. The impurity concentration of the n-type impurity region 121 is lower than that of each of the first charge accumulation region 11 and the second charge accumulation region 13.

The p-type impurity region 120 is formed on the surface of the n-type impurity region 121. With such a configuration, the n-type impurity region 121 has a potential higher than the predetermined potential in the cross-sectional potential of the first charge accumulation region 11 and the second charge accumulation region 13 in the semiconductor substrate 30. In the case of electrical separation, the electrical potential is electrically connected at a potential lower than or equal to the predetermined potential. In short, the n-type impurity region 121 functions as a separation / connection region. In addition, since the p-type impurity region 120 is formed, effects such as dark current reduction can also be obtained.

In this way, when the isolation / connection region is formed of the n-type impurity region 121, the electrode 12a for applying the fixed voltage becomes unnecessary. For this reason, compared with the pixel structure of FIG. 3, wiring number can be reduced and a pixel can be refined.

In addition, in this specification, the electric charge taken out from the photoelectric conversion part P and accumulate | stored in the floating diffusion 4 was made into the hole, and the signal readout circuit S was formed into an n-channel MOS transistor. However, it is good also as a structure which makes the charge taken out from the photoelectric conversion part P into an electron, and forms the signal reading circuit S from a p-channel MOS transistor. In this case, both n-type and p-type in the solid-state image sensor described so far are reversed. The counter electrode is also applied with a value (e.g. -10 V) lower than the reference voltage GND (e.g. 0 V) serving as a reference for all potentials supplied to the signal reading circuit. Even in this configuration, the cross-sectional potential in the substrate is as shown in Figs. 5, 6 and 8 to 10. However, in each drawing, the electric potential becomes higher as it goes upward. Thus, the same effects as described above can be obtained.

As described above, the following matters are disclosed in this specification.

The disclosed solid-state imaging device includes a pixel including a photoelectric conversion section formed above the semiconductor substrate and a MOS type signal reading circuit formed on the semiconductor substrate for reading out a signal according to the charge generated in the photoelectric conversion section. The solid-state imaging device, wherein the photoelectric conversion unit is a photoelectric conversion unit formed above the semiconductor substrate and divided for each of the pixels, a counter electrode formed above the pixel electrode, and formed between the pixel electrode and the counter electrode. And a bias voltage higher than a power supply voltage of the signal reading circuit is applied to the counter electrode so that holes among charges generated in the photoelectric conversion layer move to the pixel electrode, and the signal reading circuit includes the semiconductor substrate. A charge accumulation portion formed therein and accumulating holes moved to the pixel electrode; An output transistor for outputting a signal corresponding to the potential of the previous charge accumulation portion, and a reset transistor for resetting the potential of the charge accumulation portion to a predetermined reset potential, wherein the charge accumulation portion is an n-type electrically connected to the pixel electrode; A second charge accumulation region consisting of an impurity region, a second charge accumulation region composed of an n-type impurity region formed next to the first charge accumulation region, and the first charge accumulation region and the second charge accumulation region; And a separation / connection region which is electrically separated at a potential higher than a predetermined potential in the cross-sectional potential and electrically connected at a potential below the predetermined potential, and the amount of holes moving to the pixel electrode The first charge accumulation region, the second charge accumulation region, and the minute up to a predetermined amount. Holes accumulated in the connection region are accumulated in each of the connection regions, and holes are moved from the pixel electrode only in the first charge accumulation region after the amount of holes moving to the pixel electrodes exceeds the predetermined amount. The output transistor outputs a signal corresponding to the potential of the second charge accumulation region.

In the disclosed solid-state imaging device, the predetermined potential is higher than the reset potential.

The disclosed solid-state imaging device includes a pixel including a photoelectric conversion section formed above the semiconductor substrate and a MOS type signal reading circuit formed on the semiconductor substrate for reading out a signal according to the charge generated in the photoelectric conversion section. The solid-state imaging device, wherein the photoelectric conversion unit is a photoelectric conversion unit formed above the semiconductor substrate and divided for each of the pixels, a counter electrode formed above the pixel electrode, and formed between the pixel electrode and the counter electrode. A bias voltage lower than a reference voltage of the signal reading circuit is applied to the counter electrode so that electrons of charge generated in the photoelectric conversion layer move to the pixel electrode, and the signal reading circuit includes the semiconductor substrate. A charge accumulator formed therein and accumulating electrons moved to the pixel electrode; An output transistor for outputting a signal corresponding to the potential of the previous charge accumulation portion, and a reset transistor for resetting the potential of the charge accumulation portion to a predetermined reset potential, wherein the charge accumulation portion is electrically connected to the pixel electrode. A second charge accumulation region composed of an impurity region, a second charge accumulation region composed of a p-type impurity region formed apart from the first charge accumulation region, and the first charge accumulation region and the second charge accumulation region And a disconnection / connection region which is electrically separated at a potential lower than a predetermined potential in the cross-sectional potential and electrically connected at a potential higher than the predetermined potential, and the amount of electrons moving to the pixel electrode is small. Until the quantification, the first charge accumulation region, the second charge accumulation region, and the minute Electrons moving from the pixel electrode are accumulated in each of the connection regions, and electrons moving from the pixel electrode are accumulated only in the first charge storage region after the amount of electrons moving to the pixel electrode exceeds the predetermined amount. The output transistor outputs a signal corresponding to the potential of the second charge accumulation region.

In the disclosed solid-state imaging device, the predetermined potential is lower than the reset potential.

In the disclosed solid-state imaging device, the isolation / connection region is formed by a gate electrode to which a fixed voltage is applied, formed above the semiconductor substrate between the first charge accumulation region and the second charge accumulation region.

The disclosed solid-state imaging device includes the fixed voltage being the power supply voltage.

The disclosed solid-state imaging device includes the fixed voltage being the reference voltage.

In the disclosed solid-state imaging device, the isolation / connection region is constituted by an impurity region formed between the first charge accumulation region and the second charge accumulation region in the semiconductor substrate.

In the disclosed solid-state imaging device, the impurity region is of the same conductivity type as each of the first charge accumulation region and the second charge accumulation region, and the impurity concentration of the impurity region is the first charge accumulation region and the second. It is lower than each of the charge accumulation regions.

The disclosed solid-state imaging device includes the impurity region and another impurity region of reverse conductivity on the surface of the impurity region.

The disclosed imaging device includes the solid-state imaging device.

Industrial availability

According to this invention, the solid-state image sensor of the photoelectric conversion layer laminated type which does not fail even when excessive light enters, and the imaging device provided with the same can be provided.

Although this invention was detailed also demonstrated with reference to the specific embodiment, it is clear for those skilled in the art that various changes and correction can be added without deviating from the mind and range of this invention. This application is based on the JP application (Japanese Patent Application No. 2011-70944) for which it applied on March 28, 2011, and the Japanese application (Japanese Patent Application No. 2011-105332) for which it applied for May 10, 2011, The content Is hereby incorporated by reference.

100: solid-state imaging device
101: pixels
10: charge storage unit
11: first charge accumulation region
12: separation / connection area
13: second charge accumulation region
21: pixel electrode
22: photoelectric conversion layer
23: counter electrode
30: semiconductor substrate
31: reset transistor
32: output transistor

Claims (12)

A solid-state imaging device in which a pixel including a photoelectric conversion section formed above a semiconductor substrate and a MOS-type signal reading circuit formed in the semiconductor substrate that reads a signal according to electric charges generated in the photoelectric conversion section is arranged in an array.
The photoelectric conversion unit includes a pixel electrode formed above the semiconductor substrate and divided for each pixel, an opposite electrode formed above the pixel electrode, and a photoelectric conversion layer formed between the pixel electrode and the opposite electrode,
A bias voltage higher than the power supply voltage of the signal reading circuit is applied to the counter electrode so that holes among charges generated in the photoelectric conversion layer move to the pixel electrode,
The signal readout circuit includes a charge accumulation section in which the holes formed in the semiconductor substrate and moved to the pixel electrode accumulate, an output transistor for outputting a signal corresponding to the potential of the charge accumulation section, and a potential of the charge accumulation section. A reset transistor for resetting to a reset potential,
The charge accumulation section includes a first charge accumulation region comprising an n-type impurity region electrically connected to the pixel electrode, and a second charge accumulation region including an n-type impurity region spaced apart from the first charge accumulation region. A separation / connection region in which the first charge accumulation region and the second charge accumulation region are electrically separated at a potential higher than a predetermined potential in the cross-sectional potential, and electrically connected at a potential equal to or less than the predetermined potential. And the holes moving from the pixel electrode in each of the first charge accumulation region, the second charge accumulation region, and the isolation / connection region until the amount of holes moving to the pixel electrode is up to a predetermined amount. And the first electrode after the amount of holes moving to the pixel electrode exceeds the predetermined amount. Only in the accumulation region is to accumulate the hole to move from the pixel electrode,
And the output transistor outputs a signal corresponding to the potential of the second charge accumulation region. The method of claim 1,
And said predetermined potential is higher than said reset potential. A solid-state imaging device in which a pixel including a photoelectric conversion section formed above a semiconductor substrate and a MOS-type signal reading circuit formed in the semiconductor substrate that reads a signal according to electric charges generated in the photoelectric conversion section is arranged in an array.
The photoelectric conversion unit includes a pixel electrode formed above the semiconductor substrate and divided for each pixel, an opposite electrode formed above the pixel electrode, and a photoelectric conversion layer formed between the pixel electrode and the opposite electrode,
A bias voltage lower than a reference voltage of the signal readout circuit is applied to the counter electrode so that electrons of charge generated in the photoelectric conversion layer move to the pixel electrode,
The signal readout circuit includes a charge accumulation unit in which electrons formed in the semiconductor substrate and moved to the pixel electrode accumulate, an output transistor for outputting a signal in accordance with the potential of the charge accumulation unit, and a potential of the charge accumulation unit in a predetermined manner. A reset transistor for resetting to a reset potential,
The charge accumulation section includes a first charge accumulation region comprising a p-type impurity region electrically connected to the pixel electrode, and a second charge accumulation region including a p-type impurity region spaced apart from the first charge accumulation region. And a separation / connection region in which the first charge accumulation region and the second charge accumulation region are electrically separated at a potential lower than a predetermined potential in the cross-sectional potential and electrically connected at a potential higher than the predetermined potential. And the electrons moving from the pixel electrode in each of the first charge accumulation region, the second charge accumulation region, and the isolation / connection region until the amount of electrons moving to the pixel electrode is up to a predetermined amount. And the first electric charge after the amount of electrons moving to the pixel electrode exceeds the predetermined amount. Only in the accumulation region is to accumulate the electrons traveling from the pixel electrodes,
And the output transistor outputs a signal corresponding to the potential of the second charge accumulation region. The method of claim 3, wherein
And said predetermined potential is lower than said reset potential. 3. The method according to claim 1 or 2,
The isolation / connection region is formed by a gate electrode to which a fixed voltage is applied, formed above the semiconductor substrate between the first charge accumulation region and the second charge accumulation region. The method according to claim 3 or 4,
The isolation / connection region is formed by a gate electrode to which a fixed voltage is applied, formed above the semiconductor substrate between the first charge accumulation region and the second charge accumulation region. The method of claim 5, wherein
And said fixed voltage is said power supply voltage. The method according to claim 6,
And said fixed voltage is said reference voltage. 5. The method according to any one of claims 1 to 4,
The isolation / connection region is a solid-state imaging device comprising an impurity region formed between the first charge accumulation region and the second charge accumulation region in the semiconductor substrate. The method of claim 9,
The impurity region is of the same conductivity type as each of the first charge accumulation region and the second charge accumulation region,
The impurity concentration of the impurity region is lower than each of the first charge accumulation region and the second charge accumulation region. 11. The method of claim 10,
The impurity region is provided with a surface of the impurity region and a separate impurity region of reverse conductivity type. The imaging device provided with the solid-state image sensor of any one of Claims 1-11.

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