KR20140001483A

KR20140001483A - Semiconductor integrated circuit

Info

Publication number: KR20140001483A
Application number: KR1020120069159A
Authority: KR
Inventors: 이두찬; 양종열
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2012-06-27
Filing date: 2012-06-27
Publication date: 2014-01-07

Abstract

The present invention relates to a semiconductor integrated circuit device which includes a mat array which includes even-numbered mats arranged in a row direction, a dummy mat which is selectively located on the outer side of a first or final mat among the mats comprising the mat array, and a plurality of redundancy lines which are selectively arranged on the mats corresponding to a large number among the number of the mats corresponding to even rows of the mat array including the dummy mat and the number of the mat corresponding to odd rows of the mat array including the dummy mat.

Description

Semiconductor Integrated Circuits

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a redundancy word line.

Currently, semiconductor memory devices are driven by being divided into a plurality of banks. The plurality of banks includes a plurality of mats (MATs) composed of a plurality of memory cells, and the plurality of mats are arranged in a row direction and a column direction to form a plurality of mat rows (hereinafter referred to as mat blocks) and a plurality of mat columns. .

The mat row (MAT_col) of the DRAM device having the conventional 512M bank structure includes a total of 64 mats and dummy mats (MAT_D) from mat 0 (MAT 0) to mat 63 (MAT 63) as shown in FIG. Doing. In addition, each of the mats MAT is configured to include, for example, 512 word lines WL0-WL511 and eight redundancy lines Red WL0-Red WL7.

Currently, DRAM devices tend to reduce the amount of data in banks and increase the number of banks. Therefore, it is necessary to change the design of the circuit and the wiring in accordance with the generation change so that the effective net die of each DRAM device can be increased.

The present invention provides a semiconductor integrated circuit device capable of improving an effective net die.

The semiconductor integrated circuit device according to the embodiment of the present invention includes a mat column including an even number of mats arranged in a column direction, and a dummy selectively positioned outside the first or last mat of the mats constituting the mat column. A plurality of redundancy selectively disposed on the mats, the mats corresponding to a larger number of mats corresponding to even rows of the mat column and the number of mats corresponding to odd rows, including the dummy mat. It includes a line.

In addition, according to another embodiment of the present invention, a semiconductor integrated circuit device may include a mat column including a plurality of mats arranged in a column direction, and a redundancy word selectively disposed on an even number mat among mats constituting the mat column. And a redundancy word line is configured to replace a defect of either the corresponding mat and the odd mat adjacent to the even mat.

In addition, a mat column comprising a plurality of mats arranged in a column direction, and a plurality of redundancy word lines selectively disposed on odd-numbered mats of the mats constituting the mat row, the plurality of redundancy word lines And to replace defects of either the odd-numbered mat and the even-numbered mat adjacent to the corresponding-numbered mat.

In addition, a semiconductor integrated circuit device according to another embodiment of the present invention, a bank including an even mat and an odd mat arranged in a column direction, an even row decoder and an odd mat installed to correspond to the even mat outside the bank. A row decoding block including an odd row decoder installed to correspond to the dummy mat, a dummy mat selectively disposed on the outer edge of the even mat or the outer edge of the odd mat, and the even mat and the odd mat selected from the odd mat. And a plurality of redundancy lines disposed.

In this case, each of the even row decoder and the odd row decoder may include a redundancy determination circuit unit for outputting a redundancy determination signal when a defect of a corresponding mat occurs, and a mat selection circuit unit for activating a block in which the corresponding mats are arranged.

The mat selection circuit part corresponding to the mat on which the plurality of redundancy lines are arranged is one of an address decoding signal specifying the mat position, the redundancy determination signal of the redundancy determination circuit part of the row decoder, and a row decoder adjacent to the row decoder. Is driven in response to the redundancy determination signal of the redundancy determination circuit portion of the. The mat selection circuit portion corresponding to the mat on which the plurality of redundancy lines are not arranged is driven in response to an address decoding signal specifying the mat position.

According to the present invention, the redundancy word line is selectively placed only on the even mat or the odd mat of the mats constituting the mat row. Accordingly, since the redundancy word lines are disposed only on some mats, the bank size can be reduced by the area where the existing redundancy word lines are formed, and the effective net die can be improved.

1 is a plan view schematically illustrating a mat column structure of a general semiconductor integrated circuit device.
2 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.
3 is a plan view illustrating a mat column structure of a semiconductor integrated circuit device according to an example embodiment.
4 is a view for explaining a general open bit line structure requiring a dummy mat.
5 is an enlarged plan view illustrating a portion “A” of FIG. 2.
6 is a block diagram illustrating a redundancy operation according to an embodiment of the present invention.
7 is a plan view illustrating a mat column structure of a semiconductor integrated circuit device according to another exemplary embodiment of the present inventive concept.
8 is a block diagram illustrating a redundancy operation of the semiconductor integrated circuit device of FIG. 7.

Hereinafter, with reference to the accompanying drawings, it will be described a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.

Referring to FIG. 2, the semiconductor integrated circuit device 100 may include a plurality of banks BANK, a row decoding block 120, and a column decoding block 140.

The plurality of banks BANK may be divided into a plurality of upper banks up_BANK and a plurality of lower banks down_BANK around the peripheral area 110. The row decoding block 120 is positioned between two banks BANK adjacent to each other in the row direction, so that the row decoding block 120 controls the row system signals of the banks BANK. The row decoding block 120 includes a plurality of row decoders 122 corresponding to the mats arranged in the row direction, that is, the mat block.

The column decoding block 140 is positioned between the bank BANK and the peripheral region 110. The column decoding block 140 is configured to control columnar signals of two adjacent banks BANK.

As the generation of the semiconductor memory device changes, the current bank BANK may be provided with a plurality of mats MAT, for example, to input and output data of 256M bytes. The mats MAT are generally memory cell arrays, which may be arranged in a matrix in a row direction and a column direction, and include a plurality of word lines WL0-WL511 and a plurality of bit lines (not shown) on the mat MAT. Is placed).

Also, in semiconductor memory devices such as DRAMs, the number of unit banks is increasing and the amount of input / output data of the unit banks is decreasing. Despite this change, the number and arrangement of word lines and bit lines inside the banks BANK and MAT remain the form of the previous generation. Therefore, it is necessary to remove unnecessary circuit components in response to the reduction of the data amount of the unit bank.

Therefore, in the present embodiment, the number of redundancy lines, particularly redundancy word lines, installed in each mat is to be changed.

Referring to FIG. 3, a plurality of mats are continuously arranged in a column direction. In this embodiment, the mat row may be composed of an even number, for example 64 mats (MAT0-MAT63), and a dummy mat (MAT_D). The dummy mat MAT_D is disposed adjacent to the outside of any one of the mat (MAT0, hereinafter referred to as mat 0) located in the first block corresponding to the edge mat and the mat (MAT63, hereinafter referred to as 63rd mat) located in the last block. Can be. In the present embodiment, an example in which the dummy mat MAT_D is disposed at an adjacent outer side of the zeroth mat MAT0 will be described.

Typically, a dummy mat (MAT_D) is provided to drive the bit line sense amplifier of the edge mat (MAT0 or MAT 63). As shown in FIG. 4, the arbitrary mat MAT n includes a plurality of bit line pairs BL extending in the column direction as described above. At present, in order to improve area efficiency, a memory device such as a DRAM adopts an open bit line method. In the open bit line method, the upper bit line pair BL_up of the bit line pair is controlled by the upper sense amplifier up_S / A positioned above the mat MAT n, and the lower bit line pair BL_down The sub-sense amplifier down_S / A located under the mat MATn is controlled.

However, in the case of the zeroth mat MAT0, since there is no other mat thereon, the upper bit line pair BL_up of the zeroth mat MAT0 is difficult to control. Accordingly, the dummy mat MAT_D is disposed above the zeroth mat MAT0 to control the upper bit line of the zeroth mat MAT0 together with the dummy mat MAT_D. On the other hand, according to the principle described above, the MAT 63 cannot control its lower bit line pair. Therefore, one mat may be interpreted as a lower mat area of the dummy mat MAT_D and an upper mat of the 63rd mat MAT63.

In the present embodiment, when the dummy mat MAT_D is positioned above the zeroth mat MAT0, as shown in FIG. 3, the redundancy word line Red WL is an even mat MAT0, 2, and 4. ....) only to be formed.

The plurality of redundancy word lines Red WL0-Red WL7 are disposed in parallel with the plurality of word lines WL0-WL511 on respective even mats MAT0, 2, 4... On the other hand, only the plurality of word lines WL0-WL511 are disposed on the odd mats MAT1, 3, 5 ... without the redundancy word lines Red WL0-Red WL7 thereon. Therefore, the area of the odd mats MAT 1,3,5 .. may be reduced, or as much as the redundancy word line Red WL0-Red WL7 forming regions of the odd mats MAT 1,3,5 .. You can increase the number.

Referring to FIG. 5, the row decoding block 120 includes a plurality of row decoders 122. Each row decoder 122 is installed to correspond to each mat block (or mat row). The row decoder 122 controls mat blocks of both banks BANK.

The row decoder 122 may include a mat select circuit 1212, a low redundancy determining circuit 1220_Even and 1220_Odd, first and second fuse sets 1230a and 1230b, and first and second other mat driving circuits 1240a and 1240b. It may include.

The mat select circuit 1212 becomes the even mat select circuit 1212a when the row decoder 122 corresponds to the even mat block, and the odd mat select circuit 1212b when the row decoder 122 corresponds to the odd mat block. Can be.

The conventional even mat selection circuit unit 1210a and the odd mat selection circuit unit 1210b have the same configuration, but in the present embodiment, the even mat selection circuit unit corresponding to the even mat block in which the redundancy word lines Red_WL0-Red_WL7 are disposed ( 1210a) is designed to receive redundancy information of any one of the corresponding even mat and the adjacent odd mat. On the other hand, the odd mat selection circuit unit 1210b corresponding to the odd mat block does not receive redundancy information.

The first fuse set 1230a is disposed adjacent to one side of the low redundancy determining circuit unit 1220_Even and 1220_odd, for example, the left side of the mat block, and the second fuseset 1230b is the low redundancy determining circuit unit 1220_Even and 1220_odd. Disposed adjacent to the other side of the mat block, for example, the right mat block, to provide a fuse signal for replacing a defective cell of the mat block.

The first mat driving circuit unit 1240a is disposed between the left mat block and the first fuse set 1230a, and the second mat driving circuit unit 1240b is disposed between the right mat block and the other fuse set 1230b. Provide a signal for substantially driving adjacent mat blocks.

As shown in FIG. 6, when the redundancy word line Red_WL0-Red_WL1 is disposed only on an even mat, the even mat selection circuit unit 1210a may have a row free decoding block 130 as shown in FIG. 6. The address decoding signals LAX9A, LAXBC, and LAXDE provided by, the redundancy determination signal HITB <0: 1> output from the low redundancy determination circuit unit 1220_Even of the corresponding even mat, and adjacent (for example, the following rows). And receive all of the redundancy determination signals HITB <2: 3> outputted from the low redundancy determination circuit portion 1220_odd of the odd-numbered mat, and generate a block selection signal BS in response thereto. Here, the address decoding signals LAX9A, LAXBC, and LAXDE are signals for determining the positions of the mat and the mat block, and the redundancy determination signals HITB <0: 3> are used when the defects of the mat are generated. The signal indicates defect information according to the cutting information of the fuse sets 1230a and 1230b.

That is, the even matte selection circuit unit 1210a receives the mat block signal in the case of normal, the redundancy information of the even mat block, and the redundancy information of the adjacent odd mat block, and if it is normal, drives the mat driving circuits 1240a and 1240b. Can be. The even mat selection circuit unit 1210a may replace some of the redundancy word lines Red WL0-Red WL7 with defects of the even mat block when redundancy information of the even mat block is input. When the redundancy information of the odd mat block is input, the rest of the redundancy word lines Red WL0-Red WL7 may be provided to the odd mat block.

On the other hand, even if the odd mat selection circuit unit 1210b generates a redundancy determination signal HITB <2: 3> due to a defect occurring in the odd mat Odd_MAT, the odd mat Odd_MAT is a redundancy word line Red_WL0-Red_WL7. Does not hold In addition, since the odd mat selection circuit unit 1210b is designed not to receive the redundancy determination signal HITB <2: 3> corresponding to the redundancy information, the odd mat selection circuit unit 1210b is provided only when a normal address decoding signal is input. The odd mat driving circuit unit 1240b is driven.

In this case, the number of redundancy word lines required for each mat may be reduced in response to the decrease in the amount of data in the bank. Even if the odd mat is not provided with the redundancy word lines, the even mat is provided with a sufficient amount of the redundancy word lines, thereby covering the defects of the odd mat.

In the present embodiment, according to the installation of the dummy mat MAT_D, the total number of mats (total pile mats and mats constituting the mat rows) constituting the mat rows is odd, so that the even mats (MAT0, 2, The number of 4 ...) and the odd-numbered mats (MAT1, 3, 5 ...) are different. In this case, the redundancy word line is disposed on a mat corresponding to a smaller number of even mats and odd mats. That is, as described above, when the dummy mat MAT_D is disposed outside the zeroth mat MAT0, the number of the odd-numbered mats MAT_D, MAT1, 3, 5, ..63 is the even-numbered mats MAT0, 2, and 4. .62). In this case, redundancy word lines are arranged on even-numbered mats MAT0,2,4 .., 62.

Accordingly, the number of redundancy word lines can be configured to the minimum, and the redundancy word lines can be prevented from being disposed on the dummy mat MAT_D.

As illustrated in FIG. 7, the dummy mat MAT_D may be positioned below the 63rd mat MAT63. In this case, the number of even mats is greater than the number of odd mats. Accordingly, the redundancy word lines Red WL0-Red_WL7 may be distributed only to a relatively small number of odd-numbered row mats.

In this case, as shown in Fig. 8, the odd matte selection circuit section 1210b includes the address decoding signal, the low redundancy determination signal HITB <2: 3> of the odd-numbered mat and one of the adjacent even-numbered mats. The block selection signal is generated in response to the determination signal HITB <0: 1>, and the even matte selection circuit unit 1210a generates the block selection signal in response to the address decoding signal.

As described in detail above, according to the present invention, the redundancy word line is selectively disposed only on even or odd mats among the mats constituting the mat row. Therefore, the size of the bank can be reduced, and further, the effective net die can be improved.

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that it can be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

120: row decoding block 122: row decoder
1210a: Even mat selection circuit 1210b: Odd mat selection circuit

Claims

A mat row comprising even mats arranged in a row direction;
A dummy mat selectively positioned outside the first or last mat of the mats constituting the mat row; And
Selectively placing on the mats the smaller number of the mats in the even row and the number of the mats in the odd row among the total number of mats constituting the dummy mat and the mat row And a plurality of redundancy lines.

The method of claim 1,
If the dummy mat is placed outside the first mat,
And the plurality of redundancy lines are respectively disposed on mats corresponding to the even-numbered rows.

The method of claim 1,
If the dummy mat is placed outside the last mat,
And the plurality of redundancy lines are disposed on mats corresponding to the odd-numbered rows.

The method of claim 1,
And the mat holding the plurality of redundancy lines is configured to provide a portion of the plurality of redundancy lines to the mat on which the defect has occurred, in the event of a defect of the mat not having adjacent redundancy lines.

A mat row composed of a plurality of mats arranged in a row direction; And
A redundancy word line selectively disposed on even mats of the mats constituting the mat row;
And said redundancy word line is configured to replace a defect of any of said even mat and an odd mat adjacent to said even mat.

The method of claim 5, wherein
And a plurality of even mat driving circuit parts installed corresponding to each of the even mats and controlling the even mats.

The method according to claim 6,
The even-matte driving circuit unit may include an address decoding signal including mat position information, a redundancy determination signal according to defect information of the even-numbered mat, and a redundancy determination signal according to defect information of one of the even-numbered and other adjacent mats. Accordingly enabled, and outputting a signal for selecting the mat block.

The method of claim 7, wherein
The semiconductor integrated circuit device further comprises a dummy mat outside the first mat of the plurality of mats constituting the mat row.

A mat row composed of a plurality of mats arranged in a row direction; And
A plurality of redundancy word lines selectively disposed on odd-numbered mats of the mats constituting the mat row;
And the plurality of redundancy word lines is configured to replace a defect of any of the odd-numbered mats and the even-numbered mats adjacent to the odd-numbered mats.

The method of claim 9,
And a plurality of odd mat driving circuit parts disposed corresponding to each of the odd number mats and controlling the odd number mats.

11. The method of claim 10,
The odd-matte driving circuit unit may include an address decoding signal including mat position information, a redundancy determination signal according to defect information of the odd-numbered mat, and a redundancy determination signal according to defect information of one of the even-numbered mats adjacent to the odd-numbered mat. Accordingly enabled, and outputting a signal for selecting the mat block.

A bank comprising an even mat and an odd mat arranged in a column direction;
A row decoding block including an even row decoder installed to correspond to the even mat and an odd row decoder installed to correspond to the odd mat outside the bank;
A dummy mat selectively disposed at the row direction outer edge of the even mat or the row direction outer edge of the odd mat; And
And a plurality of redundancy lines disposed on one of the even mat and the odd mat.

13. The method of claim 12,
When the dummy pad is located outside the even mat,
And the redundancy line is disposed on the even mat.

13. The method of claim 12,
When the dummy pad is located outside the odd mat,
And the redundancy line is disposed on the odd mat.

13. The method of claim 12,
Each of the even-row decoder and the odd-row decoder,
A redundancy determination circuit unit outputting a redundancy determination signal when a defect of a corresponding mat occurs; And
And a mat selection circuit portion for activating a block in which the corresponding mats are arranged.

The method of claim 15,
The mat selection circuit corresponding to the mat on which the plurality of redundancy lines are arranged
A semiconductor integrated circuit driven in response to the address decoding signal specifying the mat position, the redundancy determination signal of the redundancy determination circuit portion of the row decoder, and a redundancy determination signal of the redundancy determination circuit portion of one of the row decoders adjacent to the row decoder. Device.

17. The method of claim 16,
And a mat selection circuit portion corresponding to a mat on which the plurality of redundancy lines are not disposed is driven in response to an address decoding signal specifying the mat position.