KR20130139621A

KR20130139621A - Semiconductor integrated circuit

Info

Publication number: KR20130139621A
Application number: KR1020120063244A
Authority: KR
Inventors: 이두찬; 양종열
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2012-06-13
Filing date: 2012-06-13
Publication date: 2013-12-23

Abstract

Technology relates to a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a plurality of mat groups which are composed of a plurality of mats and are located on the same row and a pair of external sub word line drivers which are arranged between the adjacent mat groups to control the corresponding mat group.

Description

Semiconductor Integrated Circuits

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a high speed semiconductor memory device.

As the operating speed of processors increases, there is a need for semiconductor memory devices with higher access speeds. As a memory device used with a processor, a dynamic random access memory (DRAM) is typically used, and a DRAM may be configured as an array of individual memory cells.

The memory cell array may include a plurality of rows (word lines) and columns (bit lines), and capacitors are connected at intersections of rows and columns.

In general, in a write operation, data is stored in a capacitor, and in a read operation, when data is read from a memory cell, an amount of charge stored in the capacitor is sensed to estimate a logic state of the memory cell. At this time, the charges of the capacitors may leak, and thus the DRAM device requires a refresh operation.

In a typical DRAM, refresh, read, and write operations may be performed simultaneously on cells in one row. This data can be refreshed, read and written by activation of the word line. By activation of the word line, all the memory cells in the row are substantially connected to the bit line.

It is urgent to reduce the processing speed of memory devices such as DRAM. In order to improve DRAM access speed and cycle time, it is important to reduce the word line length and the number of word lines per memory cell array. In other words, the capacitance load caused by the word line is reduced.

Accordingly, a technique of controlling memory cells in groups by arranging memory cells of the DRAM in operation units called "banks" has been widely adopted. Furthermore, in order to reduce power consumption, a stack bank in which two banks are arranged in succession and set to drive simultaneously is used.

However, in the stack bank structure, since word lines of consecutively arranged banks are activated at the same time during word line activation, there is a problem in that the word lines are unnecessarily driven.

The present invention provides a semiconductor integrated circuit device capable of preventing unnecessary word line driving.

A semiconductor integrated circuit device according to an embodiment of the present invention includes a plurality of mats each composed of a plurality of mats, and disposed to control the mat group between the mat groups located on the same row and the mat group adjacent to each other. Includes a pair of external sub word line drivers.

In addition, a semiconductor integrated circuit device according to another embodiment of the present invention may include a peripheral region, a plurality of bank groups disposed above and below the peripheral region, a plurality of banks respectively provided in the plurality of bank groups, and A row decoder block disposed in each bank group, the row decoder block being positioned between the banks so that two banks are shared, each bank including a plurality of mat rows in which a plurality of mats are arranged along a row; Is divided into a plurality of mat groups including the predetermined mats, and a sub word line controlling the mat group is continuously disposed between the plurality of mat groups.

Further, according to another embodiment of the present invention, a plurality of mats disposed on the same row, and a bank including a sub word line driver positioned between the plurality of mats, the sub word line driver is selected mats Two are arranged in succession, and the mats are divided and driven individually based on the two consecutively arranged sub word line drivers.

According to the present invention, the word lines of the mats constituting the mat row can be controlled by dividing into groups or driven collectively, thereby reducing unnecessary word line driving. In addition, since the word lines can be grouped and collectively controlled, data output can also be diversified.

1 is a plan view of a semiconductor integrated circuit device showing a bank structure according to an embodiment of the present invention.
2 is a plan view illustrating an internal configuration of a bank according to an exemplary embodiment of the present invention.
3 is a plan view illustrating a part of a mat row and a corresponding row decoder according to an embodiment of the present invention.
4 is an internal block diagram of a row decoder according to an embodiment of the present invention.
5 is a circuit diagram illustrating a sub word line driver according to an exemplary embodiment of the present invention.
6 and 7 are block diagrams for explaining the driving of the mat selection unit according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like numbers refer to like elements throughout the specification.

Referring to FIG. 1, the semiconductor integrated circuit device 100 may include a plurality of bank groups BG0 and BG1 and a peripheral region 110.

The plurality of bank groups BG0 and BG1 include an upper bank group BG0 and a lower bank group BG1, and the upper bank group BG0 and the lower bank group BG1 have a peripheral area 110 therebetween. It is arranged symmetrically. The upper bank group BG0 may include a first upper bank group BG0_a and a second upper bank group BG0_B, and the lower bank group BG1 may include the first lower bank group BG1_a and the second lower bank. It may include a group BG1_b. Here, the first and second upper bank groups BG0_a and BG0_b and the first and second lower bank groups BG1_a and BG1_b may have the same structure, respectively. Hereinafter, the unit bank group will be described.

The unit bank groups BG0_a, BG0_b, BG1_a, and BG1_b may include a plurality of banks 120. The plurality of banks 120 constituting the unit bank groups BG0_a, BG0_b, BG1_a, and BG1_b may be arranged side by side in the extending direction of the peripheral area 110. In the present embodiment, the unit bank groups BG0_a, BG0_b, BG1_a, and BG1_b may include four banks 120 arranged side by side. In addition, the bank 120 of the present embodiment may include, for example, 256M memory cells.

In addition, the unit bank group BG0_a, BG0_b, BG1_a or BG1_b may include a row decoder block 130A positioned between the banks 120. The row decoder block 130 is located between the first bank 120a and the second bank 120b and between the third bank 120c and the fourth bank 120d, so that the two banks 120 are one. The row decoder 130 may be shared. Accordingly, the second and third banks 120b and 120c are disposed continuously.

In addition, the row decoder 130 provides a main word line control signal and a sub word line control signal to a sub word line driver (not shown) of a corresponding bank, and the bit line equalization signal and sense to a sense amplifier. Can provide an amplifier control signal. Reference numeral 140 denotes a column decoder, and like the row decoder 130, the column decoder 140 may be arranged one per two banks.

As shown in FIG. 2, the bank 120 may include a plurality of mats 150. Since the plurality of mats 150 may be arranged in a matrix form, the bank 120 may be divided into a plurality of mat rows MAT_row and a plurality of mat columns MAT_col.

3 shows a part of the mat row MAT_row and the corresponding row decoder 130 according to the present embodiment. The mat row MAT_row of FIG. 3 will show one selected mat row MAT_row of the first bank 120a as an example. In addition, the row decoder 130 is a unit circuit unit constituting the row decoder block 130A and is provided corresponding to a mat row MAT_row.

Referring to FIG. 3, the mat row MAT_row may be disposed on one side of the row decoder 130. That is, as described above, since the banks 120a and 120b are located at both sides of the row decoder 130, the mat row MAT_row of the first bank 120a is disposed at one side of the row decoder 130. Done.

The mat row MAT_row may include a plurality of mats 200 arranged side by side on the same row, and in this embodiment, the mat row MAT_row may include a total of eight mats 200. Each mat 200 may include a plurality of word lines (not shown) extending in the x direction and a plurality of bit lines (not shown) extending in the y direction, respectively, between the word lines and the bit lines. Memory cells (not shown) may be provided. Also, a sub word line driver SWD for driving a sub word line may be positioned at both edges of the edge of the mat 200 that meet the word line, and a sense amplifier may sense bit line data at both edges of the mat 200. (S / A) may be located. In addition, a sub hole S / H in which an input / output switch is formed may be positioned at a corner portion where the sub word line driver SWD and the sense amplifier S / A meet.

In addition, in the present embodiment, one mat row MAT_row constituting one bank 120 may be grouped by a plurality of mats, and may be controlled for each group.

That is, the mats 200a-200h constituting one mat row MAT_row are, for example, a first mat group MG1 composed of first to fourth mats 200a, 200b, 200c, and 200d. The second mat group MG2 may be divided into fifth to eighth mats 200e, 200f, 200g, and 200h. The division of the first mat group MG1 and the second mat group MG2 may be classified into a sub word line driver SWD. In more detail, the sub word line for controlling the mats 200a-200d of the first mat group MG1 on both sides of the mats 200a-200d constituted by the first mat group MG1 is described. The driver SWD is provided, and similarly, the mats 200e-200h configured as the second mat group MG2 are also controlled on both sides of the mats 200e-200h configured as the second mat group MG2. A sub word line driver SWD is provided. Accordingly, the first word group driver word word driver SWD and the second word group driver word word driver SWD are continuously disposed at the boundary between the first and second mat groups MG1 and MG2. The first and second mat groups MG1 and MG2 may be divided.

The row decoder 130 may include first to fourth mat driving circuit parts 132a to 132d, a fuse part 134, and a mat selector 136.

The fuse unit 134 may be positioned at the center of the row decoder 130, and the first and second mat driving circuit units 132a and 132b may be located at one side (the first bank side) of the fuse unit 134. The third and fourth mat driving circuit parts 132c and 132d may be disposed in the row decoder 130 on the other side (the second bank side) of the fuse part 134.

The first mat driving circuit unit 132a is configured to provide a main word line selection signal and a sub word line control signal to each sub word line driver SWD of the first mat group MG1 of the first bank 120a. The second mat driving circuit unit 132b is configured to provide a main word line selection signal and a sub word line control signal to each sub word line driver SWD of the second mat group MG2 of the first bank 120a. Similarly, the third mat driving circuit section 132c is configured to provide a main word line selection signal and a sub word line control signal to each sub word line driver of the first mat group (not shown) of the second bank (not shown). And a fourth mat driving circuit section 132d is configured to provide a main word line selection signal and a sub word line control signal to each sub word line driver of the second mat group of the second bank. Here, the first to fourth mat driving circuit parts 132a to 132d may all have the same configuration.

The fuse unit 134 may include a first fuse circuit unit FUSE1 and a second fuse circuit unit FUSE2. For example, the first fuse circuit unit FUSE1 may be a redundancy circuit unit of the first bank 120a. The second fuse circuit unit FUSE2 may be a redundancy circuit unit of a second bank (not shown).

The mat selection unit 136 is disposed between the first fuse circuit unit FUSE1 and the second fuse circuit unit FUSE2, so that either the first bank 120a or the second bank 120b and the first and the selected banks are selected. One of the second mat groups MG1 and MG2 is selected.

4 shows a block diagram of a row decoder 130 according to an embodiment of the present invention.

Referring to FIG. 4, the row decoder 130 includes the mat selector 136 and the first to fourth mat driving circuits 132a-132d as described above.

The mat selector 136 receives the bank select signal BS and the data select signal DS. The mat selector 136 selects one of the adjacent first and second banks 120a and 120b according to a signal combination of the bank select signal BS and the data select signal DS, and corresponds to the first corresponding one. The mat enable signal MATen is provided to at least one of the fourth to fourth mat driving circuits 132a to 132d.

At least one of the first to fourth mat driving circuits 132a to 132d to which the activated mat enable signal MATen is input may receive a main word line signal MWLB and a sub word line driving signal FXB. Optionally provided to the sub word line drivers SWD of the groups MG1 and MG2, preferably the mat groups MG1 and MG2. In this case, the first and second mat groups MG1 and MG2 may share the same main word line signal MWLB, and the sub word line driving signal FXB may be separately provided.

The sub word line driver SWD includes an inverter In and a keeper transistor N, as shown in FIG. 5. The inverter In switches the inverted sub word line driving voltage FX in response to the main word line signal MWLB. The keeping transistor N is connected to an output terminal of the inverter In and maintains an output voltage of the inverter in response to the sub word line driving signal FXB.

The mat selector 136 of the row decoder 130 according to the present invention receives the bank selection signal BA and determines whether the first bank 120a or the second bank 120b is active. Next, the mat selector 136 provides an activated mat enable signal MATen to at least one of the mat driving circuits 132a-132d of the banks 120a or 120b that are activated.

As shown in FIG. 6, when the 4-bit data input / output is determined by the data select signal DS level, the mat selector 136 may drive the first mat of the first bank 120a. Only the circuit unit 132a provides the activated mat enable signal MATen. Then, the first mat driving circuit unit 132a is selectively operated to provide the main word line signal MWLB and the sub word line control signal FXB to the first mat group MG1 of the first bank 120a. do. Accordingly, only four mats 200a-200d of the mat rows MAT_row are driven to input and output 4-bit data in one unit.

On the other hand, when the 8-bit data input and output is determined by the level of the data selection signal DS, as shown in FIG. The active mat enable signal MATen is provided to both of the second mat driving circuits 132a and 132b. Accordingly, the first and second mat driving circuits 132a and 132b may provide the main word line signal MWLB and the sub word line control signal FXB to the first and second mat groups MG1 and MG2, respectively. do. Accordingly, all the mats constituting the mat row MAT_row, for example, all eight mats 200a-200h are driven to input and output 8-bit data in one unit.

In the present embodiment, the case in which the first bank 120a is selected has been described as an example. However, this is only an example for describing the matte driving, and the case in which the second bank 120b is selected may be equally applied.

According to the present exemplary embodiment, since word lines of the mats constituting the mat row MAT_row can be controlled by dividing into groups or driven collectively, unnecessary word line driving can be reduced. In addition, since the word lines can be grouped and collectively controlled, data output can also be diversified.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100 semiconductor integrated circuit device 110 peripheral area
120: bank 130: low decoder
200: matte

Claims

A plurality of mat groups each composed of a plurality of mats and positioned on the same row; And
And a pair of external sub word line drivers arranged to control the mat group between adjacent mat groups.

The method of claim 1,
And an internal sub word line driver disposed between each mat constituting the plurality of mat groups.

The method of claim 1,
The plurality of mat groups located on the same row constitute a unit mat row of a bank,
And a row decoder on one side of the unit mat row for controlling the unit mat row.

The method of claim 3, wherein
Wherein the row decoder comprises:
A mat selector configured to generate a mat enable signal for selecting the plurality of mat groups according to a bank select signal and a data select signal; And
And a plurality of mat driving circuits driving the mat group according to the activation of the mat enable signal.

5. The method of claim 4,
And the plurality of mat driving circuit units are provided in a number corresponding to the plurality of mat groups.

5. The method of claim 4,
The mat selector is configured to provide an activated mat enable signal to one mat group or to provide an activated mat enable signal to all of the plurality of mat groups according to the level of the data select signal. .

The method of claim 3, wherein
The unit mat row includes two mat groups,
Each mat group is configured to include four mats.

Peripheral area;
A plurality of bank groups disposed above and below the peripheral area;
A plurality of banks each provided in the plurality of bank groups;
A row decoder block disposed in the bank group and positioned between the banks so as to share two banks;
Each bank comprising a plurality of mat rows in which a plurality of mats are arranged along the row,
The mat row is divided into a plurality of mat groups including the predetermined mats,
And a plurality of sub word lines for controlling the mat group in succession between the plurality of mat groups.

The method of claim 8,
And the sub word line driver disposed between the mats forming the plurality of mat groups.

The method of claim 8,
The plurality of bank groups includes first and second upper bank groups and first and second lower bank groups,
And the first and second upper bank groups and the first and second lower bank groups are configured to include first to fourth banks, respectively.

11. The method of claim 10,
And the row decoder block is located between the first and second banks and between the third and fourth banks, respectively.

The method of claim 11,
The mat row is divided into two mat groups,
Each of the mat groups is configured to include first to fourth mats.

The method of claim 9,
The row decoder block includes a row decoder installed corresponding to the mat row.
Wherein the row decoder comprises:
A mat selector for selecting one of adjacent banks according to a bank select signal and a data select signal and providing a mat enable signal in the mat group in a corresponding mat row of the selected bank; And
And a plurality of mat driving circuits for driving the mat in the mat group according to the activation of the mat enable signal.

The method of claim 13,
The mat selector is configured to provide an activated mat enable signal to one mat group or to provide an activated mat enable signal to all of the plurality of mat groups according to the level of the data select signal. .

A plurality of mats disposed on the same row;
A bank including a sub word line driver positioned between the plurality of mats,
And two sub word line drivers disposed consecutively between selected mats so that the mats are separately driven based on the two consecutive sub word line drivers.