KR20130140413A - Semiconductor device - Google Patents

Abstract

The semiconductor device in an embodiment of the present invention includes a substrate, a buffer layer on the substrate, a device layer including a doped semiconductor compound and arranged on the buffer layer, a first middle layer including an undoped semiconductor compound, applying a stress to the device layer, and arranged between the buffer layer and the device layer, and a second middle layer including AlyGa1-yN (here, 1 < y < 1), partly attenuating the stress from the first middle layer to the device layer, and arranged between the first middle layer and the device layer. [Reference numerals] (10) Substrate;(22) Initial buffer layer;(24) Transition layer;(30) First middle layer;(40) Second middle layer;(50) Device layer

Description

Semiconductor device

Embodiments relate to semiconductor devices.

III-V compound semiconductors such as GaN are widely used in optoelectronics due to their many advantages such as wide and easy-to-adjust bandgap energy. Such GaN is usually grown on a sapphire substrate or a silicon carbide (SiC) substrate. Such a substrate is not suitable for a large diameter, and in particular, a SiC substrate is expensive.

Fig. 1 is a view showing a general semiconductor device, which is composed of a substrate 5 and an n-type GaN layer 7. Fig.

In order to solve the above-mentioned problems, a silicon substrate 5 which is cheaper than a sapphire substrate or a silicon carbide substrate, has a large diameter, and has excellent thermal conductivity, is used. However, since the lattice mismatch between GaN and silicon is very large and the thermal expansion coefficient difference therebetween is very large, the melt-back, crack, pit, , Surface morphology defects, and the like.

For example, cracks may be caused by a tensile strain occurring during cooling of the n-type GaN layer 7 grown at a high temperature. Further, when a buffer layer (not shown) such as AlN is formed on the silicon substrate 5, pits may be generated due to the growth temperature of AlN, large lattice mismatch between silicon and AlN.

For the reasons stated above, there is a demand for a semiconductor device having a structure capable of providing good characteristics that does not cause such problems even if the silicon substrate 5 is used.

The embodiment provides a semiconductor device having good crystallinity, preventing cracks, improving surface morphology, and having a thick n-type GaN.

The semiconductor device of the embodiment includes a substrate; A buffer layer on the substrate; An element layer disposed on the buffer layer and including a doped semiconductor compound; A first intermediate layer disposed between the buffer layer and the device layer and applying a stress to the device layer and including an undoped semiconductor compound; And Al _y Ga _1-y N (where 1 <y <1) disposed between the first intermediate layer and the device layer to attenuate a portion of the stress applied from the first intermediate layer to the device layer. And a second intermediate layer. Here, stress means compressive stress.

The substrate may be a silicon substrate having a (1111) crystal plane as a main surface. For example, y is 0.6 to 0.8, and the thickness of the second intermediate layer may be 15 nm to 25 nm.

The buffer layer may further include an initial buffer layer on the substrate; And a transition layer disposed between the initial buffer layer and the first intermediate layer.

The device layer may include a light emitting structure, and the light emitting structure may include a first conductivity type semiconductor layer; An active layer on the first conductivity type semiconductor layer; And a second conductivity type semiconductor layer disposed between the active layer and the second intermediate layer.

A semiconductor device according to another embodiment includes a conductive support substrate; A first conductivity type GaN layer on the conductivity type support substrate; An active layer on the first conductive semiconductor layer; A second conductivity type GaN layer on the active layer; An Al _y Ga _1-y N (where 1 <y <1) layer on the second conductivity type GaN layer; And GaN undoped on the Al _y Ga _1-y N layer.

The semiconductor device may further include a reflective layer disposed between the conductive support substrate and the first conductive GaN layer. For example, the first conductivity type may be p-type, and the second conductivity type may be n-type.

Since the second intermediate layer of the semiconductor device according to the embodiment is formed at a high temperature of 1000 ° C. to 1100 ° C., the crystallinity is improved to prevent the occurrence of cracks, and since Ga is added to the second intermediate layer, the surface morphology is increased. It is further improved, and since the compressive stress to the device layer can be controlled by the second intermediate layer, the device layer, for example, n-type GaN can be formed thicker.

1 is a view showing a general semiconductor device.
2 shows a cross-sectional view of a semiconductor device according to an embodiment.
3A to 3D are cross-sectional views illustrating a method of manufacturing the semiconductor device illustrated in FIG. 2.
4 is a cross-sectional view of a semiconductor device according to an embodiment in which a vertical light emitting device is implemented using the semiconductor device illustrated in FIG. 2.
5A through 5C are cross-sectional views illustrating a method of manufacturing the semiconductor device in accordance with the embodiment illustrated in FIG. 4.
6 is a graph showing the full width at half maximum when the second intermediate layer is formed at a low temperature and when formed at a high temperature.
7A and 7B are views of an n-type GaN layer when the n-type GaN layer illustrated in FIG. 4 has a thickness of 2.5 μm.
FIG. 8 is a cross-sectional view of a semiconductor device according to an embodiment implementing a HEMT using the semiconductor device illustrated in FIG. 2. FIG.
9 is a cross-sectional view of a light emitting device package according to an embodiment.
10 is a perspective view of a lighting unit according to an embodiment.
11 is an exploded perspective view of a backlight unit according to an embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the embodiment according to the present invention, in the case of being described as being formed on the "upper" or "on or under" of each element, on or under includes both elements being directly contacted with each other or one or more other elements being indirectly formed between the two elements. Also, when expressed as "on" or "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. In addition, the size of each component does not necessarily reflect the actual size.

Fig. 2 shows a cross-sectional view of the semiconductor device 100A according to one embodiment.

The semiconductor device 100A illustrated in FIG. 2 includes a substrate 10, a buffer layer 20, a first intermediate layer 30, a second intermediate layer 40, and a device layer 50.

The substrate 10 may be a silicon substrate having a (111) crystal plane as a principal plane.

The buffer layer 20 is disposed on the substrate 10 and may include an initial buffer layer 22 and a transition layer 24. The initial buffer layer 22 may include at least one of AlN, AlAs, and SiC. When the initial buffer layer 22 has a threshold thickness or more, diffusion of silicon atoms from the silicon substrate 10 may be prevented, and melt-back may be prevented. Here, the critical thickness means a thickness at which silicon atoms from the silicon substrate 10 can be diffused. To this end, the initial buffer layer 22 may have a thickness of several tens or hundreds of nanometers, for example, may have a thickness of 10 nm or more and 300 nm or less.

The transition layer 24 is disposed between the initial buffer layer 22 and the first intermediate layer 30. The transition layer 24 may have various types of structures.

For example, transition layer 24 may include at least one of _{AlN / Al x Ga 1-x} N superlattice unit layers. Here, the AlN / Al _x Ga _{1 -x} N superlattice unit layer may be a bi-layer structure composed of an AlN superlattice layer and an Al _x Ga _{1 -x} N superlattice layer. Where 0 <x <1. In the AlN / Al _x Ga ₁ -xN superlattice unit layer, the relative positions of the AlN superlattice layer and the Al _x Ga _{1 -x} N superlattice layer are not limited. For example, AlN super lattice layer may be a member teomcheung (bottom layer) and Al _x Ga _1-x N superlattice layer is tapcheung (top layer) layered on the AlN layer superlattice. Alternatively, in the AlN / Al _x Ga _{1 -x} N superlattice unit layer, the Al _x Ga _{1 -x} N superlattice layer is a buffer layer and the AlN superlattice layer is stacked on the Al _x Ga _{1 -x} N superlattice layer It may also be a top layer.

For example, the transition layer 24 may include a plurality of AlN / Al _x Ga _1-x N superlattice unit layers. At this time, the transition layer 24 has a concentration gradient of Al and Ga according to the distance from the initial buffer layer 22. For example, the plurality of AlN / Al _x Ga _1-x N superlattice unit layers may have a smaller x value as the distance from the initial buffer layer 22 increases.

Alternatively, the transition layer 24 may comprise at least one AlGaN layer.

Alternatively, the transition layer 24 may comprise an AlGaN layer disposed on the initial buffer layer 22 and a GaN layer disposed on the AlGaN layer.

The transition layer 24 described above can induce the lattice constant to gradually transition from the initial buffer layer 22 to the GaN element layer 50 and to apply gradually increasing compressive stress to the GaN element layer 50. [ Therefore, the tensile strain caused from the silicon substrate 10 can be effectively compensated for by the difference in thermal expansion coefficient, and the possibility of cracking can be eliminated, thereby improving the crystallinity. It is also possible to effectively merge the pits caused in the AlN initial buffer layer 22 and reduce the threading dislocation TD to improve the surface morphology of the GaN element layer 50 And the potential is reduced by bending, so that a structure having improved crystallinity from the initial buffer layer 22 to the GaN element layer 50 can be obtained. Furthermore, since the possibility of occurrence of cracks can be eliminated, the mobility of electrons may be increased.

Meanwhile, the first intermediate layer 30 may be disposed on the transition layer 24. The first intermediate layer 30 may apply a compressive stress to the device layer 50 and may include an undoped semiconductor compound. For example, the first intermediate layer 30 may include undoped GaN (hereinafter referred to as "uGaN") as an undoped semiconductor compound. The first intermediate layer 30 serves to recover the deterioration of the crystallinity of the element layer 50 by including a metal such as aluminum (Al) in the initial buffer layer 22 and the transition layer 24.

The second intermediate layer 40 may be disposed on the first intermediate layer 30. The second intermediate layer 40 serves to attenuate excessive compressive stress applied to the device layer 50 from the first intermediate layer 30. To this end, the second intermediate layer 40 may include Al _y Ga _1-y N (where 1 <y <1). For example, y may be 0.6 to 0.8 and the thickness of the second intermediate layer 40 may be 15 nm to 25 nm.

In addition, when the second intermediate layer 40 is formed at a high temperature (HT) of 1000 ° C. to 1100 ° C., the crystallinity and surface morphology of the device layer 50 may be further improved.

The device layer 50 is disposed on the second intermediate layer 40 and may include a doped semiconductor compound. For example, the device layer 50 may comprise doped GaN.

In example embodiments, the device layer 50 may include a light emitting structure. The light emitting structure may include a first conductive semiconductor layer, an active layer disposed on the first conductive semiconductor layer, and a second conductive semiconductor layer disposed between the active layer and the second intermediate layer 40. This will be described in more detail below.

Hereinafter, a method of manufacturing the semiconductor device 100A illustrated in FIG. 2 will be described with reference to FIGS. 3A to 3D. In this example, the substrate 10 is a silicon substrate, the initial buffer layer 22 includes AlN, the transition layer 24 includes AlGaN, and the first intermediate layer 30 includes uGaN. However, it goes without saying that the semiconductor device 100A exemplified in Fig. 2 may be manufactured by various other methods without being limited to the method described in this example.

3A to 3D are cross-sectional views illustrating a method of manufacturing the semiconductor device 100A illustrated in FIG. 2.

Referring to FIG. 3A, a silicon substrate 10 is prepared. The silicon substrate 10 is exposed to trimethyl aluminum (TMA) gas in the absence of ammonia (NH ₃ ) gas for 15 seconds to deposit an ultra-aluminum film so that silicon nitride is deposited on the surface of the silicon substrate 10 As shown in Fig. In some cases, a step of removing the native oxide film on the silicon substrate 10 by rapid annealing the silicon substrate 10 to a temperature of, for example, about 900 캜 may be additionally performed. However, the silicon substrate 10 can be prepared in various forms without being limited thereto.

Thereafter, an AlN initial buffer layer 22 having a predetermined thickness is formed on the silicon substrate 10 at a temperature of about 900 캜 while using ammonia (NH ₃ ). At this time, when the thickness of the AlN initial buffer layer 22 increases beyond the crystal thickness, it changes from the three-dimensional growth mode to the two-dimensional growth mode by the fusion of AlN islands. Since the AlN island thus fused can completely cover the silicon substrate 10, diffusion of silicon atoms can be prevented. Alternatively, an AlN initial buffer layer 22 may be formed on the silicon substrate 10 by various methods instead of the above-described method.

Thereafter, as illustrated in FIG. 3B, a transition layer 24 including AlGaN is formed on the AlN initial buffer layer 22.

Thereafter, as illustrated in FIG. 3C, a first intermediate layer 30 including uGaN is formed on the AlGaN transition layer 24.

Thereafter, a high temperature (HT) Al _y Ga _1-y N layer is formed as the second intermediate layer 40 on the first intermediate layer 30 of uGaN as illustrated in FIG. 3D. If the growth temperature of the second intermediate layer 40 is less than 1000 ° C., crystallinity may be lowered. Thus, according to the embodiment, the growth temperature of the second intermediate layer 40 may be a high temperature of 1000 ℃ to 1100 ℃, the growth pressure may be 50 to 100A mBar.

Thereafter, n-type GaN may be formed on the second intermediate layer 40 as the element layer 50.

For example, in the process described above with reference to FIGS. 3A-3D, Ga, Al, and N may be grown by metal organic chemical vapor deposition (MOCVD). That is, a structure including Ga, Al, and N may be formed by MOCVD using a precursor material including trimethyl gallium (TMG), trimethyl aluminum (TMA), and ammonia (NH ₃ ).

Meanwhile, the semiconductor device 100A illustrated in FIG. 2 can be used in various fields. For example, the semiconductor device 100A may be applied to a light emitting device such as a light emitting diode (LED), and may be applied to a horizontal light emitting device and a vertical light emitting device.

4 is a cross-sectional view of a semiconductor device 100B according to an embodiment in which a vertical light emitting device is implemented using the semiconductor device 100A illustrated in FIG. 2.

The semiconductor device 100B implementing the vertical light emitting device illustrated in FIG. 4 includes a conductive support substrate 60, a first conductive semiconductor layer 56, an active layer 54, and a second conductive semiconductor layer 52. And a second intermediate layer 40 and a first intermediate layer 30. Since the first intermediate layer 30 and the second intermediate layer 40 illustrated in FIG. 4 correspond to the first intermediate layer 30 and the second intermediate layer 40 illustrated in FIG. 2, the same reference numerals are used. Detailed description will be omitted. In addition, the light emitting structures 52, 54, 56 and the conductive support substrate 60 illustrated in FIG. 4 correspond to the device layer 50 illustrated in FIG. 2.

Since the conductive support substrate 60 may serve as a first electrode together with an ohmic layer (not shown) and a reflective layer (not shown), a metal having excellent electrical conductivity may be used, Metals with high thermal conductivity can be used because they must be able to dissipate heat sufficiently. Here, since the ohmic layer and the reflective layer are well-known technologies, a detailed description thereof will be omitted. Alternatively, a separate first electrode (not shown) may be disposed under the conductive support substrate 60.

For example, the conductive support substrate 60 may be made of a material selected from the group consisting of molybdenum (Mo), silicon (Si), tungsten (W), copper (Cu), and aluminum (Cu), a copper-tungsten (Cu-W), a carrier wafer (for example, GaN, Si, Ge, GaAs, ZnO, SiGe, SiC, SiGe, Ga ₂ O _3, etc.), and the like.

In addition, the conductive support substrate 60 may have a mechanical strength enough to be separated into separate chips through a scribing process and a breaking process without causing warping of the entire nitride semiconductor have.

The light emitting structures 52, 54, 56 include a first conductive semiconductor layer 56 disposed on the conductive support substrate 60, an active layer 54 disposed on the first conductive semiconductor layer 56, and The second conductive semiconductor layer 52 may be disposed on the active layer 54.

The first conductive semiconductor layer 56 may include a III-V compound semiconductor doped with a first conductive dopant, and may be Al _k In _z Ga _(1-kz) N (0? K? 1, 0? z? 1, 0? k + z? 1). For example, the first conductive semiconductor layer 56 may be formed of at least one selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP . The first conductive dopant may include, but is not limited to, Mg, Zn, Ca, Sr, or Ba as a p-type dopant.

The active layer 54 is a layer in which holes (or electrons) injected through the first conductivity type semiconductor layer 56 and electrons (or holes) injected through the second conductivity type semiconductor layer 52 meet with each other, Which emits light having an energy determined by the energy band inherent to the material constituting the light emitting layer 54.

The active layer 54 may be formed of at least one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum-wire structure or a quantum dot structure . For example, the active layer 54 can be formed by implanting trimethylgallium (TMG) gas, ammonia (NH ₃ ) gas, nitrogen gas (N ₂ ), and trimethyl indium (TMIn) However, the present invention is not limited thereto.

The well layer / barrier layer of the active layer 54 may have any one or more pairs of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs and GaP But is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.

The second conductivity-type semiconductor layer 52 may include a III-V compound semiconductor doped with a second conductivity-type dopant, and In _k Al _z Ga _1-kz N (0 ≦ k ≦ 1, 0 ≦ z ≦ And 1, 0 ≦ k + z ≦ 1). For example, when the second conductivity type semiconductor layer 52 is an n-type semiconductor layer, the second conductivity type dopant may include Si, Ge, Sn, Se or Te as an n-type dopant, but is not limited thereto .

In the above-described light emitting structure, the first conductivity type semiconductor layer 56 is formed of a p-type semiconductor layer and the second conductivity type semiconductor layer 52 is formed of an n-type semiconductor layer. However, the first conductivity type semiconductor layer 56 may be an n-type semiconductor layer, and the second conductivity type semiconductor layer 52 may be a p-type semiconductor layer. That is, the light emitting structure may be implemented as any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure.

In addition, the roughness structure 70 may be provided above the second conductivity-type semiconductor layer 52 in order to increase the luminous efficiency. Roughness structure 70 may be a sawtooth structure, as shown in Figure 4, may be a concave-convex structure, the tooth structure or the concave-convex structure may be arranged periodically or aperiodic.

The roughness structure 70 may be formed only in the first intermediate layer 30 and the second intermediate layer 40 as illustrated in FIG. 4, or, unlike the example illustrated in FIG. 4, may be formed only in the first intermediate layer 30. The first intermediate layer 30, the second intermediate layer 40, and the second conductive semiconductor layer 52 may be formed all over the same.

The second electrode 80 may be formed on the second conductive semiconductor layer 52. The second electrode 80 may be formed of a metal, and may be formed of a reflective electrode material having ohmic characteristics. Layer structure including at least one of aluminum (Al), titanium (Ti), chrome (Cr), nickel (Ni), copper (Cu), and gold (Au).

In addition, a bonding layer (not shown) and an ohmic layer (not shown) may be further disposed between the supporting substrate 60 and the first conductivity-type semiconductor layer 56, which are well known techniques. Omit.

Hereinafter, a method of manufacturing the semiconductor device 100B illustrated in FIG. 4 will be described with reference to FIGS. 3A to 3D and FIGS. 5A to 5C. In this example, the substrate 10 is a silicon substrate, the initial buffer layer 22 comprises AlN, the transition layer 24 comprises AlGaN, the first intermediate layer 30 comprises uGaN, and the first conductivity type. The semiconductor layer 56 includes p-type GaN and the second conductive semiconductor layer 52 exemplifies a case of n-type GaN. However, the semiconductor device 100B illustrated in FIG. 4 may be manufactured by various other methods, without being limited thereto.

5A through 5C are cross-sectional views illustrating a method of manufacturing the semiconductor device 100B illustrated in FIG. 4.

As described above with reference to FIGS. 3A to 3D, the silicon substrate 10, the AlN initial buffer layer 22, the AlGaN transition layer 24, the uGaN first intermediate layer 30, and HT-Al _x Ga _1-x N second intermediate layers 40 are formed.

Thereafter, as illustrated in 5a, the n-type GaN layer, which is the second conductivity-type semiconductor layer 52, the active layer 54, the p-type GaN layer, which is the first conductivity-type semiconductor layer 56, and the conductive support substrate 60. ) Is sequentially formed on the second intermediate layer 40.

Thereafter, as illustrated in FIG. 5B, the silicon substrate 10 is removed by wet etching, and the AlN initial buffer layer 22 and the AlGaN transition layer 24 are removed by dry etching.

The resultant illustrated in FIG. 5B is then reversed to form the roughness structure 70. In this case, unlike illustrated in FIG. 4, the roughness structure 70 illustrated in FIG. 5C is deeply formed over the first intermediate layer 30, the second intermediate layer 40, and the n-type GaN layer 52. It can be seen.

FIG. 6 is a graph showing a full width at half maximum (FWHM) when the second intermediate layer 40 is formed at a low temperature (LT) and at a high temperature. Here, the unit of FWHM is arcsec (degree / 3600), and (002) and (102) represent the plane direction of GaN, respectively.

7A and 7B are views of the n-type GaN layer 52 when the n-type GaN layer 52 illustrated in FIG. 4 has a thickness of 2.5 μm.

Referring to FIG. 6, it is understood that the FWHM is less when the second intermediate layer 40 is formed at a high temperature of 1000 ° C. to 1100 ° C. than when the second intermediate layer 40 is formed at a low temperature (LT) of 800 ° C. to 900 ° C., for example. Can be. Low FWHM gives good crystallinity. Therefore, in the semiconductor devices 100A and 100B according to the embodiment, it can be seen that the crystallinity of the device layer 50 may be improved by forming the second intermediate layer 40 at a high temperature.

In addition, when the second intermediate layer 40 is grown at low temperature, the n-type GaN layer 52 has cracks 72, 74, and 76 as illustrated in FIG. 7A. In contrast, when the second intermediate layer 40 is grown at a high temperature, the n-type GaN layer 52 may be prevented from generating cracks as illustrated in FIG. 7B.

In addition, since the second intermediate layer 40 is formed at a high temperature, the n-type GaN layer 52 can be formed thicker. In general, the thicker the n-type GaN layer 52 in the case of the vertical light emitting device has various advantages. Therefore, the semiconductor device 100B according to the embodiment is usefully applied to the vertical light emitting device as illustrated in FIG. 4.

Hereinafter, the HEMT 100C using the semiconductor element exemplified in Fig. 2 described above will be described with reference to the accompanying drawings as follows. Here, the same reference numerals as those in FIG. 2 denote the same elements, and redundant description thereof will be omitted.

8 is a cross-sectional view of a semiconductor device 100C according to an embodiment in which an HEMT is implemented using the semiconductor device 100A illustrated in FIG. 2.

Referring to FIG. 8, the semiconductor device 100C includes a substrate 10, an initial buffer layer 22, a transition layer 24, a first intermediate layer 30, a second intermediate layer 40, and a device layer 50A. do.

The element layer 50A is an element corresponding to the element layer 50 illustrated in FIG. 2. However, device layer 50A includes channel layer 92, undoped AlGaN (hereinafter referred to as uAlGaN) layer 96, n-type or p-type GaN layer 94, gate G and a plurality of contacts. It consists of (S, D).

The channel layer 92 may be formed to include undoped GaN, and may be disposed on the second intermediate layer 40. The uAlGaN layer 96 is disposed on top of the channel layer 92 through the heterojunction 98. In addition, a gate electrode G, which may be embodied including a material such as gold (Au), is disposed over the uAgAN layer 96.

When the channel formed by the channel layer 92 is an n-type channel, an n-type GaN layer 94 is disposed on both sides of the uAlGaN layer 96 on top of the channel layer 92. However, when the channel formed by the channel layer 92 is a p-type channel, the p-type GaN layer 94 is disposed on both sides of the uAlGaN layer 96 on top of the channel layer 92. The GaN layer 94 is a structure embedded in the channel layer 92.

At least one contact (S, D) is disposed on both sides of the uAlGaN layer 96 on the GaN layer 94. Here, the at least one contact may include a source contact S that may be implemented with Al and a drain contact D that may be implemented with Al. The source contact S is disposed on the GaN layer 94 disposed on the channel layer 92, and the drain contact D is disposed on the GaN layer 94 spaced apart from the source contact D. .

The semiconductor device 100A illustrated in FIG. 2 may include a photodetector, a gated bipolar junction transistor, a gated hot electron transistor, a gated heterostructure a bipolar junction transistor, a gas sensor, a liquid sensor, a pressure sensor, a multi-function sensor such as pressure and temperature, a power switching transistor, (microwave transistor) or a lighting device.

Hereinafter, the configuration and operation of the light emitting device package including the semiconductor device 100B illustrated in FIG. 4 applied to the vertical light emitting device will be described.

9 is a cross-sectional view of a light emitting device package 200 according to an embodiment.

The light emitting device package 200 according to the embodiment includes the package body 205, the first and second lead frames 213 and 214 provided on the package body 205, and the package body 205 A light emitting device 220 electrically connected to the first and second lead frames 213 and 214 and a molding member 240 surrounding the light emitting device 220.

The package body portion 205 may be formed of silicon, synthetic resin, or metal, and may be formed with an inclined surface around the light emitting device 220.

The first and second lead frames 213 and 214 are electrically separated from each other and serve to supply power to the light emitting device 220. The first and second lead frames 213 and 214 may function to increase light efficiency by reflecting the light generated from the light emitting device 220. The heat generated from the light emitting device 220 may be transmitted to the outside It may also serve as a discharge.

The light emitting device 220 may include, but is not limited to, the semiconductor device 100B illustrated in FIG.

The light emitting device 220 may be disposed on the first or second lead frame 213 or 214 or may be disposed on the package body 205 as illustrated in FIG.

The light emitting device 220 may be electrically connected to the first and / or second lead frames 213 and 214 by a wire, a flip chip, or a die bonding method. The light emitting device 220 illustrated in FIG. 9 is electrically connected to the first lead frame 213 and the wire 230 and is electrically connected to the second lead frame 214 in direct contact with the present invention, but is not limited thereto.

The molding member 240 can surround and protect the light emitting device 220. In addition, the molding member 240 may include a phosphor to change the wavelength of light emitted from the light emitting device 220.

A plurality of light emitting device packages according to embodiments may be arranged on a substrate, and a light guide plate, a prism sheet, a diffusion sheet, a fluorescent sheet, or the like may be disposed on a path of light emitted from the light emitting device package. The light emitting device package, the substrate, and the optical member may function as a backlight unit or function as a lighting unit. For example, the lighting system may include a backlight unit, a lighting unit, a pointing device, a lamp, and a streetlight.

10 is a perspective view of a lighting unit 300 according to an embodiment. However, the illumination unit 300 of Fig. 10 is an example of the illumination system, but is not limited thereto.

The illumination unit 300 includes a case body 310, a connection terminal 320 installed in the case body 310 and supplied with power from an external power source, a light emitting module unit 330 installed in the case body 310, ).

The case body 310 is formed of a material having a good heat dissipation property, and may be formed of metal or resin.

The light emitting module unit 330 may include a substrate 332 and at least one light emitting device package 200 mounted on the substrate 332.

The substrate 332 may be a printed circuit pattern on an insulator and may be a printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, or the like .

In addition, the substrate 332 may be formed of a material that efficiently reflects light, or may be formed of a color whose surface is efficiently reflected, for example, white, silver, or the like.

At least one light emitting device package 200 may be mounted on the substrate 332. Each of the light emitting device packages 200 may include at least one light emitting device 220, for example, a light emitting diode (LED). The light emitting diode may include a colored light emitting diode that emits red, green, blue, or white colored light, and a UV light emitting diode that emits ultraviolet (UV) light.

The light emitting module unit 330 may be arranged to have a combination of various light emitting device packages 200 to obtain colors and brightness. For example, a white light emitting diode, a red light emitting diode, and a green light emitting diode may be combined to secure high color rendering (CRI).

The connection terminal 320 may be electrically connected to the light emitting module unit 330 to supply power. In the embodiment, the connection terminal 320 is connected to the external power source by being inserted in a socket manner, but the present invention is not limited thereto. For example, the connection terminal 320 may be formed in a pin shape and inserted into an external power source, or may be connected to an external power source through wiring.

11 is an exploded perspective view of the backlight unit 400 according to the embodiment. However, the backlight unit 400 of FIG. 11 is an example of the illumination system, and the present invention is not limited thereto.

The backlight unit 400 includes a light guide plate 410, a reflective member 420 under the light guide plate 410, a bottom cover 430, a light emitting module unit 440 for providing light to the light guide plate 410 ). The bottom cover 430 houses the light guide plate 410, the reflection member 420, and the light emitting module unit 440.

The light guide plate 410 serves to diffuse light to make a surface light source. The light guide plate 410 is made of a transparent material, and may be made of, for example, acrylic resin such as PMMA (polymethyl methacrylate), polyethylene terephthalate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate As shown in FIG.

The light emitting module unit 440 provides light to at least one side of the light guide plate 410, and ultimately acts as a light source of the display device in which the backlight unit is installed.

The light emitting module 440 may be in contact with the light guide plate 410, but is not limited thereto. Specifically, the light emitting module unit 440 includes a substrate 442 and a plurality of light emitting device packages 200 mounted on the substrate 442. The substrate 442 may be in contact with the light guide plate 410, but is not limited thereto.

The substrate 442 may be a PCB including a circuit pattern (not shown). However, the substrate 442 may include not only general PCB but also metal core PCB (MCPCB), flexible PCB, and the like, but the present invention is not limited thereto.

The plurality of light emitting device packages 200 may be mounted on the substrate 442 such that the light emitting surface on which the light is emitted is spaced apart from the light guiding plate 410 by a predetermined distance.

A reflective member 420 may be formed under the light guide plate 410. The reflective member 420 reflects the light incident on the lower surface of the light guide plate 410 so as to face upward, thereby improving the brightness of the backlight unit. The reflective member 420 may be formed of, for example, PET, PC, PVC resin or the like, but is not limited thereto.

The bottom cover 430 may house the light guide plate 410, the light emitting module 440, the reflective member 420, and the like. To this end, the bottom cover 430 may be formed in a box shape having an opened top surface, but the present invention is not limited thereto.

The bottom cover 430 may be formed of a metal or a resin, and may be manufactured using a process such as press molding or extrusion molding.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

5, 10: silicon substrate 20: buffer layer
22: initial buffer layer 24: transition layer
30: first intermediate layer 40: second intermediate layer
50: device layer 52: second conductivity type semiconductor layer
54: active layer 56: first conductivity type semiconductor layer
60: conductive support substrate 70: roughness structure
100A and 100B: semiconductor device 200: light emitting device package
205: package body portion 213, 214: lead frame
220: light emitting element 230: wire
240: molding member 300: lighting unit
310: Case body 320: Connection terminal
330 and 440 light emitting module units 332 and 442 substrate
400: backlight unit 410: light guide plate
420: reflective member 430: bottom cover
440: Light emitting module section

Claims (9)

Board;
A buffer layer on the substrate;
An element layer disposed on the buffer layer and including a doped semiconductor compound;
A first intermediate layer disposed between the buffer layer and the device layer and applying a stress to the device layer and including an undoped semiconductor compound; And
A part disposed between the first intermediate layer and the device layer to attenuate a portion of the stress applied from the first intermediate layer to the device layer and comprising Al _y Ga _1-y N (where 1 <y <1); 2 A semiconductor device comprising an intermediate layer. The semiconductor device according to claim 1, wherein the substrate is a silicon substrate having a (1111) crystal plane as a main plane. The semiconductor device of claim 1, wherein y is 0.6 to 0.8. The semiconductor device of claim 1, wherein the second intermediate layer has a thickness of 15 nm to 25 nm. The method of claim 1, wherein the buffer layer
An initial buffer layer on the substrate; And
And a transition layer disposed between the initial buffer layer and the first intermediate layer. The method of claim 1, wherein the device layer comprises a light emitting structure,
The light-
A first conductive semiconductor layer;
An active layer on the first conductive semiconductor layer; And
And a second conductivity type semiconductor layer disposed between the active layer and the second intermediate layer. The semiconductor device of claim 1, wherein the stress comprises a compressive stress. A conductive type supporting substrate;
A first conductivity type GaN layer on the conductivity type support substrate;
An active layer on the first conductive semiconductor layer;
A second conductivity type GaN layer on the active layer;
An Al _y Ga _1-y N (where 1 <y <1) layer on the second conductivity type GaN layer; And
Semiconductor device comprising an undoped GaN on the _y N _layer, the Al _y Ga _1. The semiconductor device of claim 8, wherein the first conductivity type is p-type and the second conductivity type is n-type.

Images