KR20130140412A

KR20130140412A - Semiconductor device

Info

Publication number: KR20130140412A
Application number: KR1020120063797A
Authority: KR
Inventors: 장정훈
Original assignee: 엘지이노텍 주식회사
Priority date: 2012-06-14
Filing date: 2012-06-14
Publication date: 2013-12-24

Abstract

The semiconductor device of the embodiment includes a substrate, a buffer layer disposed on the substrate, and a first conductive type semiconductor layer disposed in at least one multilayer structure on the buffer layer, wherein the multilayer structure is formed on the first semiconductor layer and the first semiconductor layer. And a second semiconductor layer having a first conductivity type dopant at a higher concentration than the first semiconductor layer.

Description

Semiconductor device

Embodiments relate to semiconductor devices.

Group III-V compound semiconductors, such as GaN, are widely used in optoelectronics and the like due to their many advantages, including wide and easy-to-adjust bandgap energy. Such GaN is usually grown on a sapphire substrate or a silicon carbide (SiC) substrate. Such a substrate is not suitable for a large diameter, and in particular, a SiC substrate is expensive.

FIG. 1 is a diagram showing a general semiconductor element, and is composed of a silicon substrate 5 and an n-type GaN layer 7.

In order to solve the above-mentioned problems, a silicon substrate 5 which is cheaper than a sapphire substrate or a silicon carbide substrate, has a large diameter, and has excellent thermal conductivity, is used.

For example, in order to implement a light emitting device such as a light emitting diode (LED), an n-type GaN layer 7 may be disposed on the silicon substrate 5. In this case, the lattice mismatch between GaN and silicon is very large, and the coefficient of thermal expansion difference between them is also very large, so that melt-back, crack, and pit deteriorate crystallinity. ), Various problems such as poor surface morphology and the like.

In particular, when doping silicon into the GaN layer as an n-type dopant to form the n-type GaN layer 7 on the silicon cone substrate 5, the n-type GaN layer is different from when the substrate 5 is a sapphire substrate. Tensile strain (tensile strain) occurs in (7) may cause more cracks. In addition, when the GaN layer 7 is formed by using the n-type dopant, there is a problem in that the mobility of electrons is lowered, thereby increasing the driving voltage.

Embodiments provide a semiconductor device that can relieve tensile stress, increase the mobility of electrons to lower the driving voltage, have a thicker conductive semiconductor layer, and reduce the possibility of cracking.

The semiconductor device of the embodiment includes a substrate; A buffer layer disposed on the substrate; And a first conductivity type semiconductor layer disposed on the buffer layer in at least one multilayer structure, wherein the multilayer structure comprises: a first semiconductor layer; And a second semiconductor layer disposed on the first semiconductor layer and having a first conductivity type dopant having a higher concentration than the first semiconductor layer.

The second semiconductor layer may be a delta doped semiconductor layer by a first conductivity type dopant. The doping concentration of the first conductivity type dopant is, for example, 1E19 to 5E19 atoms / cm 3.

The first semiconductor layer may be an undoped semiconductor layer, and may have a first conductivity type dopant diffused from the second conductivity type semiconductor layer. Alternatively, the first semiconductor layer may be a semiconductor layer doped with a first conductivity type dopant at a lower concentration than the second semiconductor layer.

The first conductivity type may be n-type, and the substrate may be a silicon substrate having a (111) crystal plane as a main plane.

For example, the thickness of the first semiconductor layer may be 5 nm to 10 nm, and the thickness of the second semiconductor layer may be 1 nm to 10 nm. The stacked number of the at least one multilayer structure may be 40 to 60. For example, the thickness of the first conductivity-type semiconductor layer may be 50 nm to 100 nm.

Since the semiconductor device according to the embodiment forms a first conductivity type semiconductor layer by including at least one multilayer structure in which an undoped or lightly doped first semiconductor layer and a delta doped second semiconductor layer are stacked, the substrate is formed of silicon. Even if it is used, it is possible to reduce the possibility of tensile stress in the first conductive semiconductor layer, to reduce the occurrence of cracks, to increase the electron mobility to lower the driving voltage, and to have a thick first conductive semiconductor layer. have.

1 is a view showing a general semiconductor device.
2 is a sectional view of a semiconductor device according to an embodiment.
3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment.
4 and 5 are graphs showing concentration change profiles of the first conductive semiconductor layer according to the thickness of the first semiconductor layer.
6 is a graph showing the correlation between carrier concentration and electron mobility.
7 is a cross-sectional view of a vertical light emitting device according to the embodiment.
8 is a cross-sectional view of a horizontal light emitting device according to the embodiment.
9 is a cross-sectional view of a light emitting device package according to an embodiment.
10 is a perspective view of a lighting unit according to an embodiment.
11 is an exploded perspective view of a backlight unit according to an embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the present embodiment, when described as being formed on the "on or under" of each element, the (top) or (bottom) ( on or under includes both that two elements are in direct contact with one another or one or more other elements are formed indirectly between the two elements.

Also, when expressed as "on" or "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

2 is a sectional view of a semiconductor device 100 according to an embodiment.

The semiconductor device 100 illustrated in FIG. 2 includes a substrate 10, a buffer layer 20, an intermediate layer 30, and a first conductivity type semiconductor layer 40.

The substrate 10 may be a silicon (Si) substrate having a (111) crystal plane as its principal plane. For example, the thickness of the silicon substrate 10 may be 100 nm to 200 nm.

The buffer layer 20 is disposed on the substrate 10 and may include at least one of AlN, AlAs, and SiC. When the buffer layer 20 has a threshold thickness or more, diffusion of silicon atoms from the silicon substrate 10 may be prevented and thus meltback may be prevented. Here, the critical thickness means a thickness at which silicon atoms from the silicon substrate 10 can be diffused. To this end, the buffer layer 20 may have a thickness of several tens or hundreds of nanometers, for example, may have a thickness of 10 nm or more and 300 nm or less.

The intermediate layer 30 may be disposed on the buffer layer 20 to impart compressive stress to the first conductive semiconductor layer 40. Therefore, the tensile stress caused from the silicon substrate 10 due to the difference in the coefficient of thermal expansion is effectively compensated, so that a crack may occur in the first conductivity type semiconductor layer 40 disposed on the intermediate layer 30. This is avoided. The crack acts as a trap, and considering the fact that carriers are easily trapped by the trap, the mobility of electrons can be increased because the possibility of crack occurrence is eliminated.

For this purpose, the intermediate layer 30, for example, at least one of _{AlN / Al x Ga 1 - x} N superlattice: may include (SL SuperLattice) unit layer. _{Here, AlN / Al x Ga 1 -} x N superlattice unit AlN layer is a super lattice layer and the Al _x Ga ₁ _- _x N seconds may be a double layer in a grid layer (bi-layer) structure is made. Where 0 <x <1. Alternatively, the intermediate layer 30 may include a plurality of AlGaN layers having different or identical compositions, or may include AlGaN layers and GaN layers that are alternately stacked. Without being limited to this, the intermediate layer 30 may be implemented in various forms.

The thickness of the intermediate layer 30 may be selected to a degree sufficient to prevent bowing of the wafer.

Referring back to FIG. 2, the first conductivity type semiconductor layer 40 is disposed on the intermediate layer 30. In some cases, a low temperature (LT) buffer layer (not shown) including AlN may be further disposed between the intermediate layer 30 and the first conductive semiconductor layer 40.

For example, the first conductivity type may be n type. In this case, the first conductivity type dopant may include Si, Ge, Sn, Se, Te, but is not limited thereto.

According to the present embodiment, the first conductivity type semiconductor layer 40 includes at least one multilayer structure 40A, 40B. For example, the stacked number of the at least one multilayer structure 40A, 40B may be 40 to 60, for example 50.

As illustrated in FIG. 2, each of the multilayer structures 40A and 40B includes a first semiconductor layer 42 and 46 and a second semiconductor layer 44 and 48. First, the second semiconductor layers 44 and 48 will be described, followed by the first semiconductor layers 42 and 46.

The second semiconductor layers 44 and 48 are disposed on the first semiconductor layers 42 and 46 and have a first conductivity type dopant having a higher concentration than the first semiconductor layers 42 and 46. For example, the second semiconductor layers 44 and 48 may be delta doped semiconductor layers by the first conductivity type dopant. Here, delta doping means that a large amount of doping is temporarily concentrated.

The doping concentration of the first conductivity type dopant for forming the second semiconductor layers 44 and 48 may be 1E19 to 5E19 atoms / cm 3.

Next, according to an embodiment, the first semiconductor layers 42 and 46 may be undoped semiconductor layers. In this case, since the first semiconductor layers 42 and 46 are not doped, due to the difference in concentration of the dopant, the first semiconductor layer (from the second semiconductor layers 44 and 48 adjacent to the first semiconductor layers 42 and 46) ( 42 and 46, the first conductivity type dopant is diffused. Therefore, since the first semiconductor layers 42 and 46 have the first conductive dopant diffused, the entire first conductive semiconductor layer 40 may be the first conductive type.

In another embodiment, the first semiconductor layers 42 and 46 may be semiconductor layers doped with a first conductivity type dopant at a lower concentration than the second semiconductor layers 44 and 48. Also in this case, since the first semiconductor layers 42 and 46 are lightly doped than the second semiconductor layers 44 and 48, the first semiconductor layer (from the second semiconductor layers 44 and 48) is changed by the concentration difference of the dopant. 42 and 46, the first conductivity type dopant is diffused.

The thickness T3 of the first conductive semiconductor layer 40 described above may be, for example, 50 nm to 100 nm.

If the thickness T1 of the first semiconductor layers 42 and 46 is too thin, the improvement of electron mobility is insignificant, and the conductivity decreases if the thickness T1 of the first semiconductor layers 42 and 46 is too thick. . In consideration of this, the thicknesses of the first semiconductor layers 42 and 46 may be 5 nm to 10 nm. In this case, the thickness T2 of the second semiconductor layers 44 and 48 may be 1 nm to 10 nm.

Hereinafter, a method of manufacturing the semiconductor device 100 illustrated in FIG. 2 will be described with reference to the accompanying drawings. Here, the substrate 10 includes silicon, the buffer layer 20 includes AlN, and the first semiconductor layers 42 and 46 are undoped GaN (hereinafter, referred to as 'uGaN'). The second semiconductor layers 44 and 48 include delta doped GaN (hereinafter, referred to as 'Si delta doped GaN'), and the first conductivity type is n-type. Assume The semiconductor device 100 shown in FIG. 2 may be manufactured by various other methods without being limited by the manufacturing method described below.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment.

Referring to FIG. 3A, an AlN layer is formed from the buffer layer 20 on the silicon substrate 10, and an intermediate layer 30 is formed on the AlN layer. Thereafter, a uGaN layer 42 is formed on the intermediate layer 30. Thereafter, the first conductive dopant, ie, the n-type dopant, is delta-doped with silicon to form a second semiconductor layer (Si delta doped GaN) 44. In this case, the doping concentration of the first conductivity type dopant may be 1E19 to 5E19 atoms / cm 3.

Subsequently, referring to FIG. 3B, another first semiconductor layer 46 is formed by uGaN on the second semiconductor layer (Si delta doped GaN) 44.

3C, a second semiconductor layer (Si delta doped GaN) 48 is formed by delta doping 52 of silicon as the first conductivity type dopant on the first semiconductor layer 46. The doping concentrations of silicon in forming the second semiconductor layers 44 and 48 may be the same or different. For example, the doping concentration of the first conductivity type dopant for forming the second semiconductor layer 48 may be 1E19 to 5E19 atoms / cm 3.

Hereinafter, the concentration change of the first conductive semiconductor layer 40 according to the thickness of the first semiconductor layers 42 and 46 will be described as follows. At this time, as the first conductivity type dopant, the doping concentration of silicon is 1E19 atoms / cm 3 to form the second semiconductor layers 44 and 48, and the thickness of the second semiconductor layers Si and delta doped GaN 44 and 48 is increased. It was set to 7 nm.

4 and 5 are graphs showing concentration change profiles of the first conductive semiconductor layer 40 according to the thicknesses of the first semiconductor layers 42 and 46. In each graph, the vertical axis represents the first dopant concentration of the first conductivity type semiconductor layer 40, and the horizontal axis represents the depth from the top to the bottom of the semiconductor device. That is, the depth of the top surface of the semiconductor device is '0' and the depth increases toward the bottom.

When the thickness of uGaN, which is the first semiconductor layers 42 and 46, is 14 nm, the first conductivity type semiconductor layer 40 exhibits a concentration profile as illustrated in FIG. In addition, when the thickness of uGaN, which is the first semiconductor layers 42 and 46, is 7 nm, the first conductivity-type semiconductor layer 40 has a concentration profile as shown in FIG. 5.

4 and 5, the thicker the first semiconductor layers 42 and 46 under the same doping concentration when the second semiconductor layers 44 and 48 are formed, the first conductive semiconductor layer. It can be seen that the dopant concentration of 40 becomes small.

Therefore, as the thickness of the first semiconductor layers 42 and 46 becomes thicker, the concentration profile of the first conductivity-type semiconductor layer 40 must be constant by doping at a higher concentration to form the second semiconductor layers 44 and 48. Can be maintained. In addition, when the first semiconductor layers 42 and 46 are formed thick, the electron mobility is further improved. However, as mentioned above, when the thickness of the 1st semiconductor layers 42 and 46 is too large, electroconductivity will fall.

6 is a graph showing the correlation between carrier concentration and electron mobility, where the horizontal axis represents concentration and the vertical axis represents electron mobility.

Referring to FIG. 6, in the case of the conventional semiconductor device illustrated in FIG. 1, the higher the doping concentration of the nGaN layer 7 is, the lower the mobility (■) 120 is. As such, in general, the dopant concentration, which is an impurity, and the mobility of electrons are inversely related.

However, according to the present embodiment, the dopant concentration of the first conductive semiconductor layer 40 including the first semiconductor layers 42 and 46 and the delta doped second semiconductor layers 44 and 48 is 5E18 atoms. It can be seen that when the number / cm 3, the mobility (★) 130 remains constant at 250 cm 2 / Vs.

In the above-described embodiment, the first semiconductor layers 42 and 46, which are undoped or doped at a lower concentration than the second semiconductor layers 44 and 48, are formed under the second semiconductor layers 44 and 48. By being disposed in, the problem that the tensile stress is caused during the formation of the first conductivity-type semiconductor layer 40 can be solved and the occurrence of cracks can be prevented.

In addition, the first semiconductor layers 42 and 46 which are not doped or doped to a lower concentration than the second semiconductor layers 44 and 48 serve as current spreading. This is because the carrier may flow to the first semiconductor layers 42 and 46 and then spread widely to the second semiconductor layers 44 and 48. Therefore, as illustrated in FIG. 6, the mobility of electrons may be larger than that of the semiconductor device illustrated in FIG. 1, and thus, the driving voltage of the semiconductor device 100 may be lowered.

In addition, since the first semiconductor layers 42 and 46 and the second semiconductor layers 44 and 48 have a multilayer structure in which they are alternately stacked, the first conductivity-type semiconductor layer 40 may be thicker. In general, considering that a thick n-type semiconductor layer is required for a vertical light emitting device, if the above-described semiconductor device is applied to a vertical light emitting device, the light emitting device may have excellent light emission efficiency.

The semiconductor device 100 according to the above embodiment may be used for a vertical or horizontal light emitting device.

Hereinafter, vertical and horizontal light emitting devices implemented using the semiconductor device 100 according to the above-described embodiment will be described with reference to the accompanying drawings. The same reference numerals are used for the same parts.

7 is a cross-sectional view of the vertical light emitting device 100A according to the embodiment.

First, a manufacturing method of the vertical light emitting device 100A shown in FIG. 7 will be described.

In order to form the vertical light emitting device 100A using the semiconductor device 100, the active layer 60 and the second conductive semiconductor layer 70 are disposed on the first conductive semiconductor layer 40 illustrated in FIG. 2. ) And the support substrate 80 are sequentially formed. Subsequently, the substrate 10 is removed by wet etching, the buffer layer 20 and the intermediate layer 30 are removed by dry etching, and then reversed, as illustrated in FIG. 7, the first and second electrodes 92 and 94. ).

In the vertical light emitting device, the first conductive semiconductor layer 40, the active layer 60, and the second conductive semiconductor layer 70 shown in FIG. 7 form a light emitting structure.

The first conductivity type semiconductor layer 40 may be formed of a semiconductor compound. It can be implemented with compound semiconductors, such as group III-V, II-VI, and the like, and the first conductive dopant as described above is doped. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1). The first conductive semiconductor layer 40 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP.

The active layer 60 is disposed between the first conductive semiconductor layer 40 and the second conductive semiconductor layer 70. Electrons injected through the first conductivity type semiconductor layer 40 and holes injected through the second conductivity type semiconductor layer 70 meet each other to form energy determined by an energy band inherent in the material forming the active layer 60. Light is emitted.

The active layer 60 may include a single well structure, a multi well structure, a single quantum well structure, a multi quantum well structure (MQW), a quantum-wire structure, or a quantum dot. ) And at least one of the structures. For example, the active layer 60 may be injected with trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn) to form a multi-quantum well structure. It is not limited.

The well layer / barrier layer of the active layer 60 may be formed of one or more pair structures of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, GaP (InGaP) / AlGaP. However, the present invention is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.

A conductive clad layer (not shown) may be formed on or under the active layer 60. The conductive cladding layer may be formed of a semiconductor having a bandgap wider than the bandgap of the barrier layer of the active layer 60. For example, the conductive clad layer may include GaN, AlGaN, InAlGaN, superlattice structure, or the like. In addition, the conductive clad layer may be doped with n-type or p-type.

The second conductivity-type semiconductor layer 70 is disposed between the active layer 60 and the support substrate 80 and may be formed of a semiconductor compound. It may be implemented as a compound semiconductor, such as III-V group, II-VI group, and the second conductivity type dopant may be doped. For example, it may include a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). When the second conductivity type semiconductor layer 70 is a p type semiconductor layer, the second conductivity type dopant may include Mg, Zn, Ca, Sr, Ba, or the like as a p type dopant.

The support substrate 80 illustrated in FIG. 7 is disposed under the second conductive semiconductor layer 70. The support substrate 80 may serve as the second electrode 94 together with an ohmic layer (not shown) and a reflective layer (not shown), so that a metal having excellent electrical conductivity may be used, and is generated during operation of the light emitting device. Since it must be able to dissipate the heat sufficiently, it is possible to use a metal with high thermal conductivity. As such, the second electrode 94 may be omitted, and the support substrate 80 may serve as the second electrode 94.

For example, the support substrate 80 may be made of a material selected from the group consisting of molybdenum (Mo), silicon (Si), tungsten (W), copper (Cu), and aluminum (Al) or alloys thereof. In addition, gold (Au), copper alloy (Cu Alloy), nickel (Ni), copper-tungsten (Cu-W), carrier wafers (e.g. GaN, Si, Ge, GaAs, ZnO, SiGe, SiC, SiGe, Ga ₂ O _3, etc.) may be optionally included.

In addition, the support substrate 80 may have a mechanical strength enough to separate well into separate chips through a scribing process and a breaking process without causing warping of the entire nitride semiconductor.

In addition, a surface grating reflector may be provided on the surface of the first conductivity-type semiconductor layer 40. The surface grating reflector may have a concave-convex structure 90 as shown in FIG. 7, which may be arranged regularly. Alternatively, unlike FIG. 7, the surface grating reflector 90 may be formed in the first conductivity-type semiconductor layer 40 except for the region where the first electrode 92 is formed.

Although the surface grating reflector 90 may be formed directly on the first conductivity type semiconductor layer 40 as shown in FIG. 7, the surface grating reflector 90 may be formed separately from the first conductivity type semiconductor layer 40. It may be formed on the semiconductor layer 40. That is, the surface grating reflector 90 may be made of a material different from that of the first conductivity type semiconductor layer 40 or may be made of the same material as that of the first conductivity type semiconductor layer 40.

If the surface grating reflector 90 is made of a material different from that of the first conductivity type semiconductor layer 40, for example, the surface grating reflector 90 may be made of a material having a refractive index of 1.5 to 2.5. The surface grating reflector 90 may include an oxide and may include, for example, any one of ITO, SiO ₂ , Al ₂ O ₃ , ZnO, TiO ₂ , and a polymer. Alternatively, the material of the surface grating reflector 90 may be an imprint resin or a sol-gel solution in which nanoparticles such as TiO ₂ , ZnO, and Al ₂ O ₃ are dispersed.

The first electrode 92 may be formed on the first conductive semiconductor layer 40 in contact with the surface grating reflector 90. The first electrode 92 may be formed of a metal, and may be formed of a reflective electrode material having ohmic characteristics. Layer structure including at least one of aluminum (Al), titanium (Ti), chrome (Cr), nickel (Ni), copper (Cu), and gold (Au).

In addition, a bonding layer (not shown), a reflective layer (not shown), and an ohmic layer (not shown) may be further disposed between the support substrate 80 and the second conductivity-type semiconductor layer 70. Since it is a conventional technique, detailed description is omitted here.

8 is a cross-sectional view of the horizontal light emitting device 100B according to the embodiment.

The active layer 60A, the second conductive semiconductor layer 70A, and the first and second electrodes 92A and 94A illustrated in FIG. 8 may be formed of the active layer 60 and the second conductive semiconductor layer shown in FIG. 70) and the first and second electrodes 92 and 94, respectively, have the same role, and have the same composition, and thus duplicate description thereof will be omitted herein.

First, a manufacturing method of the horizontal light emitting device 100B illustrated in FIG. 8 will be described.

The active layer 60A and the second conductivity-type semiconductor layer 70A are sequentially formed on the semiconductor device 100 shown in FIG. 2. Thereafter, the first and second conductive semiconductor layers 40 and 70A and the active layer 60A are mesa-etched to expose the first conductive semiconductor layer 40. Subsequently, first and second electrodes 92A and 94A are formed on the second conductive semiconductor layer 70A and the exposed first conductive semiconductor layer 40, respectively.

Hereinafter, the configuration and operation of the light emitting device package including the light emitting device using the semiconductor device 100 described above will be described. Hereinafter, the light emitting device 220 may include the horizontal light emitting device illustrated in FIG. 8, but is not limited thereto.

9 is a cross-sectional view of a light emitting device package 200 according to an embodiment.

The light emitting device package 200 according to the embodiment includes the package body 205, the first and second lead frames 213 and 214 provided on the package body 205, and the package body 205 A light emitting device 220 electrically connected to the first and second lead frames 213 and 214 and a molding member 240 surrounding the light emitting device 220.

The package body portion 205 may be formed of silicon, synthetic resin, or metal, and may be formed with an inclined surface around the light emitting device 220.

The first and second lead frames 213 and 214 are electrically separated from each other and serve to supply power to the light emitting device 220. The first and second lead frames 213 and 214 may function to increase light efficiency by reflecting the light generated from the light emitting device 220. The heat generated from the light emitting device 220 may be transmitted to the outside It may also serve as a discharge.

The light emitting device 220 may be disposed on the first or second lead frame 213 or 214 or may be disposed on the package body 205 as illustrated in FIG.

The light emitting device 220 may be electrically connected to the first and / or second lead frames 213 and 214 by a wire, a flip chip, or a die bonding method. The light emitting device 220 illustrated in FIG. 9 is electrically connected to the first lead frame 213 and the wire 230 and is electrically connected to the second lead frame 214 in direct contact with the present invention, but is not limited thereto.

The molding member 240 can surround and protect the light emitting device 220. In addition, the molding member 240 may include a phosphor to change the wavelength of light emitted from the light emitting device 220.

A plurality of light emitting device packages according to embodiments may be arranged on a substrate, and a light guide plate, a prism sheet, a diffusion sheet, a fluorescent sheet, or the like may be disposed on a path of light emitted from the light emitting device package. The light emitting device package, the substrate, and the optical member may function as a backlight unit or function as a lighting unit. For example, the lighting system may include a backlight unit, a lighting unit, a pointing device, a lamp, and a streetlight.

10 is a perspective view of a lighting unit 300 according to an embodiment. However, the illumination unit 300 of Fig. 10 is an example of the illumination system, but is not limited thereto.

The illumination unit 300 includes a case body 310, a connection terminal 320 installed in the case body 310 and supplied with power from an external power source, a light emitting module unit 330 installed in the case body 310, ).

The case body 310 is formed of a material having a good heat dissipation property, and may be formed of metal or resin.

The light emitting module unit 330 may include a substrate 332 and at least one light emitting device package 200 mounted on the substrate 332.

The substrate 332 may be a printed circuit pattern on an insulator and may be a printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, or the like .

In addition, the substrate 332 may be formed of a material that efficiently reflects light, or may be formed of a color whose surface is efficiently reflected, for example, white, silver, or the like.

At least one light emitting device package 200 may be mounted on the substrate 332. Each of the light emitting device packages 200 may include at least one light emitting device 220, for example, a light emitting diode (LED). The light emitting diode may include a colored light emitting diode that emits red, green, blue, or white colored light, and a UV light emitting diode that emits ultraviolet (UV) light.

The light emitting module unit 330 may be arranged to have a combination of various light emitting device packages 200 to obtain colors and brightness. For example, a white light emitting diode, a red light emitting diode, and a green light emitting diode may be combined to secure high color rendering (CRI).

The connection terminal 320 may be electrically connected to the light emitting module unit 330 to supply power. In the embodiment, the connection terminal 320 is connected to the external power source by being inserted in a socket manner, but the present invention is not limited thereto. For example, the connection terminal 320 may be formed in a pin shape and inserted into an external power source, or may be connected to an external power source through wiring.

11 is an exploded perspective view of the backlight unit 400 according to the embodiment. However, the backlight unit 400 of FIG. 11 is an example of the illumination system, and the present invention is not limited thereto.

The backlight unit 400 includes a light guide plate 410, a reflective member 420 under the light guide plate 410, a bottom cover 430, a light emitting module unit 440 for providing light to the light guide plate 410 ). The bottom cover 430 houses the light guide plate 410, the reflection member 420, and the light emitting module unit 440.

The light guide plate 410 serves to diffuse light to make a surface light source. The light guide plate 410 is made of a transparent material, and may be made of, for example, acrylic resin such as PMMA (polymethyl methacrylate), polyethylene terephthalate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate As shown in FIG.

The light emitting module unit 440 provides light to at least one side of the light guide plate 410, and ultimately acts as a light source of the display device in which the backlight unit is installed.

The light emitting module 440 may be in contact with the light guide plate 410, but is not limited thereto. Specifically, the light emitting module unit 440 includes a substrate 442 and a plurality of light emitting device packages 200 mounted on the substrate 442. The substrate 442 may be in contact with the light guide plate 410, but is not limited thereto.

The substrate 442 may be a PCB including a circuit pattern (not shown). However, the substrate 442 may include not only general PCB but also metal core PCB (MCPCB), flexible PCB, and the like, but the present invention is not limited thereto.

The plurality of light emitting device packages 200 may be mounted on the substrate 442 such that the light emitting surface on which the light is emitted is spaced apart from the light guiding plate 410 by a predetermined distance.

A reflective member 420 may be formed under the light guide plate 410. The reflective member 420 reflects the light incident on the lower surface of the light guide plate 410 so as to face upward, thereby improving the brightness of the backlight unit. The reflective member 420 may be formed of, for example, PET, PC, PVC resin or the like, but is not limited thereto.

The bottom cover 430 may house the light guide plate 410, the light emitting module 440, the reflective member 420, and the like. To this end, the bottom cover 430 may be formed in a box shape having an opened top surface, but the present invention is not limited thereto.

The bottom cover 430 may be formed of a metal or a resin, and may be manufactured using a process such as press molding or extrusion molding.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

5, 10: substrate 20: buffer layer, AlN
30: intermediate layer 40: first conductive semiconductor layer
40A and 40B: laminated structure 42 and 46: first semiconductor layer
44, 48: second semiconductor layer 60, 60A: active layer
70, 70A: Second conductive semiconductor layer 92, 92A, 94, 94A: electrode
100A, 100B, and 220: light emitting device 200: light emitting device package
205: package body portion 213, 214: lead frame
230: wire 240: molding member
300: illumination unit 310: case body
320: connection terminal 330, 440: light emitting module part
332, 442: substrate 400: backlight unit
410: light guide plate 420: reflective member
430: bottom cover 440: light emitting module part

Claims

Board;
A buffer layer disposed on the substrate; And
A first conductivity type semiconductor layer disposed on the buffer layer in at least one multilayer structure,
The multilayer structure
A first semiconductor layer; And
And a second semiconductor layer disposed on the first semiconductor layer and having a first conductivity type dopant having a higher concentration than the first semiconductor layer.

The semiconductor device of claim 1, wherein the second semiconductor layer is a delta doped semiconductor layer by a first conductivity type dopant.

The semiconductor device of claim 2, wherein a doping concentration of the first conductivity type dopant is 1E19 to 5E19 atoms / cm 3.

The semiconductor device of claim 1, wherein the first semiconductor layer is an undoped semiconductor layer and has a first conductivity type dopant diffused from the second conductivity type semiconductor layer.

The semiconductor device of claim 1, wherein the first semiconductor layer is a semiconductor layer doped with a first conductivity type dopant at a lower concentration than the second semiconductor layer.

The semiconductor device of claim 1, wherein the first conductivity type is n-type.

The semiconductor device according to claim 1, wherein the substrate is a silicon substrate having a (111) crystal plane as a principal plane.

The semiconductor device of claim 1, wherein the first semiconductor layer has a thickness of 5 nm to 10 nm.

The semiconductor device of claim 1, wherein the second semiconductor layer has a thickness of about 1 nm to about 10 nm.

The semiconductor device of claim 1, wherein the stacked number of the at least one multilayer structure is 40 to 60.

The semiconductor device of claim 1, wherein the first conductive semiconductor layer has a thickness of 50 nm to 100 nm.