KR20130131074A - Array substrate and method of fabricating the same - Google Patents

Abstract

The present invention provides an array substrate and a manufacturing method including a step of forming a gate wire having a triple-layered structure on a substrate with a pixel area, a second layer of copper, and a third layer of nitrified copper and forming a gate electrode connected to the gate wire; a step of forming a gate insulating film having a single layered structure of oxidized silicon (SiO2) on the gate electrode and the gate wire; a step of forming an etch stopper and an oxide semiconductor layer of an island form, overlapped on the gate insulating film corresponding to the gate electrode; a step of forming a drain electrode and a source electrode touching each end of the oxide semiconductor layer by being separated from each other on the etch stopper and a data wire defining the pixel area by intersecting with the gate wire on the gate insulating film; a step of forming a protective layer having a drain contact hole exposing the drain electrode and formed of the oxidized silicon (SiO2) on the data wire, the source electrode, and the drain electrode; and a step of forming the pixel electrode touching the drain electrode through the drain contact hole on the protective layer. [Reference numerals] (AA) Start

Description

[0001] The present invention relates to an array substrate and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device having an oxide semiconductor layer excellent in device characteristic stability and capable of reducing the number of manufacturing steps.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor (Tr), which is a switching element capable of controlling voltage on and off for each pixel, has a resolution. And it is attracting the most attention because of its ability to implement video.

In such a liquid crystal display, an array substrate including a thin film transistor (Tr), which is essentially a switching element, is configured to remove each of the pixel areas on and off.

FIG. 1 is a cross-sectional view of a portion in which one pixel region is cut including a thin film transistor Tr in a conventional array substrate constituting a liquid crystal display.

As shown in the drawing, a gate electrode may be formed in the switching region TrA in the plurality of pixel regions P defined by crossing a plurality of gate lines (not shown) and a plurality of data lines 33 on the array substrate 11. 15) is formed.

In addition, a gate insulating film 18 is formed on the entire surface of the gate electrode 15, and a semiconductor layer including an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon is sequentially formed thereon. 28 is formed.

In addition, the ohmic contact layer 26 is spaced apart from each other to correspond to the gate electrode 15, and a source electrode 36 and a drain electrode 38 are formed. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45.

At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, the thickness difference (t1 ≠ t2) of the active layer 22, more precisely the source and drain in which the channel layer is formed therein. As the thickness of the thin film transistor Tr is reduced in the portions exposed between the electrodes, deterioration of the characteristics of the thin film transistor Tr occurs.

Therefore, as shown in Fig. 2 (cross section of one pixel region of the array substrate with a thin film transistor Tr having a conventional oxide semiconductor layer), no oxide contact material is required without the need for an ohmic contact layer. A thin film transistor (Tr) having an oxide semiconductor layer 77 having a single layer structure has been developed by using the.

Since the oxide semiconductor layer 77 does not need to form an ohmic contact layer, in order to form an ohmic contact layer spaced from each other made of impurity amorphous silicon, which is a similar material, as in an array substrate having a semiconductor layer made of conventional amorphous silicon. Since it does not need to be exposed to the ongoing dry etching, it is possible to prevent degradation of the characteristics of the thin film transistor (Tr).

On the other hand, in recent years, due to the large area of the display device, the array substrate is gradually increased in area and the wiring is relatively long, resulting in signal delay due to internal resistance. One of the metal materials, copper (Cu), is used.

However, when the wirings and the electrodes, particularly the gate wirings and the gate electrodes are formed of copper, the contact force with silicon oxide, which is best used as an insulating layer in the array substrate, is reduced, and the oxide semiconductor layer is exposed to hydrogen gas (H ₂ ). The characteristics of the thin film transistors react sensitively, resulting in significant differences between the formation positions.

Therefore, to solve this problem, a gate insulating film formed in contact with the gate electrode and the gate wiring made of copper and in contact with the oxide semiconductor layer at the same time is formed as a double layer structure.

That is, the gate layer and the lower layer in contact with the gate electrode of the gate insulating film is formed of silicon nitride to improve the contact force, and the upper layer in contact with the oxide semiconductor layer is silicon oxide instead of silicon nitride containing a lot of hydrogen therein. Formed.

In the protective layer, although the etch stopper is interposed, the oxide layer is formed of silicon oxide to prevent hydrogen from being supplied to the oxide semiconductor layer. In this case, the contact force between the data line and the source and drain electrodes is lowered. Before forming a protective layer made of silicon, a surface treatment process of exposing the surface of the data line and the source and drain electrodes to a plasma using N ₂ as a reaction gas or a plasma using N ₂ O and NH ₃ as a reaction gas is performed. We carry out more.

Therefore, an array substrate using conventional copper as an electrode and a wiring must have a double layer of gate insulating film, and the surface treatment is performed by exposing to N2 plasma or (N ₂ O + NH ₃ ) plasma corresponding to the data wiring and the source and drain electrodes. Since the process to be added, the process time is long and the manufacturing cost is rising.

In addition, the plasma surface treatment requires a separate CVD apparatus because a CVD apparatus capable of forming a plasma is required. Further, since the plasma surface treatment requires additional CVD equipment, the process time is further increased, and productivity per unit time is lowered.

The present invention is to solve the above-mentioned problem, the copper wiring as an excellent bonding force with the insulating film and the oxide semiconductor layer is not affected by hydrogen, the array that can reduce the manufacturing cost without significant difference between the characteristics of the thin film transistor It aims at providing the manufacturing method of a board | substrate.

A method of manufacturing an array substrate according to an exemplary embodiment of the present invention for achieving the above object is characterized in that the pixel region has a triple layer structure on a substrate, and the second layer is made of copper and the third layer is made of copper nitride. Forming a gate wiring and a gate electrode connected thereto; Forming a gate insulating film having a single layer structure made of silicon oxide (SiO ₂ ) on the gate wiring and the gate electrode; Forming an island-type oxide semiconductor layer and an etch stopper on the gate insulating layer to overlap the gate electrode; Forming a source line and a drain electrode on the gate insulating layer, the data line defining the pixel region and the source and drain electrodes spaced apart from each other on the etch stopper and in contact with an end of the oxide semiconductor layer, respectively; Forming a protective layer formed of silicon oxide (SiO ₂ ) over the data line and the source and drain electrodes and having a drain contact hole exposing the drain electrode; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer.

In this case, the data line has the same stacked structure as the gate line, and the first layer, which is a lower layer of each of the gate line, the gate electrode and the data line, and the source and drain electrodes, is made of molybdenum or molybdenum.

The first layer, the second layer, and the third layer may be continuously formed through the same sputtering device, and the third layer may be a target of the second layer in the step of forming the second layer. It is characterized by being formed by flowing nitrogen gas into the sputtering device at the moment of the thickness to proceed sputtering in the nitrogen gas atmosphere.

In the forming of the protective layer having the drain contact hole, the third layer of the drain electrode may be removed to correspond to the drain contact hole to expose the surface of the second layer of the drain electrode.

The oxide semiconductor layer and the etch stopper may be simultaneously formed by one mask process, or the oxide semiconductor layer and the etch stopper may be patterned and formed by two mask processes, respectively.

The oxide semiconductor layer is made of one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO), and the etch stopper is made of silicon oxide (SiO ₂ ).

A method of manufacturing an array substrate according to an exemplary embodiment of the present invention includes: a gate wiring extending in one direction on a substrate on which a pixel region is defined, and a gate electrode connected thereto; A gate insulating film having a single layer structure made of silicon oxide (SiO ₂ ) on the gate wiring and the gate electrode; An oxide semiconductor layer and an etch stopper overlapping the gate insulating layer to correspond to the gate electrode and formed in an island shape; A data line over the gate insulating layer, the data line crossing the gate line to define the pixel area; Source and drain electrodes spaced apart from each other on the etch stopper and in contact with ends of the oxide semiconductor layer, respectively; A protective layer formed over the data line, a source and a drain electrode, and formed of silicon oxide (SiO ₂ ) and having a drain contact hole exposing the drain electrode; And a pixel electrode formed in each pixel area in contact with the drain electrode through the drain contact hole on the passivation layer, wherein the gate wiring, the gate electrode, the data wiring, the source and the drain electrode have a triple layer structure and have a second layer. This copper third layer is characterized by being made of copper nitride.

The second layer of the gate wiring, the gate electrode, the data wiring, the source and the drain electrode is made of molybdenum or molybdenum.

In addition, the drain electrode has a third layer corresponding to the drain contact hole, so that the surface of the second layer of the drain electrode is exposed, and the pixel electrode is in contact with the second layer of the drain electrode.

The oxide semiconductor layer is made of one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO), and the etch stopper is made of silicon oxide (SiO ₂ ).

According to the present invention, the oxide semiconductor layer includes an electrode and a wiring as copper, which is a low-resistance metal material having superior mobility characteristics compared to an array substrate having an amorphous silicon semiconductor layer, and which is cheaper and has excellent conductivity. Even if the area is increased, problems such as signal delay can be suppressed.

In consideration of the poor bonding properties with silicon oxide due to the copper properties, the copper oxide layer is provided on the uppermost layer by introducing an appropriate amount of nitrogen gas in the last step during the copper sputtering process so that the silicon oxide is formed on the single layer of the gate insulating film and the protective layer. Even if the layer is formed, the bonding strength is not a problem, and furthermore, since the gate insulating film is not formed in a double layer structure of silicon nitride and silicon oxide, the material cost is reduced by reducing the material cost.

In addition, the copper layer and the copper nitride layer are continuously made using the same sputtering device, and further, since the equipment does not need to be moved, the process time is shorter than that of nitrogen plasma treatment on the copper surface using the CVD device to improve the conventional bonding force. Effect.

1 is a cross-sectional view of one pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device;
2 is a cross-sectional view of one pixel region of an array substrate having a thin film transistor Tr having a conventional oxide semiconductor layer.
3 is a cross-sectional view of one pixel region of an array substrate having a thin film transistor having an oxide semiconductor layer according to an embodiment of the present invention.
4A through 4M are cross-sectional views of manufacturing steps of one pixel area of an array substrate according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

3 is a cross-sectional view of one pixel area of an array substrate having a thin film transistor having an oxide semiconductor layer according to an embodiment of the present invention. Here, for convenience of description, a portion where the thin film transistor Tr as a switching element is formed in each pixel region P is defined as a switching region TrA.

As shown, the array substrate 101 according to the embodiment of the present invention, the first layer (105a) made of molybdenum (Mo) or molybdenum (MoTi) and pure copper (Cu) on a transparent insulating substrate 101 A plurality of gate wirings (not shown) having a triple layer structure of the second layer 105b made of the third layer 105c and the third layer 105c made of copper nitride (CuNx) extend in one direction.

In addition, the gate electrodes 105 (105a, 105b, 105c) connected to the respective gate wirings (not shown) and having the same triple layer structure as the gate wirings (not shown) are connected to each switching region TrA on the substrate 101. )) Is formed.

A gate insulating film 115 having a single layer structure of silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 101 over the gate wiring (not shown) of the triple layer structure and the gate electrode 105. .

Even though the gate insulating layer 115 forms a single layer structure of silicon oxide (SiO ₂ ), the third layer 105c, which is the uppermost layer of the gate wiring (not shown) and the gate electrode 105, has the silicon oxide (SiO) ratio compared to copper. ₂ ) It is not a problem for the bonding force because it is made of copper nitride (CuNx) excellent in the bonding force with.

In the case of the conventional array substrate (71 in FIG. 2), since the gate wiring (not shown) and the gate electrode (73 in FIG. 2) form a double layer structure and the uppermost layer (73b in FIG. 2) is made of pure copper, silicon oxide by depositing a silicon oxide (SiO ₂₎ after after bonding force between the copper (Cu) is preferentially deposited in a relatively high silicon nitride (SiNx) prior to depositing the silicon oxide (SiO ₂₎ to the bonding strength problem of the (SiO ₂₎ A gate insulating film (75 (75a, 75b) in Fig. 2) having a double layer structure was formed.

However, in the array substrate 101 according to the embodiment of the present invention, the third layer 105c, which is the uppermost layer in the gate wiring (not shown) and the gate electrode 105, has a bonding force with silicon oxide (SiO ₂ ). Since it is made of excellent copper nitride (CuNx), even if the gate insulating film 115 is formed from a single layer of silicon oxide (SiO ₂ ), there is no problem in bonding strength.

Meanwhile, an oxide semiconductor layer 120 is formed in each switching region TrA on the gate insulating layer 115 of the silicon oxide (SiO ₂ ) single layer structure corresponding to the center portion of each gate electrode 105 in an island form. An etch stopper 125 made of silicon oxide (SiO ₂ ) is formed to correspond to the central portion of each oxide semiconductor layer 120.

In addition, a first layer (not shown) made of molybdenum (Mo) or molybdenum (MoTi), a second layer (not shown) made of pure copper (Cu), and copper nitride (CuNx) may be disposed on the gate insulating layer 115. The third layer (not shown) has a triple layer structure, and intersects with the gate line (not shown) to define the pixel region P, and a data line (not shown) is provided.

Further, in each switching region TrA, the first layer 133a and 136a made of molybdenum (Mo) or molybdenum (MoTi) and the same as that of the data line (not shown) are made of pure copper (Cu). It has a triple layer structure consisting of two layers 133b and 136b and a copper nitride (CuNx), and a third layer structure 133c and 136c, spaced apart from each other on the etch stopper 125 and end of the etch stopper 125, respectively. The source electrode 133 and the drain electrode 136 are formed in contact with the ends of the oxide semiconductor layer 120 exposed to the outside. In this case, the source electrode 133 and the data line (not shown) are connected to each other.

The source electrode 133 and the drain electrode 136 spaced apart from the gate electrode 105, the gate insulating layer 115, the oxide semiconductor layer 120, and the etch stopper 125 sequentially stacked in the switching regions TrA. ) Forms a thin film transistor (Tr) that is a switching element.

Next, a protective layer 144 made of silicon oxide (SiO ₂ ) is provided on the thin film transistor Tr and the data line (not shown). In this case, the protective layer 144 is provided with a drain contact hole 148 exposing the drain electrode 136 in each of the switching regions TrA. The drain contact hole 148 is provided with the protective layer ( The second layer 136b made of copper of the drain electrode 136 may be exposed by removing the portion 144c to the third layer 136c of the drain electrode 136.

The drain contact hole 148 is configured to remove the third layer 136c of the drain electrode 136 to expose the second layer 136b. The third layer 136c of copper nitride (CuNx) material may be configured to expose the second layer 136b. ) Is to improve the conductivity of the pixel electrode 170 in contact with the drain electrode 136 through the drain contact hole 148 because the insulating property has substantially no conductive property.

In the array substrate 101 according to an embodiment of the present invention, the protective layer 144 is made of silicon nitride (SiNx), which is an inorganic insulating material and is more excellent in bonding with copper (Cu) than silicon oxide (SiO ₂ ). the formation without forming of a silicon oxide (SiO _2), although the etch stopper 125 is being provided even to the hydrogen (H ₂₎ penetrating into the oxide semiconductor layer 120 by diffusion of hydrogen (H ₂₎ This is to restrain at source.

On the other hand, the third layer 133c, 136c, which is the uppermost layer in the data line (not shown) and the source electrode 133 and the drain electrode 136 having a triple layer structure, is made of a copper nitride (CuNx) material, and thus silicon oxide. An improvement in bonding characteristics with the protective layer 144 of (SiO ₂ ) material will be described.

At this time, in the array substrate 101 of the present invention, the gate wiring (not shown), the gate electrode 105, the data wiring (not shown), the source electrode 133, and the drain electrode 136 have a triple layer structure. The components may appear to be the same or increased compared to the conventional oxide semiconductor layer (77 in FIG. 2) and the array substrate (71 in FIG. 2) wired to copper (Cu), but the manufacturing method is much simplified and this It will be described later in detail through the manufacturing method.

Next, each drain through the drain contact hole 148 as a transparent conductive material indium-tin-oxide (ITO) or indium-ink-oxide (IZO) over the protective layer 144 having the drain contact hole 148. A pixel electrode 170 is formed in contact with the second layer 136b of the electrode 136 and separated for each pixel region.

In the array substrate 101 according to the exemplary embodiment of the present invention, hydrogen (H ₂ ) that generates a significant difference in characteristics of the thin film transistor (Tr) including the oxide semiconductor layer 120 includes the oxide semiconductor layer 120. (SiO ₂ ) is used as an insulating layer (a gate insulating film and a protective layer) in order to fundamentally prevent the penetration into the film), and furthermore, the gate wiring (not shown), the gate electrode 105 and the data wiring (not shown) are used. C) and the third layers 105c, 133c, and 136c, which are uppermost layers of the source electrode 133 and the drain electrode 136, are formed of copper nitride (CuNx) material, thereby forming a silicon oxide formed on top of each of these components. The bonding characteristic with the gate insulating film 115 or the protective layer 144 made of SiO ₂ ) is improved.

Meanwhile, in the case of the array substrate 101 according to the exemplary embodiment of the present invention, only the pixel electrode 170 made of a transparent conductive material is formed on the protective layer 144 so that the array substrate 101 for the twisted nematic mode liquid crystal display device is formed. It is shown as an example.

 When the array substrate 101 forms an array substrate for a transverse electric field type liquid crystal display device, although not shown in the drawing, the pixel electrode has a bar shape in each pixel region P and is spaced at a predetermined interval. A plurality of common wirings having the same triple layer structure on the same layer on which the gate wirings are formed, are spaced apart from the gate wirings, and the protective layer 144 and the gate insulating film 115 are provided on the substrate. A common contact hole is disposed in the common wiring (not shown), and the upper portion of the passivation layer 144 may be in contact with the common wiring through the common contact hole in each pixel area P. A plurality of common electrodes alternate with the bar type pixel electrode may be further formed.

In addition, when the array substrate 101 according to the embodiment of the present invention forms an array substrate for an organic light emitting device, although not shown in the drawing, the pixel electrode 150 having a plate shape in each of the pixel areas P is described above. An organic light emitting layer (not shown) is formed, and a counter electrode (not shown) facing each pixel electrode 150 is further provided thereon, wherein the pixel electrode 150 and the organic light emitting layer (not shown) The counter electrode (not shown) forms an organic light emitting diode (not shown).

Further, a driving thin film transistor (not shown) having the same configuration as that of the thin film transistor Tr provided in the switching region TrA is further provided in each pixel region P, and parallel to the data line. The same layer has the same triple layer structure as that of the data line and is provided with a power line wiring (not shown).

Hereinafter, a method of manufacturing an array substrate according to an embodiment of the present invention having the above-described configuration will be described.

4A through 4M are cross-sectional views illustrating manufacturing processes of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. Here, for convenience of description, a portion where the thin film transistor Tr as a switching element is formed in each pixel region P is defined as a switching region TrA.

First, as shown in FIG. 4A, a transparent insulating substrate 101, for example, a substrate 1041 made of glass or plastic is placed inside a chamber of the sputter device 195, and then molybdenum (Mo) or molybdenum ( MoTi) is deposited to form the first metal layer 104a. Forming preferentially the first metal layer 104a made of molybdenum (Mo) or molybdenum (MoTi) on the substrate 101 may be a medium for improving the bonding strength since the bonding strength between the copper and the substrate 101 is poor. This is to serve as a layer.

The substrate 101 on which the first metal layer 104a is formed may be moved to a chamber having a different target source without being exposed to the outside in the sputter device 195 or may be made of copper (Cu) material in the same chamber. After switching as a target source, sputtering is performed to form a second metal layer 104b made of copper (Cu) on the first metal layer 104a.

Thereafter, as shown in FIG. 4B, nitrogen gas (N ₂ ) is introduced into the chamber when the second metal layer 104b becomes 1000 mm to 3000 mm as an example of a suitable thickness without changing the chamber of the sputter device 195. Is supplied at an appropriate flow rate so that copper (Cu) is deposited in a nitrogen gas (N ₂ ) atmosphere.

The first copper nitride layer 104c made of copper nitride (CuNx) is formed from the point where the nitrogen gas N ₂ flows into the second metal layer 104b by sputtering in the nitrogen gas N ₂ atmosphere. Is formed.

The formation of the first copper nitride layer 104c on the copper second metal layer 104b is to improve the bonding force with the gate insulating film 115 made of silicon oxide (SiO ₂ ).

Therefore, the first metal layer 104a made of molybdenum (Mo) or molybdenum (MoTi) and the second metal layer 104b made of pure copper (Cu) and finally on the substrate 101 by the sputtering process as described above. A first copper nitride layer 104c made of copper nitride (CuNx) is formed.

The first and second metal layers 104a and 140b and the first copper nitride layer 104c are continuously formed in the same sputter device 195 without exposure to the outside or movement between devices.

Therefore, the gate wiring (not shown) and the gate electrode 105 are structurally made of one layer, that is, copper nitride (CuNx) material, compared to an array substrate (71 of FIG. 1) using copper (Cu) as an electrode and a wiring. Although one copper nitride layer 104c is further formed, as described above, the second metal layer 104b and the first copper nitride layer 104c made of copper (Cu) are in the same chamber of the sputter device 195. In practice, the manufacturing process time is virtually no difference.

Next, as shown in FIG. 4C, the first and second metal layers (104a and 104b of FIG. 4B) and the first copper nitride layer (104c of FIG. 4B) are coated with a photoresist, exposed and exposed using an exposure mask. Development of photoresist, a series of unit processes such as etching of the first and second metal layers (104a and 104b in FIG. 4B) and the first copper nitride layer (104c in FIG. 4B), and stripping of the photoresist. The patterning process is performed continuously to form a first layer 105a made of molybdenum (Mo) or molybdenum (MoTi), a second layer 105b made of copper (Cu), and a third layer made of copper nitride (CuNx). A plurality of gate wirings (not shown) having a triple layer structure of the layer 105c and extending in the first direction, and simultaneously connected to the gate wirings (not shown) in the switching region TrA, are the same triple layer structure. The gate electrodes 105 (105a, 105b, 105c) having the same are formed.

At this time, since the third layer 105c of the copper nitride (CuNx) material of the gate wiring (not shown) having the triple layer structure and the gate electrode 105 has an insulating property, substantially the conductive wiring and the electrode It does not play a role but improves the bonding characteristics with the gate insulating film 115 formed thereon.

Next, as shown in FIG. 4D, an oxide that is an inorganic insulating material is formed on the substrate 101 having the triple layer structure and the substrate 101 on which the gate electrode 105 is formed by using a CVD apparatus (not shown). to form the gate wiring (not shown) and gate electrode (105) over the silicon oxide on the front (SiO ₂₎ gate insulating film 115 made of a single layer by depositing silicon (SiO _2).

In the case of the conventional array substrate (71 of FIG. 2), the gate insulating film (75 of FIG. 2) has a double layer structure, and the upper layer (75b of FIG. 2) is made of copper (Cu) material so that the gate wiring and the gate are not shown. In order to improve the bonding force with the electrode (73 in FIG. 2), silicon nitride (SiNx) is first deposited to form a lower layer (75a in FIG. 2), and silicon oxide (SiO ₂ ) is deposited on the upper layer (75b in FIG. 2). Although the gate insulating film (75 in FIG. 2) having a double layer structure was formed by forming a double layer structure), in the case of the array substrate 101 according to the embodiment of the present invention, the third of the gate wiring (not shown) and the gate electrode 105 The layer 105c is made of silicon nitride (SiO ₂ ) and copper nitride (CuNx), which has a much better bonding strength than copper (Cu), so that a single layer of silicon oxide (SiO ₂ ) is formed without forming a lower layer of silicon nitride (SiNx). Bonding even when a gate insulating film 115 is formed It is excellent in terms of force, so it does not cause problems such as falling out of the process later.

Next, as illustrated in FIG. 4E, a zinc oxide (ZnO) -based oxide, for example, indium gallium zinc oxide (IGZO), is formed as an oxide semiconductor material on the gate insulating layer 115 having a silicon oxide (SiO ₂ ) single layer structure. Depositing, or applying one of ZTO (Zinc Tin Oxide) and ZIO (Zinc Indium Oxide) to form an oxide semiconductor material layer 119, and subsequently an inorganic insulating material over the oxide semiconductor material layer 119. For example, silicon oxide (SiO ₂ ) is deposited to form an inorganic insulating material layer 123.

Thereafter, a photoresist is formed on the inorganic insulating material layer 123 to form a photoresist layer 191, and the light transmitting area TA, the blocking area BA, and the light are formed on the photoresist layer 191. After the exposure mask 199 having the transflective area HTA having a transmission amount smaller than the transmission area TA is positioned, the exposure mask 199 is exposed.

In this case, when the photoresist layer 191 is a negative type, a portion that receives light remains during development, and when the positive type, a portion that receives light is removed when developing.

In the drawing, the photoresist layer 191 is shown as an example of a negative photoresist.

In the switching region TrA in each pixel region P, the transmissive region TA corresponds to a portion where an etch stopper (125 in FIG. 4M) is to be formed later, and the outer side of the etch stopper (125 in FIG. 4M). The transflective region HTA corresponds to the portion where the side end portion of the oxide semiconductor layer 120 (in FIG. 4M) exposed is formed, and corresponds to the portion where the other region, that is, the photoresist layer 191 is to be removed. In this case, the exposure mask 199 is positioned above the photoresist layer 191 to correspond to the blocking area BA, and then exposed.

In this case, diffraction exposure or halftone exposure is performed on the characteristics of the exposure mask 199 having the transflective area HTA.

Next, as shown in FIG. 4F, when the photoresist layer 190 subjected to exposure is developed, each of the switching regions TrA corresponds to the transmission area TA of the exposure mask 199. A portion of the first photoresist pattern 191a having a first thickness is formed, and a portion corresponding to the transflective region HTA of the exposure mask 199 has a second thickness that is thinner than the first thickness. The photoresist pattern 191b is formed, and in the portion corresponding to the blocking area BA of the exposure mask 199, the photoresist layer 191 of FIG. 4E is removed to remove the inorganic insulating material layer 123. Exposed.

Next, as shown in FIG. 4G, the inorganic insulating material layer 124 of FIG. 4F and the oxide semiconductor material layer disposed below the inorganic insulating material layer exposed to the outside of the first and second photoresist patterns 191a and 191b ( By etching and removing 119 of FIG. 4F, the oxide semiconductor layer 120 and the inorganic insulating layer having the same planar area and completely overlapping with each other are formed in the shape of the island in the switching region TrA. Pattern 124 is formed.

Next, as shown in FIG. 4H, ashing is performed to remove the second photoresist pattern (191b of FIG. 4G) having the second thickness, thereby removing the inorganic material from the outside of the first photoresist pattern 191a. The upper surfaces of both ends of the insulating pattern 124 are exposed to a predetermined width. In this case, the thickness of the first photoresist pattern 191a is also reduced by ashing, but is still remaining on the center portion of the inorganic insulating pattern 124.

Next, as shown in FIG. 4I, the second photoresist pattern (191b of FIG. 4H) is removed to newly expose the inorganic insulating pattern (124 of FIG. 4H) to the outside of the first photoresist pattern (191a of FIG. 4H). ) By etching to form an etch stopper 125 corresponding to the central portion of the oxide semiconductor layer 120, and at the same time, a predetermined width of both ends of the oxide semiconductor layer 120 outside the etch stopper 125. Expose

In the exemplary embodiment of the present invention, as described above, the mask process is performed once, and the island semiconductor oxide layer 120 is formed in each switching region TrA, and predetermined portions of both ends of the oxide semiconductor layer 120 are disposed thereon. Although it is shown to form the island-shaped etch stopper 125 exposing the width, as an alternative, the island-type oxide is formed through one mask process after forming an oxide semiconductor material layer (119 in FIG. 4E). The semiconductor layer 120 is formed first, and then, an oxide insulating layer is formed by depositing silicon oxide (SiO ₂ ) on the oxide semiconductor layer 120, followed by another mask process for patterning. As a result, an island type etch stopper 125 may be formed on the center portion of the oxide semiconductor layer 120.

Thereafter, the first photoresist pattern (191a of FIG. 4H) remaining on the etch stopper 125 is removed through a strip to expose the etch stopper 125.

Next, as shown in FIG. 4J, the substrate 101 having the etch stopper 125 is positioned inside the sputtering device 196 in the same manner as described above with reference to FIGS. 3A to 3B. Mo or MoTi is deposited to form the third metal layer 132a.

In addition, the target source of the third metal layer 132a is moved to a chamber different from the target source without exposing to the outside in the sputtering device 196 or a target source made of copper in the same chamber. After the change, the fourth metal layer 132b made of copper (Cu) is formed by sputtering.

Subsequently, nitrogen gas (N ₂ ) is supplied as an appropriate flow rate to the inside of the chamber at a time when the fourth metal layer 132b becomes the target thickness, for example, 1000 kPa to 3000 kPa without changing the chamber of the sputtering device 196, thereby providing nitrogen gas. Copper (Cu) is deposited in the (N ₂ ) atmosphere to form a second copper nitride layer 132c on the fourth metal layer 132b.

The third and fourth metal layers 132a and 132b and the second copper nitride layer 132c are also continuously formed in the same sputter device 196 without being exposed to the outside or moving between devices.

Next, as shown in FIG. 4K, the gate insulating layer 115 is patterned by masking the third and fourth metal layers 132a and 132b of FIG. 4J and the second copper nitride layer 132c of FIG. 4J. A first layer (not shown) made of molybdenum (Mo) or molybdenum (MoTi), a second layer (not shown) made of copper (Cu), and a third layer (not shown) made of copper nitride (CuNx) on the phase A data line (not shown) defining the pixel area P is formed to cross the gate line (not shown).

At the same time, in the switching region TrA, first layers 133a and 136a made of molybdenum (Mo) or molybdenum (MoTi) and second layers 133b and 136b made of copper (Cu) and copper nitride (CuNx). The third layer 133c, 136b consisting of a three-layer structure is spaced apart from each other on the etch stopper 125 and the upper surface of the end of the oxide semiconductor layer 120 exposed to the outside of the etch stopper 125, respectively The source electrode 133 and the drain electrode 136 are formed. In this case, the source electrode 133 is formed to be connected to the data line (not shown).

 The gate electrode 105, the gate insulating layer 115, the oxide semiconductor layer 120, the etch stopper 125, and the source electrode 133 and the drain electrode, which are sequentially stacked in the switching region TrA, may be spaced apart from each other. 136 forms a thin film transistor Tr which is a switching element.

Next, as shown in FIG. 4L, silicon oxide (SiO ₂ ), which is an inorganic insulating material, is deposited on the data line (not shown), the source electrode 133, and the drain electrode 136, and is then disposed on the entire surface of the substrate 101. The protective layer 144 is formed.

In this case, the data line (not shown) and the source and drain electrodes 133 and 136 may include the third layers 133a and 136b made of copper nitride (CuNx), which are excellent in bonding strength to silicon oxide (SiO ₂ ). Since it is formed, plasma in a nitrogen gas atmosphere using a CVD apparatus (not shown) as in the manufacture of a conventional array substrate (71 in FIG. 2) before forming the protective layer 144 of silicon oxide (SiO ₂ ) material The surface treatment step of modifying the surface of these components by exposing the data wiring (not shown) and the source and drain electrodes (81 and 83 in Fig. 2) does not need to proceed.

On the other hand, the protective layer 144 is formed of silicon oxide (SiO ₂ ) without forming silicon nitride (SiN x), which is relatively excellent in bonding strength with copper (Cu), when the protective layer is formed of silicon nitride (SiN x). Although the etch stopper 125 made of silicon oxide (SiO ₂ ) is blocked, hydrogen (H ₂ ) from silicon nitride (SiNx) forming a protective layer therein because the etch stopper 125 has a thickness of about 600 kPa to 800 kPa. In order to prevent this from happening because () can be diffused and finally penetrate into the oxide semiconductor layer 120.

When the protective layer 144 is formed of silicon oxide (SiO ₂ ), since hydrogen (H ₂ ) is not included in itself, hydrogen (H ₂ ) penetrates into the oxide semiconductor layer 120 to form a thin film transistor (Tr). The formation of the has the advantage that can be suppressed at the source to generate significant differences by location.

In this case, although the bonding force between the protective layer made of silicon oxide (SiO ₂ ), the data line (not shown), and the source and drain electrodes 133 and 136 may be a problem, in order to improve the bonding force according to the present invention. The array substrate 101 has a second copper nitride layer 132c when the third and fourth metal layers 132a and 132b of FIG. 4J are formed to form the data line (not shown) and the source and drain electrodes 133 and 136. Is simultaneously formed so as to be an intermediate layer for improving the bonding strength between copper (Cu) and silicon oxide (SiO ₂ ).

Subsequently, a mask process is performed on the protective layer 144 to form a drain contact hole 148 exposing the drain electrode 136.

At this time, when the protective layer 144 for forming the drain contact hole 148 is patterned, up to the third layer 136c of copper nitride (CuNx) material in the drain electrode 136 in addition to the protective layer 144. It is preferable to form such that the surface of the second layer 136b of the drain electrode 136 is exposed by being removed. Since the third layer 136c of the copper nitride (CuNx) material has an insulating property among the drain electrode 136 having the triple layer structure, the pixel electrode (170 of FIG. 4M) and the drain electrode 136 formed later may be In order to be electrically connected, the second layer 136b made of copper (Cu) material having conductive properties must be in contact with each other.

Next, as shown in FIG. 4M, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the substrate 101 on the protective layer 140. By forming a conductive material layer (not shown) and performing a mask process, the conductive material layer (not shown) is contacted with the second layer 136b of the drain electrode 136 through the drain contact hole 148 and for each pixel region P. FIG. The array substrate 101 according to the exemplary embodiment of the present invention is completed by forming the separated plate electrode 1170.

On the other hand, the manufacturing method according to the embodiment of the present invention described above until only the step of forming the plate-shaped pixel electrode 170 in each pixel area (P) on the protective layer 144 substantially twisted nematic mode liquid crystal display Although a method of manufacturing an array substrate for an apparatus is provided, it may be variously modified.

That is, when the array substrate 101 forms an array substrate for a transverse electric field type liquid crystal display device, the pixel electrodes have a bar shape in each pixel region P and are formed in a plurality of forms spaced apart at regular intervals. When the gate line (not shown) is formed on the substrate 101, the common wiring (not shown) is spaced apart from each other at the same time, and when the drain contact hole 148 is formed in the protective layer 144. Forming a common contact hole (not shown) that exposes a common wiring (not shown), and contacts the common wiring (not shown) through the common contact hole (not shown) over the protective layer 144 and simultaneously This can be accomplished by forming a plurality of common electrodes (not shown) that alternate with (bar) pixel electrodes (not shown).

In addition, when the array substrate 101 forms an array substrate for an organic light emitting device, a power line (not shown) is formed in parallel with the data line (not shown) and the switching region TrA is formed. In the same manner as forming the thin film transistor Tr, a driving thin film transistor (not shown) having the same structure is formed in each pixel region P, and the organic light emitting layer (not shown) is disposed on the pixel electrode 150 described above. And forming a counter electrode (not shown) facing each of the pixel electrodes 150 on top thereof.

The array substrate 101 according to the embodiment of the present invention manufactured by such a method is provided with the oxide semiconductor layer 120, so that the mobility characteristics are superior to those of the array substrate provided with the semiconductor layer of amorphous silicon, and further, inexpensive. In addition, since the electrode and the wiring are formed of copper (Cu), which is a very low-resistance metal material having excellent conductivity, problems such as signal delay can be suppressed even if the area is large.

In consideration of the poor bonding property with silicon oxide (SiO ₂ ) due to the copper properties, a proper amount of nitrogen (N ₂ ) gas is introduced in the final step during the sputtering of copper (Cu) so that the copper nitride layer is provided on the top layer. Therefore, even when a single layer of silicon oxide (SiO ₂ ) is formed on the gate insulating film 115 and the protective layer 144, the bonding strength is not a problem. Moreover, the copper layer and the copper nitride layer are formed continuously using the same sputtering device. As a result, the process time is shortened compared to the nitrogen plasma treatment on the copper surface by using the CVD apparatus to improve the conventional bonding force, and furthermore, the process time is further shortened because no movement between equipments is required.

In addition, since the gate insulating layer 115 does not have a double layer structure of silicon nitride (SiNx) and silicon oxide (SiO ₂ ), the gate insulating layer 115 has an advantage of reducing material cost and cost.

Meanwhile, the present invention is not limited to the above-described embodiments and modifications, and various changes and modifications are possible without departing from the spirit of the present invention.

101: (array) substrate 105: gate electrode
105a, 105b, 105c: first, second, and third layers (of gate electrodes)
115: gate insulating film 120: oxide semiconductor layer
125: etch stopper 132a: third metal layer
132b: fourth metal layer 132c: second copper nitride layer
196: sputter device P: pixel area
TrA: switching area

Claims (12)

Forming a gate wiring and a gate electrode connected thereto having a triple layer structure on the substrate in which the pixel region is defined, wherein the second layer is made of copper nitride;
Forming a gate insulating film having a single layer structure made of silicon oxide (SiO ₂ ) on the gate wiring and the gate electrode;
Forming an island-type oxide semiconductor layer and an etch stopper on the gate insulating layer to overlap the gate electrode;
Forming a source line and a drain electrode on the gate insulating layer, the data line defining the pixel region and the source and drain electrodes spaced apart from each other on the etch stopper and in contact with an end of the oxide semiconductor layer, respectively;
Forming a protective layer formed of silicon oxide (SiO ₂ ) over the data line and the source and drain electrodes and having a drain contact hole exposing the drain electrode;
Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer;
Wherein the substrate is a substrate.
The method of claim 1,
The data line has the same stacked structure as the gate line, and the first layer, which is a lower layer of each of the gate line, the gate electrode and the data line, and the source and drain electrodes, is made of molybdenum or molybdenum. Manufacturing method.
3. The method of claim 2,
And the first layer, the second layer, and the third layer are continuously formed through the same sputtering device.
The method of claim 3, wherein
And the third layer is formed by injecting nitrogen gas into the sputtering device at a moment when the second layer becomes a target thickness in forming the second layer, and performing sputtering in a nitrogen gas atmosphere. Method of manufacturing a substrate.
The method of claim 1,
The forming of the protective layer having the drain contact hole may include removing the third layer of the drain electrode corresponding to the drain contact hole so that the surface of the second layer of the drain electrode is exposed. .
The method of claim 1,
And the oxide semiconductor layer and the etch stopper are simultaneously formed by one mask process.
The method of claim 1,
And the oxide semiconductor layer and the etch stopper are patterned and formed by two mask processes, respectively.
The method of claim 1,
The oxide semiconductor layer is formed of any one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc oxide (ZIO)
The etch stopper is a method of manufacturing an array substrate, characterized in that consisting of silicon oxide (SiO ₂ ).
A gate wiring extending in one direction on the substrate on which the pixel region is defined and a gate electrode connected thereto;
A gate insulating film having a single layer structure made of silicon oxide (SiO ₂ ) on the gate wiring and the gate electrode;
An oxide semiconductor layer and an etch stopper overlapping the gate insulating layer to correspond to the gate electrode and formed in an island shape;
A data line over the gate insulating layer, the data line crossing the gate line to define the pixel area;
Source and drain electrodes spaced apart from each other on the etch stopper and in contact with ends of the oxide semiconductor layer, respectively;
A protective layer formed over the data line, a source and a drain electrode, and formed of silicon oxide (SiO ₂ ) and having a drain contact hole exposing the drain electrode;
A pixel electrode formed in each pixel area in contact with the drain electrode through the drain contact hole on the passivation layer;
Wherein the gate wiring, the gate electrode, the data wiring, the source and the drain electrode have a triple layer structure, and the second layer is made of copper nitride and the third layer is made of copper nitride.
The method of claim 9,
And the second layer of the gate wiring, the gate electrode, the data wiring, the source and the drain electrode is made of molybdenum or molybdenum.
The method of claim 9,
And the third electrode corresponding to the drain contact hole is removed to expose a surface of the second layer of the drain electrode, and the pixel electrode is in contact with the second layer of the drain electrode.
The method of claim 9,
The oxide semiconductor layer is formed of any one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc oxide (ZIO)
The etch stopper is an array substrate, characterized in that made of silicon oxide (SiO ₂ ).

Images