KR20130121388A - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device which drives a liquid crystal display panel with a dot inversion mode using a source drive direct circuit outputting data voltage so that polarity is reversed with a column inversion mode. The feature of the liquid crystal display device according to the embodiment of the present invention is to comprise; the liquid crystal display which includes data lines, gate lines crossed with the data lines, and a pixel array in which multiple pixels are formed; the source drive direct circuit which supplies the data voltage to the data lines with the column inversion mode so that the polarity is alternately reversed by a predetermined period; a gate driving circuit which sequentially supplies a gate pulse to the gate lines. The pixel array comprises; two sub pixels which are commonly connected to one data line among three sub pixels existing in an identical horizontal line; one sub pixel which is independently connected to the other data line.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display device which drives a liquid crystal display panel in a dot inversion manner by using a source drive integrated circuit which outputs a data voltage such that polarity is inverted in a column inversion manner.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. Liquid crystal displays can be miniaturized compared to cathode ray tubes (CRTs), which are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes.

The liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying a data voltage to the data lines of the liquid crystal display panel, A gate drive IC for supplying a gate pulse (or a scan pulse) to scan lines (or scan lines), a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, and the like.

Due to the process technology of the liquid crystal display device and the breakthrough of the driving technology, the manufacturing cost of the liquid crystal display device is lowered and the image quality is greatly improved. In particular, in order to reduce manufacturing costs, a double rate driving (DRD) technique is provided in which two subpixels existing in one horizontal line are connected to one data line, and a data voltage having the same polarity is supplied to the two subpixels. Proposed.

1 is a view illustrating some pixels of a liquid crystal display panel to which a DRD technology is applied. Referring to FIG. 1, in the DRD technique, two subpixels in one horizontal line are connected to one data line, but each of the two subpixels is connected to a different gate line. As shown in FIG. 1, the first and second sub-pixels P1 and P2 have a jth data (j is a natural number satisfying 1 ≦ j ≦ m, and m is the number of data lines of the liquid crystal display panel). The first sub-pixel P1 is connected to the k-th (k is a natural number satisfying 1≤k≤n, n is the number of gate lines of the liquid crystal display panel) and is connected to the gate line Gk and the second sub-pixel ( P2 is connected to the k-th gate line Gk-1.

DRD technology controls the source drive IC to supply two pixel data voltages on one data line, which greatly reduces manufacturing costs. However, in the DRD technique, since the two subpixels present in one horizontal line are controlled by different gate lines, the number of gate lines is doubled compared with the related art. Therefore, the gate drive IC needs to increase the driving frequency by 2 times than the conventional one to generate the gate pulse. However, in this case, the gate pulse width is reduced by 1/2 times due to the increase of the driving frequency, thereby reducing the data voltage charging period by 1/2 times. When the data voltage charging period is shortened, each pixel of the subpixels is largely affected by the common voltage ripple. Therefore, problems such as image quality distortion and image quality degradation may occur.

The present invention provides a liquid crystal display device which can improve image quality while reducing manufacturing costs.

A liquid crystal display device according to an exemplary embodiment of the present invention includes a liquid crystal display panel including data lines, gate lines crossing the data lines, and a pixel array in which a plurality of sub pixels are formed; A source drive integrated circuit configured to supply data voltages to the data lines such that polarities are alternately alternated every predetermined period in a column inversion manner; And a gate driving circuit which sequentially supplies gate pulses to the gate lines, wherein the pixel array is commonly connected to any one of three subpixels in the same horizontal line. And one subpixel connected to another data line alone.

The present invention forms subpixels so that the neighboring subpixels can be driven in a dot inversion manner in which neighboring subpixels are charged with opposite polarity data voltages even though the source drive IC supplies data voltages of the same polarity for each line. As a result, the present invention can suppress the afterimage of the liquid crystal, flicker, and the like, and can reduce the power consumption of the source drive IC by reducing the number of polarity inversions of the data voltage.

In addition, the present invention controls two sub pixels continuous in the vertical direction using two or three gate lines, or controls four sub pixels continuous in the vertical direction using six or seven gate lines. . As a result, the present invention can increase the data voltage charging period than the DRD technology, thereby reducing the influence of the common voltage ripple. For this reason, the present invention can prevent image distortion and deterioration of image quality, and thus can improve image quality over DRD technology.

Furthermore, the present invention forms a common line in an undriven region where no data line is formed. As a result, the present invention can prevent the reduction of the aperture ratio due to the common line formed in the conventional drive region.

1 is a view illustrating some pixels of a liquid crystal display panel to which a DRD technology is applied.
2 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a circuit diagram illustrating in detail a pixel array according to a first exemplary embodiment of the present invention.
4 is a waveform diagram illustrating outputs of a data driving circuit and a gate driving circuit according to a first embodiment of the present invention;
5 is a circuit diagram illustrating in detail a pixel array according to a second exemplary embodiment of the present invention.
6 is a waveform diagram illustrating outputs of a data driving circuit and a gate driving circuit according to a second exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

2 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 2, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 10 in which a pixel array 10 is formed, and source drive integrated circuits 12. And a timing controller 11. A backlight unit for uniformly irradiating light to the liquid crystal display panel 10 may be disposed below the liquid crystal display panel 10.

The liquid crystal display panel 10 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The pixel array 10 is formed in the liquid crystal display panel. The pixel array 10 displays video data using subpixels arranged in a matrix by a cross structure of data lines and gate lines. The lower glass substrate of the pixel array 10 includes data lines, gate lines, thin film transistors (TFTs), pixel electrodes of subpixels connected to the TFTs, and storage capacitors connected to the pixel electrodes. Include. Each of the subpixels of the pixel array 10 displays an image by adjusting the amount of light transmitted by driving the liquid crystal of the liquid crystal layer by a voltage difference between a pixel electrode charged with a data voltage and a common electrode applied with a common voltage through the TFT. do. A detailed structure of the pixel array 10 will be described in detail with reference to FIGS. 3 and 5.

The black matrix and the color filter are formed on the upper glass substrate of the liquid crystal display panel. The common electrode is formed on the upper glass substrate in the case of the vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and in-plane switching (IPS) mode and fringe field switching (FFS). In the case of a horizontal electric field driving method such as), it is formed on the lower glass substrate together with the pixel electrode. The liquid crystal display of the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a TCP (Tape Carrier Package) 15, bonded to a lower glass substrate of a liquid crystal display panel by a TAB (Tape Automated Bonding) process, . The source drive ICs 12 may be adhered to the lower glass substrate of the liquid crystal display panel by a chip on glass (COG) process.

Each of the source drive ICs 12 receives the digital video data and the source timing control signal from the timing controller 11. The source drive ICs 12 convert digital video data into positive / negative data voltages in response to a source timing control signal to supply data lines of the pixel array 10. The source drive ICs 12 output data voltages in a column inversion manner under the control of the timing controller 11. The column type version scheme is a scheme of supplying data voltages of opposite polarities to neighboring data lines and maintaining the polarities of the data voltages supplied to the data lines to remain the same for one frame period. Therefore, the source drive ICs 12 output data voltages having polarity inverted in the column inversion manner to the data lines as shown in FIGS. 4 and 6.

The gate drive circuit 13 receives the gate timing control signal from the timing controller 11. [ The gate driving circuit 13 sequentially supplies gate pulses (or scan pulses) to the gate lines of the pixel array in response to the gate timing control signal. The gate driving circuit 13 may be mounted on the TCP and bonded to the lower glass substrate of the liquid crystal display panel by a TAB process. Alternatively, the gate driving circuit 13 may be directly formed on the lower glass substrate at the same time as the pixel array 10 by a gate in panel (GIP) process. The gate driving circuit 13 may be disposed on both sides of the pixel array 10 or one side of the pixel array 10 as shown in FIG. 2.

The timing controller 11 receives digital video data, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and timing signals such as a dot clock from an external system board. The timing controller 11 generates a timing control signal for controlling the operation timing of the source drive ICs 12 based on the digital video data and timing signals and a gate timing control signal for controlling the operation timing of the gate drive circuit 13 And generates a control signal. The timing controller 11 supplies digital video data and a source timing control signal to the source drive ICs 12. [ The timing controller 11 supplies a gate timing control signal to the source drive ICs 12. [ The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 are connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

3 is a circuit diagram illustrating in detail a pixel array according to a first embodiment of the present invention. 3, j-2 (j is a natural number of 3 or more) to j + 2 data lines Dj-2, Dj-1, Dj, Dj + 1, Dj + 2, and k-2 to k + A pixel array including subpixels surrounded by two (k is a natural number of three or more) gate lines Gk-2, Gk-1, Gk, Gk + 1, and Gk + 2 is shown.

Referring to FIG. 3, the pixel array has a form in which the first to fourth pixels P1, P2, P3, and P4 are regularly arranged. In FIG. 3, each of the first to fourth pixels P1, P2, P3, and P4 includes a red subpixel R, a green subpixel G, and a blue subpixel B. Note that it is not limited thereto. That is, each of the first to fourth pixels P1, P2, P3, and P4 may be implemented by any combination of a yellow subpixel, a magenta subpixel, and a cyan subpixel.

The first pixel P1 includes first to third subpixels SP1, SP2, and SP3 present in the first horizontal line HLINE # 1. The first sub-pixel SP1 is connected to the k-th gate line Gk-2 and the j-th data line Dj-1 through the first TFT T1. The gate electrode of the first TFT T1 is connected to the k-2th gate line Gk-2, the source electrode is connected to the j-1th data line Dj-1, and the drain electrode is the first subpixel. It is connected to the pixel electrode of SP1. The second sub-pixel SP2 is connected to the k-th gate line Gk-2 and the j-th data line Dj through the second TFT T2. The gate electrode of the second TFT T2 is connected to the k-th gate line Gk-2, the source electrode is connected to the j-th data line Dj, and the drain electrode of the second sub-pixel SP2 It is connected to a pixel electrode. The third sub pixel SP3 is connected to the k-1 th gate line Gk-1 and the j-1 th data line Dj-1 through the third TFT T3. The gate electrode of the third TFT T3 is connected to the k-1 th gate line Gk-1, the source electrode is connected to the j-1 th data line Dj-1, and the drain electrode is the third sub pixel. It is connected to the pixel electrode of SP3.

The second pixel P2 includes fourth to sixth subpixels SP4, SP5, and SP6 present in the first horizontal line HLINE # 1. The fourth sub-pixel SP4 is connected to the k-th gate line Gk-1 and the j-th data line Dj through the fourth TFT T4. The gate electrode of the fourth TFT T4 is connected to the k-th gate line Gk-1, the source electrode is connected to the j-th data line Dj, and the drain electrode of the fourth sub-pixel SP4 It is connected to a pixel electrode. The fifth sub-pixel SP5 is connected to the k-th gate line Gk-2 and the j + 1th data line Dj + 1 through the fifth TFT T5. The gate electrode of the fifth TFT T5 is connected to the k-2th gate line Gk-2, the source electrode is connected to the j + 1th data line Dj + 1, and the drain electrode is the fifth subpixel. It is connected to the pixel electrode of SP5. The sixth sub-pixel SP6 is connected to the k-th gate line Gk-2 and the j + 2th data line Dj + 2 through the sixth TFT T6. The gate electrode of the sixth TFT T6 is connected to the k-th gate line Gk-2, the source electrode is connected to the j + 2th data line Dj + 2, and the drain electrode is the sixth subpixel. It is connected to the pixel electrode of SP6.

The third pixel P1 includes the seventh to ninth subpixels SP7, SP8, and SP9 present in the second horizontal line HLINE # 2. The seventh sub-pixel SP7 is connected to the k-th gate line Gk and the j-th data line Dj-2 through the seventh TFT T7. The gate electrode of the seventh TFT T7 is connected to the k-th gate line Gk, the source electrode is connected to the j-th data line Dj-2, and the drain electrode is connected to the seventh sub-pixel SP7. It is connected to a pixel electrode. The eighth sub-pixel SP8 is connected to the k-th gate line Gk and the j-th data line Dj-1 through the eighth TFT T8. The gate electrode of the eighth TFT T8 is connected to the k-th gate line Gk, the source electrode is connected to the j-1th data line Dj-1, and the drain electrode of the eighth subpixel SP8 It is connected to a pixel electrode. The ninth sub-pixel SP9 is connected to the k-th gate line Gk and the j-th data line Dj through the ninth TFT T9. The gate electrode of the ninth TFT T9 is connected to the k-th gate line Gk, the source electrode is connected to the j-th data line Dj, and the drain electrode is connected to the pixel electrode of the ninth sub-pixel SP9. do.

The fourth pixel P4 includes the tenth to twelfth subpixels SP10, SP11, and SP12 present in the second horizontal line HLINE # 2. The tenth sub-pixel SP10 is connected to the k-th gate line Gk-1 and the j + 1th data line Dj + 1 through the tenth TFT T10. The gate electrode of the tenth TFT (T10) is connected to the k-th gate line Gk-1, the source electrode is connected to the j + 1th data line Dj + 1, and the drain electrode is the tenth subpixel. It is connected to the pixel electrode of SP10. The eleventh sub-pixel SP11 is connected to the k-th gate line Gk-1 and the j + 2th data line Dj + 2 through the eleventh TFT T11. The gate electrode of the eleventh TFT (T11) is connected to the k-th gate line Gk-1, the source electrode is connected to the j + 2th data line Dj + 2, and the drain electrode is the eleventh subpixel. It is connected to the pixel electrode of SP11. The twelfth sub-pixel SP12 is connected to the k-th gate line Gk and the j + 1th data line Dj + 1 through the twelfth TFT T12. The gate electrode of the twelfth TFT T12 is connected to the k-th gate line Gk, the source electrode is connected to the j + 1th data line Dj + 1, and the drain electrode of the twelfth subpixel SP12 It is connected to a pixel electrode.

Meanwhile, the pixel array according to the first exemplary embodiment of the present invention may be connected to two subpixels commonly connected to one data line among three subpixels existing on the same horizontal line and to another data line alone. It contains one subpixel. For example, the pixel array includes second and fourth subpixels SP2 and SP4 that are commonly connected to the j th data line Dj in the first horizontal line HLINE # 1, and the j + 1 th data line And a fifth sub-pixel SP5 connected to Dj + 1 alone. In addition, the pixel array includes tenth and twelfth subpixels SP10 and SP12 connected in common to the j + 1th data line Dj + 1 in the second horizontal line HLINE # 2, and the jth data line And a ninth sub-pixel S9 connected to Dj alone.

In addition, the two consecutive sub-pixels in the vertical direction are formed to be connected to one or two of the three consecutive gate lines. For example, the first and seventh sub-pixels SP1 and SP7 of the first vertical line VLINE # 1 are k-2 to k + 1th gate lines Gk-2, Gk-1, and Gk. ) Is connected to the k-th gate line Gk-2 and the k-th gate line Gk. Fourth and tenth subpixels SP4 and SP10 of the fourth vertical line VLINE # 4 are k-1 of k-2 to kth gate lines Gk-2, Gk-1, and Gk. Is connected to the gate line. In the conventional DRD technology, two vertical subcontinuous pixels are connected to two of the four consecutive gate lines, whereas in the first exemplary embodiment of the present invention, the two consecutive vertical subpixels are 3 And is connected to one or two of the two consecutive gate lines. That is, in the conventional DRD technique, four gate lines are required to control two consecutive subpixels in the vertical direction. However, in the first embodiment of the present invention, three gate lines are controlled to control two subpixels in the vertical direction. Gate lines are required. As a result, since the frequency of the gate driving circuit of the first embodiment of the present invention is lower than the frequency of the gate driving circuit of the conventional DRD technology, the first embodiment of the present invention can increase the data voltage charging period than the DRD technology. In addition, since the common voltage is stabilized as the data voltage charging period is longer, the first embodiment of the present invention can reduce the influence of the common voltage ripple. Therefore, since the first embodiment of the present invention can prevent image distortion and image degradation, image quality can be improved over DRD technology.

In addition, the j-1th data line Dj-1 is between the first subpixel SP1 and the second subpixel SP2 and between the seventh subpixel SP7 and the eighth subpixel SP8. It is formed to be disposed. The j th data line Dj is formed to be disposed between the third sub pixel SP3 and the fourth sub pixel SP4 and between the ninth sub pixel SP9 and the tenth sub pixel SP10. The j + 1th data line Dj + 1 is disposed between the fourth subpixel SP4 and the fifth subpixel SP5 and between the tenth subpixel SP10 and the eleventh subpixel SP11. Is formed. The j-2 th data line Dj-2 is disposed on the side opposite to the side where the j-1 th data line Dj-1 is formed based on the first sub pixel SP1 and the seventh sub pixel SP7. Is formed. The j + 2th data line Dj + 2 is opposite to the side at which the fifth subpixel SP5 and the eleventh subpixel SP11 are formed based on the sixth subpixel SP6 and the twelfth subpixel SP12. It is formed to be disposed on the side. As a result, between the second sub-pixel SP2 and the third sub-pixel SP3, between the eighth sub-pixel SP8 and the ninth sub-pixel SP9, the fifth sub-pixel SP5 and the sixth sub-sub No data line is formed between the pixel SP6 and between the eleventh subpixel SP11 and the twelfth subpixel SP12. In the conventional structure in which a data line is formed between all subpixels, the common voltage line has to be formed so as to overlap the subpixels corresponding to the driving region, thereby reducing the aperture ratio. However, according to the first embodiment of the present invention, between the eighth subpixel SP8 and the ninth subpixel SP9 between the second subpixel SP2 and the third subpixel SP3 in which no data line is formed. To form a common voltage line for supplying a common voltage between the fifth subpixel SP5 and the sixth subpixel SP6, and between the eleventh subpixel SP11 and the twelfth subpixel SP12. Can be. In this case, since the common voltage line is formed in the non-driving region covered by the black matrix, the first embodiment of the present invention can improve the problem of decreasing the conventional aperture ratio.

In addition, the pixel array according to the first exemplary embodiment of the present invention has different polarities between two sub pixels continuous in the vertical direction, and different polarities between two sub pixels continuous in the horizontal direction. For example, polarities between the first pixel P1 and the second pixel P2 that are continuous in the vertical direction are different from each other, and polarities between the first pixel P1 and the seventh pixel P7 that are continuous in the horizontal direction are different from each other. different. That is, the first embodiment of the present invention may be driven by the dot inversion method.

Meanwhile, the liquid crystal display according to the first exemplary embodiment of the present invention may be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode. However, it should be noted that in the case of vertical electric field driving methods such as TN mode and VA mode, the common electrode is formed on the upper glass substrate, and in the case of horizontal electric field driving methods such as IPS mode and FFS mode, the common electrode is formed on the lower glass substrate. do.

4 is a waveform diagram illustrating outputs of a source drive IC and a gate driving circuit according to a first exemplary embodiment of the present invention. Referring to FIG. 4, data voltages DVj-2, DVj-1, DVj, DVj + 1, which are output from each of the source drive ICs 12 during the Nth (N is a natural number) and Nth + 1th frame periods. DVj + 2 is shown, and gate pulses GPk-2, GPk-1, GPk, GPk + 1, and GPk + 2 output from the gate driving circuit 13 are shown.

DVj-2 is the j-2th data voltages supplied to the j-2th data line Dj-2, and DVj-1 is the j-1th data voltage supplied to the j-1th data line Dj-1 For example, DVj is j-th data voltages supplied to the j-th data line Dj, DVj + 1 is j + 1-th data voltages supplied to the j + 1 data line Dj + 1, and DVj + 2 is The j + 2 th data voltages supplied to the j + 2 th data line Dj + 2. GPk-2 is the k-2th gate pulse supplied to the k-2th gate line Gk-2, GPk-1 is the k-1th gate pulse supplied to the k-1th gate line Gk-1, GPk is the k-th gate pulse supplied to the k-th gate line Gk, GPk + 1 is the k + 1-th gate pulse supplied to the k + 1th gate line GPk + 1, GPk + 2 is k + 2 A k + 2 th gate pulse supplied to the gate line GPk + 2.

Each of the source drive ICs 12 supplies data voltages to the data lines in a column inversion manner. The column type version scheme is a scheme of supplying data voltages of opposite polarities to neighboring data lines and maintaining the polarities of the data voltages supplied to the data lines to remain the same for one frame period. For example, each of the source drive ICs 12 supplies the j-2th data voltages DVj-2 with the first polarity during the Nth frame period as shown in FIG. 4, and the j-1th data voltages ( DVj-1) is supplied at the second polarity, j-th data voltages DVj are supplied at the first polarity, j + 1-th data voltages DVj + 1 are supplied at the second polarity, and j The +2 data voltages DVj + 2 are supplied at a first polarity. In addition, each of the source drive ICs 12 supplies the j-2th data voltages DVj-2 with the second polarity during the N + 1th frame period as shown in FIG. 4, and the j-1th data voltages ( DVj-1) is supplied at a first polarity, j-th data voltages DVj are supplied at a second polarity, j + 1-th data voltages DVj + 1 are supplied at a first polarity, and j The +2 data voltages DVj + 2 are supplied at the second polarity. In FIG. 4, although the first polarity is implemented as the positive polarity and the second polarity is the negative polarity, it should be noted that the present invention is not limited thereto. That is, the first polarity may be negative and the second polarity may be positive.

The gate drive circuit 13 sequentially outputs the gate pulses to the gate lines. For example, as shown in FIG. 4, the gate driving circuit 13 applies the k-th gate pulse GPk-2 to the k-th gate line Gk-2 in each of the Nth and Nth + 1th frame periods. Outputs the k-th gate pulse GPk-1 to the k-th gate line Gk-1, outputs the k-th gate pulse GPk to the k-th gate line Gk, and A k + 1 th gate pulse GPk + 1 is output to a k + 1 gate line Gk + 1, and a k + 2 th gate pulse GPk + 2 is applied to a k + 2 gate line Gk + 2. Output Each of the gate pulses generates a gate high voltage (VGH) for a predetermined period. The predetermined period may be implemented as one horizontal period 1H. One horizontal period 1H means one line scanning time in which digital video data is written in pixels of one horizontal line in the display panel 10.

Hereinafter, a method of charging data voltages in the subpixels during the first to third periods t1 to t3 of the Nth frame period will be described in detail with reference to FIGS. 3 and 4.

The first period t1 is a period during which the k-2nd gate pulse GPk-2 is supplied to the k-2th gate line GPk-2, and the second period t2 is a k-1th gate pulse ( The period GPk-1 is supplied to the k-th gate line GPk-1, and the third period t3 is a period during which the k-th gate pulse GPk is supplied to the k-th gate line GPk.

During the first period t1, the first, second, fifth, and sixth subpixels SP1, SP2, SP5, and SP6 charge the data voltage in response to the k-2 gate pulse GPk-2. . The first sub-pixel SP1 connected to the j-1 th data line Dj-1 charges the j-1 th data voltage DVj-1 of the second polarity. The second sub pixel SP2 connected to the j th data line Dj charges the j th data voltage DVj of the first polarity. The fifth sub pixel SP5 connected to the j + 1 th data line Dj + 1 charges the j + 1 th data voltage DVj + 1 of the second polarity. The sixth subpixel SP6 connected to the j + 2 th data line Dj + 2 charges the j + 2 th data voltage DVj + 2 of the first polarity.

During the second period t2, the third, fourth, tenth, and eleventh sub-pixels SP3, SP4, SP10, and SP11 charge the data voltage in response to the k-1 gate pulse GPk-1. . The third sub-pixel SP3 connected to the j-1 th data line Dj-1 charges the j-1 th data voltage DVj-1 of the second polarity. The fourth sub pixel SP4 connected to the j th data line Dj charges the j th data voltage DVj of the first polarity. The tenth sub-pixel SP10 connected to the j + 1th data line Dj + 1 charges the j + 1th data voltage DVj + 1 of the second polarity. The eleventh sub-pixel SP11 connected to the j + 2 th data line Dj + 2 charges the j + 2 th data voltage DVj + 2 of the first polarity.

During the third period t3, the seventh, eighth, ninth, and twelfth subpixels SP7, SP8, SP9, and SP12 charge the data voltage in response to the k-th gate pulse GPk. The seventh sub-pixel SP7 connected to the j-2 th data line Dj-2 charges the j-2 th data voltage DVj-2 of the first polarity. The eighth sub-pixel SP8 connected to the j-1 th data line Dj-1 charges the j-1 th data voltage DVj-1 of the second polarity. The ninth sub-pixel SP9 connected to the j th data line Dj charges the j th data voltage DVj of the first polarity. The twelfth sub-pixel SP12 connected to the j + 1th data line Dj + 1 charges the j + 1th data voltage DVj + 1 of the second polarity.

In summary, the first sub-pixel SP1, the third sub-pixel SP3, and the eighth sub-pixel SP8 include the first sub-pixel SP1, the third sub-pixel SP3, and the eighth sub-pixel SP8. The data voltage of the second polarity is charged in the following order. The second sub-pixel SP2, the seventh sub-pixel SP7, and the ninth sub-pixel SP9 are the order of the second sub-pixel SP2, the seventh sub-pixel SP7, and the ninth sub-pixel SP9. Charges the data voltage of the first polarity. The fourth sub-pixel SP4, the sixth sub-pixel SP6, and the eleventh sub-pixel SP11 are the order of the sixth sub-pixel SP6, the fourth sub-pixel SP4, and the eleventh sub-pixel SP11. Charges the data voltage of the first polarity. The fifth subpixel SP5, the tenth subpixel SP10, and the twelfth subpixel SP12 are the order of the fifth subpixel SP5, the tenth subpixel SP10, and the twelfth subpixel SP12. Charges the data voltage of the second polarity.

As a result, although each of the source drive ICs 12 supplies data voltages to the data lines in a column inversion manner, each of the first to twelfth subpixels SP1 to SP12 has a polarity in which neighboring subpixels are opposite to each other. It is driven by a dot inversion method that is charged with a data voltage. As a result, the first embodiment of the present invention can be driven in a dot inversion method that can significantly reduce the power consumption (P) by the column inversion method and can suppress the DC afterimage, flicker, etc. of the liquid crystal. There are advantages to it. An effect of reducing power consumption P will be described in detail with reference to Equation 1.

In Equation 1, P is power consumption, f is frequency, n is the number of data lines, C is a capacitor, and V is an effective voltage. The power consumption (P) is proportional to the magnitude of the frequency (f) and the effective voltage (V). The frequency (f) becomes large when driven by an alternating current, and the effective voltage (V) is changed from the positive data voltage to the negative data voltage. It is large when transitioned, or vice versa, when transitioned from a negative data voltage to a positive data voltage.

A conventional liquid crystal display device swings a positive data voltage and a negative data voltage around one common voltage Vcom every one horizontal period or two horizontal periods. The conventional liquid crystal display device has a high frequency f and the magnitude of the effective voltage V is from the negative data voltage to the positive data voltage. In contrast, since the liquid crystal display according to the first exemplary embodiment of the present invention performs direct current driving every one frame period, the frequency f is low as shown in FIG. 4, and the magnitude of the effective voltage V is positive from the common voltage. Up to the negative data voltage. That is, the magnitude of the effective voltage V of the liquid crystal display according to the first embodiment of the present invention corresponds to 50% of the conventional liquid crystal display, and the frequency f is significantly lower than that of the conventional liquid crystal display. Therefore, the liquid crystal display according to the first exemplary embodiment of the present invention has an advantage in that power consumption P can be greatly reduced as compared to the conventional liquid crystal display.

5 is a circuit diagram illustrating in detail a pixel array according to a second exemplary embodiment of the present invention. 5, p-2 (p is a natural number of 3 or more) to p + 2 data lines Dp-2, Dp-1, Dp, Dp + 1, and Dp + 2, and q-3 to q + A pixel array is shown that includes subpixels surrounded by 3 (q is a natural number of 4 or more) gate lines Gq-3, Gq-2, Gq-1, Gq, Gq + 1, Gq + 2, and Gq + 3. .

Referring to FIG. 5, the pixel array has a form in which the first to eighth pixels P1, P2, P3, P4, P5, P6, P7, and P8 are regularly arranged. In FIG. 5, the first to eighth pixels P1, P2, P3, P4, P5, P6, P7, and P8 each represent a red subpixel R, a green subpixel G, and a blue subpixel B. Although described based on the inclusion, it should be noted that it is not limited thereto. That is, each of the first to eighth pixels P1, P2, P3, P4, P5, P6, P7, and P8 may be implemented by any combination of a yellow subpixel, a magenta subpixel, and a cyan subpixel.

The first pixel P1 includes first to third subpixels SP1, SP2, and SP3 present in the first horizontal line HLINE # 1. The first sub pixel SP1 is connected to the q-3rd gate line Gq-3 and the p-2 data line Dp-2 through the first TFT T1. The gate electrode of the first TFT T1 is connected to the q-3rd gate line Gq-3, the source electrode is connected to the p-2 data line Dp-2, and the drain electrode is the first subpixel. It is connected to the pixel electrode of SP1. The second sub-pixel SP2 is connected to the q-th gate line Gq-2 and the p-th data line Dp-1 through the second TFT T2. The gate electrode of the second TFT T2 is connected to the q-2 gate line Gq-2, the source electrode is connected to the p-1 data line Dp-1, and the drain electrode is connected to the second sub pixel. It is connected to the pixel electrode of SP2. The third sub-pixel SP3 is connected to the q-th gate line Gq-2 and the p-th data line Dp through the third TFT T3. The gate electrode of the third TFT T3 is connected to the q-2nd gate line Gq-2, the source electrode is connected to the pth data line Dp, and the drain electrode of the third subpixel SP3 is connected. It is connected to a pixel electrode.

The second pixel P2 includes fourth to sixth subpixels SP4, SP5, and SP6 present in the first horizontal line HLINE # 1. The fourth sub-pixel SP4 is connected to the q-th gate line Gq-2 and the p + 1th data line Dp + 1 through the fourth TFT T4. The gate electrode of the fourth TFT T4 is connected to the q-2 gate line Gq-2, the source electrode is connected to the p + 1 data line Dp + 1, and the drain electrode is the fourth sub pixel. It is connected to the pixel electrode of SP4. The fifth subpixel SP5 is connected to the q-th gate line Gq-2 and the p + 2th data line Dp + 2 through the fifth TFT T5. The gate electrode of the fifth TFT T5 is connected to the q-th gate line Gq-2, the source electrode is connected to the p + 2th data line Dp + 2, and the drain electrode is the fifth subpixel. It is connected to the pixel electrode of SP5. The sixth sub-pixel SP6 is connected to the q-3rd gate line Gq-3 and the p + 1th data line Dp + 1 through the sixth TFT T6. The gate electrode of the sixth TFT T6 is connected to the q-3rd gate line Gq-3, the source electrode is connected to the p + 1th data line Dp + 1, and the drain electrode is the sixth subpixel. It is connected to the pixel electrode of SP6.

The third pixel P1 includes the seventh to ninth subpixels SP7, SP8, and SP9 present in the second horizontal line HLINE # 2. The seventh sub-pixel SP7 is connected to the q th gate line Gq and the p-2 th data line Dp-2 through the seventh TFT T7. The gate electrode of the seventh TFT T7 is connected to the qth gate line Gq, the source electrode is connected to the p-2 data line Dp-2, and the drain electrode of the seventh subpixel SP7 is connected. It is connected to a pixel electrode. The eighth sub-pixel SP8 is connected to the q-1 th gate line Gq-1 and the p-1 th data line Dp-1 through the eighth TFT T8. The gate electrode of the eighth TFT T8 is connected to the q-1 gate line Gq-1, the source electrode is connected to the p-1 data line Dp-1, and the drain electrode is the eighth subpixel. It is connected to the pixel electrode of SP8. The ninth sub-pixel SP9 is connected to the q-th gate line Gq-1 and the p-th data line Dp through the ninth TFT T9. The gate electrode of the ninth TFT T9 is connected to the q-th gate line Gq-1, the source electrode is connected to the p-th data line Dp, and the drain electrode of the ninth sub-pixel SP9 It is connected to a pixel electrode.

The fourth pixel P4 includes the tenth to twelfth subpixels SP10, SP11, and SP12 present in the second horizontal line HLINE # 2. The tenth sub-pixel SP10 is connected to the q-1 th gate line Gq-1 and the p + 1 th data line Dp + 1 through the tenth TFT T10. The gate electrode of the tenth TFT (T10) is connected to the q-1th gate line Gq-1, the source electrode is connected to the p + 1th data line Dp + 1, and the drain electrode is the tenth subpixel. It is connected to the pixel electrode of SP10. The eleventh sub-pixel SP11 is connected to the q-th gate line Gq-1 and the p + 2th data line Dp + 2 through the eleventh TFT T11. The gate electrode of the eleventh TFT T11 is connected to the q-1 gate line Gq-1, the source electrode is connected to the p + 2th data line Dp + 2, and the drain electrode is the eleventh subpixel. It is connected to the pixel electrode of SP11. The twelfth sub-pixel SP12 is connected to the qth gate line Gq and the p + 1th data line Dp + 1 through the twelfth TFT T12. The gate electrode of the twelfth TFT T12 is connected to the qth gate line Gq, the source electrode is connected to the p + 1th data line Dp + 1, and the drain electrode of the twelfth subpixel SP12 It is connected to a pixel electrode.

The fifth pixel P5 includes thirteenth to fifteenth subpixels SP13, SP14, and SP15 that exist in the third horizontal line HLINE # 3. The thirteenth sub-pixel SP13 is connected to the q + 1 th gate line Gq + 1 and the p−1 th data line Dp-1 through the thirteenth TFT T13. The gate electrode of the thirteenth TFT T13 is connected to the q + 1 th gate line Gq + 1, the source electrode is connected to the p−1 th data line Dp−1, and the drain electrode is the thirteenth subpixel It is connected to the pixel electrode of SP13. The fourteenth sub-pixel SP14 is connected to the q + 1 th gate line Gq + 1 and the p th data line Dp through the fourteenth TFT T14. The gate electrode of the second TFT T2 is connected to the q + 1th gate line Gq + 1, the source electrode is connected to the pth data line Dp, and the drain electrode of the fourteenth subpixel SP14 is connected. It is connected to a pixel electrode. The fifteenth sub-pixel SP15 is connected to the q th gate line Gq and the p th data line Dp-1 through the fifteenth TFT T15. The gate electrode of the fifteenth TFT T15 is connected to the qth gate line Gq, the source electrode is connected to the p-1 data line Dp-1, and the drain electrode of the fifteenth subpixel SP15 It is connected to a pixel electrode.

The sixth pixel P6 includes sixteenth to eighteenth subpixels SP16, SP17, and SP18 that exist in the third horizontal line HLINE # 3. The sixteenth sub-pixel SP16 is connected to the qth gate line Gq and the pth data line Dp through the sixteenth TFT T16. The gate electrode of the sixteenth TFT (T16) is connected to the qth gate line Gq, the source electrode is connected to the pth data line Dp, and the drain electrode is connected to the pixel electrode of the sixteenth subpixel SP16. do. The seventeenth sub-pixel SP17 is connected to the q + 1 th gate line Gq + 1 and the p + 1 th data line Dp + 1 through the seventeenth TFT T17. The gate electrode of the fifth TFT T5 is connected to the q + 1th gate line Gq + 1, the source electrode is connected to the p + 1th data line Dp + 1, and the drain electrode is the seventeenth subpixel. It is connected to the pixel electrode of SP17. The eighteenth sub-pixel SP18 is connected to the q + 1 th gate line Gq + 1 and the p + 2 th data line Dp + 2 through an eighteenth TFT T18. The gate electrode of the eighteenth TFT (T18) is connected to the q + 1th gate line Gq + 1, the source electrode is connected to the p + 2th data line Dp + 2, and the drain electrode is the eighteenth subpixel. It is connected to the pixel electrode of SP18.

The seventh pixel P7 includes nineteenth to twenty-first subpixels SP19, SP20, and SP21 that are present in the fourth horizontal line HLINE # 4. The nineteenth sub-pixel SP19 is connected to the q + 3 th gate line Gq + 3 and the p−1 th data line Dp-1 through the nineteenth TFT T19. The gate electrode of the nineteenth TFT T19 is connected to the q + 3 th gate line Gq + 3, the source electrode is connected to the p−1 th data line Dp−1, and the drain electrode is the 19 th subpixel. It is connected to the pixel electrode of SP19. The twentieth sub-pixel SP20 is connected to the q + 3 th gate line Gq + 3 and the p th data line Dp through the twentieth TFT T20. The gate electrode of the twentieth TFT T20 is connected to the q + 3 th gate line Gq + 3, the source electrode is connected to the p th data line Dp, and the drain electrode of the twentieth sub pixel SP20 It is connected to a pixel electrode. The twenty-first sub-pixel SP21 is connected to the q + 2 th gate line Gq + 2 and the p−1 th data line Dp-1 through the twenty-first TFT T21. The gate electrode of the twenty-first TFT T21 is connected to the q + 2 th gate line Gq + 2, the source electrode is connected to the p−1 th data line Dp−1, and the drain electrode is the twenty-first subpixel. It is connected to the pixel electrode of SP21.

The eighth pixel P8 includes the twenty-second through twenty-fourth subpixels SP22, SP23, and SP24 that are present in the fourth horizontal line HLINE # 4. The twenty-second sub pixel SP22 is connected to the q + 2 th gate line Gq + 2 and the p th data line Dp through the twenty-second TFT T22. The gate electrode of the twenty-second TFT T22 is connected to the q + 2 th gate line Gq + 2, the source electrode is connected to the p th data line Dp, and the drain electrode of the twenty-second subpixel SP22 It is connected to a pixel electrode. The twenty-third sub-pixel SP23 is connected to the q + 2 th gate line Gq + 2 and the p + 1 th data line Dp + 1 through the twenty-third TFT T23. The gate electrode of the twenty-third TFT T23 is connected to the q + 2 th gate line Gq + 2, the source electrode is connected to the p + 1 th data line Dp + 1, and the drain electrode is the twenty-third subpixel It is connected to the pixel electrode of SP23. The 24 th sub pixel SP24 is connected to the q + 2 th gate line Gq + 2 and the p + 2 th data line Dp + 2 through the 24 th TFT T24. The gate electrode of the twenty-fourth TFT T24 is connected to the q + 2 th gate line Gq + 2, the source electrode is connected to the p + 2 th data line Dp + 2, and the drain electrode is the twenty-fourth subpixel. It is connected to the pixel electrode of SP24.

Meanwhile, the pixel array according to the second exemplary embodiment of the present invention may be connected to two subpixels commonly connected to one data line among three subpixels existing on the same horizontal line and to another data line alone. It contains one subpixel. For example, the pixel array includes fourth and sixth subpixels SP4 and SP6 that are commonly connected to the p + 1th data line Dp + 1 in the first horizontal line HLINE # 1, and the pth data. The third sub pixel SP3 is connected to the line Dp alone. The pixel array includes tenth and twelfth subpixels SP10 and SP12 that are commonly connected to the p + 1th data line Dp + 1 in the second horizontal line HLINE # 2, and the pth data line Dp. The ninth sub-pixel SP3 is connected to the singular. The pixel array includes thirteenth and fifteenth subpixels SP13 and SP15 that are commonly connected to the p-1 data line Dp-1 in the third horizontal line HLINE # 3, and the p + 1 data line ( And a seventeenth sub-pixel SP17 connected to Dp + 1 alone. The pixel array includes nineteenth and twenty-first subpixels SP19 and SP21 that are commonly connected to the p-1 data line Dp-1 in the fourth horizontal line HLINE # 4, and the p + 1 data line ( And the twenty-third sub-pixel SP23 connected to Dp + 1 alone.

In addition, four sub-pixels that are continuous in the vertical direction are formed to be connected to four of six or seven consecutive gate lines. For example, the first, seventh, thirteenth, and nineteenth subpixels of the first vertical line VLINE # 1 may include the qth through qth through q + 3 gate lines. Q-3 gate lines Gq-3, qq gate lines Gq, and 1 of Gq-3, Gq-2, Gq-1, Gq, Gq + 1, Gq + 2, and Gq + 3. It is connected to the q + 1 gate line Gq + 1 and the q + 3 th gate line Gq + 3. In the conventional DRD technology, two vertical subcontinuous pixels are connected to two of the four consecutive gate lines, whereas in the second exemplary embodiment of the present invention, the four consecutive vertical subpixels are 6 And is connected to four of seven or seven consecutive gate lines. That is, in the conventional DRD technique, four gate lines are required to control two consecutive subpixels in the vertical direction, but in the second embodiment of the present invention, six gate lines are used to control the four consecutive subpixels in the vertical direction. Four or seven gate lines are required. As a result, since the frequency of the gate driving circuit of the second embodiment of the present invention is lower than the frequency of the gate driving circuit of the conventional DRD technology, the second embodiment of the present invention can increase the data voltage charging period than the DRD technology. In addition, since the common voltage is stabilized as the data voltage charging period is longer, the second embodiment of the present invention can reduce the influence of the common voltage ripple. Therefore, since the second embodiment of the present invention can prevent image distortion and image degradation, image quality can be improved over DRD technology.

In addition, the p-1 data line Dp-1 may be disposed between the first subpixel SP1 and the second subpixel SP2, between the seventh subpixel SP7 and the eighth subpixel SP8. It is formed to be disposed between the thirteenth subpixel SP13 and the fourteenth subpixel SP14, and between the nineteenth subpixel SP19 and the twentieth subpixel SP20. The pth data line Dp is between the third subpixel SP3 and the fourth subpixel SP4, between the ninth subpixel SP9 and the tenth subpixel SP10, and the fifteenth subpixel SP15. ) And the sixteenth sub-pixel SP16, and between the twenty-first sub-pixel SP21 and the twenty-second sub-pixel SP22. The jth + 1th data line Dp + 1 is between the fourth subpixel SP4 and the fifth subpixel SP5, between the tenth subpixel SP10 and the eleventh subpixel SP11, and the sixteenth subpixel SP11. The subpixel SP16 is disposed between the subpixel SP16 and the seventeenth subpixel SP17 and between the twenty-second subpixel S22 and the twenty-third subpixel S24. The p-th data line Dp-2 includes the p-th data based on the first subpixel SP1, the seventh subpixel SP7, the thirteenth subpixel SP13, and the nineteenth subpixel SP19. 1 is formed so as to be disposed on the side opposite to the side formed on the data line Dp-1. The p + 2th data line Dp + 2 is the fifth subpixel SP6, the twelfth subpixel SP12, the eighteenth subpixel SP18, and the fifth subpixel SP24 based on the sixth subpixel SP6. The pixel SP5, the eleventh subpixel SP11, the seventeenth subpixel SP17, and the twenty-third subpixel SP23 are disposed to face opposite sides of the pixel SP5. As a result, between the second sub-pixel SP2 and the third sub-pixel SP3, between the eighth sub-pixel SP8 and the ninth sub-pixel SP9, the fourteenth sub-pixel SP14 and the fifteenth sub Between the pixel SP15, between the twentieth subpixel SP20 and the twenty-first subpixel SP21, between the fifth subpixel SP5 and the sixth subpixel SP6, and the eleventh subpixel SP11. And any data line between the twelfth subpixel SP12, the seventeenth subpixel SP17 and the eighteenth subpixel SP18, and the twenty-third subpixel SP23 and the twenty-fourth subpixel SP24. Is not formed. In the conventional structure in which a data line is formed between all subpixels, the common voltage line has to be formed so as to overlap the subpixels corresponding to the driving region, thereby reducing the aperture ratio. However, according to the second embodiment of the present invention, between the second subpixel SP2 and the third subpixel SP3 in which no data line is formed, the eighth subpixel SP8 and the ninth subpixel SP9 are disposed. Between the 14th subpixel SP14 and the 15th subpixel SP15, between the 20th subpixel SP20 and the 21st subpixel SP21, the fifth subpixel SP5 and the sixth subpixel. Between SP6, between the eleventh subpixel SP11 and the twelfth subpixel SP12, between the seventeenth subpixel SP17 and the eighteenth subpixel SP18, and the twenty-third subpixel SP23. And a common voltage line for supplying a common voltage between the twenty-fourth sub-pixel SP24. In this case, since the common voltage line is formed in the non-driving region covered by the black matrix, the first embodiment of the present invention can improve the problem of decreasing the conventional aperture ratio.

In addition, the pixel array according to the second embodiment of the present invention when the upper two sub-pixels of the four consecutive sub-pixels in the vertical direction are divided into the first group, and the lower two sub-pixels into the second group, The polarities of the subpixels in the first group are the same, and the polarities of the subpixels in the second group are the same. However, it should be noted that the polarities of the subpixels in the first group and the subpixels in the second group are different from each other. For example, when the first pixel P1 and the seventh pixel P7 continuous in the vertical direction are divided into the first group, and the thirteenth pixel P13 and the nineteenth pixel P19 are divided into the second group, Polarities between the first pixel P1 and the seventh pixel P7 in the first group are the same, and polarities between the thirteenth pixel P13 and the nineteenth pixel P19 in the second group are the same. However, polarities of the first pixel P1 and the seventh pixel P7 in the first group and polarities of the thirteenth pixel P13 and the nineteenth pixel P19 in the second group are different from each other. That is, the second embodiment of the present invention may be driven by the horizontal two dot inversion method.

Meanwhile, the liquid crystal display according to the second embodiment of the present invention may be implemented in any liquid crystal mode as well as in the TN mode, VA mode, IPS mode, and FFS mode. However, it should be noted that in the case of vertical electric field driving methods such as TN mode and VA mode, the common electrode is formed on the upper glass substrate, and in the case of horizontal electric field driving methods such as IPS mode and FFS mode, the common electrode is formed on the lower glass substrate. do.

6 is a waveform diagram illustrating an output of a data driving circuit and a gate driving circuit according to a second exemplary embodiment of the present invention. Referring to FIG. 6, data voltages DVp-2, DVp-1, DVp, DVp + 1, which are output from each of the source drive ICs 12 during the Nth (N is a natural number) and Nth + 1th frame periods. DVp + 2 is shown, and the gate pulses GPq-3, GPq-2, GPq-1, GPq, GPk + 1, GPq + 2, and GPq + 3 output from the gate driving circuit 13 are shown. .

DVp-2 is the p-2 data voltages supplied to the p-2 data line Dp-2, and DVp-1 is the p-1 data voltage supplied to the p-1 data line Dp-1. For example, DVp denotes pth data voltages supplied to the pth data line Dp, DVp + 1 denotes p + 1 data voltages supplied to the p + 1th data line Dp + 1, and DVp + 2 denotes The p + 2 th data voltages supplied to the p + 2 th data line Dp + 2. GPq-3 is the q-3 gate pulse supplied to the q-3 gate line Gq-3, GPq-2 is the q-2 gate pulse supplied to the q-2 gate line Gq-2, GPq-1 is the q-1 gate pulse supplied to the q-1 gate line Gq-1, GPq is the qth gate pulse supplied to the qth gate line Gq, and GPq + 1 is q + 1 The q + 1 gate pulse supplied to the gate line GPq + 1, GPq + 2 is the q + 2 gate pulse supplied to the q + 2 gate line GPq + 2, and the GPq + 3 is the q + 3 gate It means a q + 3 th gate pulse supplied to the gate line Gq + 3.

Each of the source drive ICs 12 supplies data voltages to the data lines in a column inversion manner. The column type version scheme is a scheme of supplying data voltages of opposite polarities to neighboring data lines and maintaining the polarities of the data voltages supplied to the data lines to remain the same for one frame period. For example, each of the source drive ICs 12 supplies the p-2 data voltages DVp-2 with the first polarity during the Nth frame period as shown in FIG. 6, and the p-1 data voltages ( DVp-1) is supplied at the second polarity, p data voltages DVp are supplied at the first polarity, p + 1 data voltages DVp + 1 are supplied at the second polarity, and p is supplied. The +2 data voltages DVp + 2 are supplied at a first polarity. In addition, each of the source drive ICs 12 supplies the p-2 data voltages DVp-2 with the second polarity during the N + 1th frame period as shown in FIG. 6, and the p-1 data voltages ( DVp-1) is supplied at a first polarity, p data voltages DVp are supplied at a second polarity, p + 1 data voltages DVp + 1 are supplied at a first polarity, and p is supplied. The +2 data voltages DVp + 2 are supplied at a second polarity. In FIG. 6, although the first polarity is implemented as the positive polarity and the second polarity is the negative polarity, it should be noted that the present invention is not limited thereto. That is, the first polarity may be negative and the second polarity may be positive.

The gate drive circuit 13 sequentially outputs the gate pulses to the gate lines. For example, as illustrated in FIG. 6, the gate driving circuit 13 applies the q-2 gate pulse GPq-2 to the q-3 gate line Gq-3 in each of the Nth and N + 1th frame periods. Output, output a q-2 gate pulse GPq-2 to the q-2 gate line Gq-2, and output a q-1 gate pulse GPq to the q-1 gate line Gq-1 -1) to output the qth gate pulse GPq to the qth gate line Gq, and to output the q + 1th gate pulse GPq + 1 to the q + 1th gate line Gq + 1 Outputs a q + 2 th gate pulse GPq + 2 to a q + 2 th gate line Gq + 2, and outputs a q + 3 th gate pulse GPq to a q + 3 gate line Gq + 3 +3) Each of the gate pulses generates a gate high voltage (VGH) for a predetermined period. The predetermined period may be implemented as one horizontal period 1H. One horizontal period 1H means one line scanning time in which digital video data is written in pixels of one horizontal line in the display panel 10.

Hereinafter, a method of charging data voltages in subpixels during the first to seventh periods t1 to t7 of the Nth frame period will be described in detail with reference to FIGS. 5 and 6. The first period t1 is a period during which the q-3rd gate pulse GPq-3 is supplied to the qth-3rd gate line GPq-3, and the second period t2 is a q-2nd gate pulse ( GPq-2 is supplied to the q-2 gate line GPq-2, and in the third period t3, the q-1 gate pulse GPq-1 receives the q-1 gate line GPq-. The fourth period t4 is a period during which the qth gate pulse GPq is supplied to the qth gate line GPq, and the fifth period t5 is a period q + 1 gate pulse (1). GPq + 1 is a period in which the q + 1th gate line GPq + 1 is supplied, and a sixth period t6 includes a q + 2th gate pulse GPq + 2 in the q + 2th gate line GPq +. The seventh period t7 is a period during which the q + 3 th gate pulse GPq + 3 is supplied to the q + 3 th gate line GPq + 3.

During the first period t1, the first and sixth subpixels SP1 and SP6 charge the data voltage in response to the q-3rd gate pulse GPq-3. The first sub-pixel SP1 connected to the p-2 data line Dp-2 charges the p-2 data voltage DVp-2 of the first polarity. The sixth sub-pixel SP6 connected to the p + 1th data line Dp + 1 charges the p + 1th data voltage DVp + 1 of the second polarity.

During the second period t2, the second, third, fourth, and fifth subpixels SP2, SP3, SP4, and SP5 charge the data voltage in response to the q-2 gate pulse GPq-2. . The second sub-pixel SP2 connected to the p-1 data line Dp-1 charges the p-1 data voltage DVp-1 of the second polarity. The third sub-pixel SP3 connected to the p-th data line Dp charges the p-th data voltage DVp of the first polarity. The fourth sub-pixel SP4 connected to the p + 1th data line Dp + 1 charges the p + 1th data voltage DVp + 1 of the second polarity. The fifth sub pixel SP5 connected to the p + 2 th data line Dp + 2 charges the p + 2 th data voltage DVp + 2 of the first polarity.

During the third period t3, the eighth, ninth, tenth, and eleventh subpixels SP8, SP9, SP10, and SP11 charge the data voltage in response to the q-1 gate pulse GPq-1. . The eighth sub-pixel SP8 connected to the p-1 th data line Dp-1 charges the p-1 data voltage DVp-1 of the second polarity. The ninth sub-pixel SP9 connected to the p-th data line Dp charges the p-th data voltage DVp of the first polarity. The tenth sub-pixel SP10 connected to the p + 1th data line Dp + 1 charges the p + 1th data voltage DVp + 1 of the second polarity. The eleventh sub-pixel SP11 connected to the p + 2th data line Dp + 2 charges the p + 2th data voltage DVp + 2 of the first polarity.

During the fourth period t4, the seventh and twelfth subpixels SP7 and SP12 charge the data voltage in response to the qth gate pulse GPq. The seventh sub-pixel SP7 connected to the p-2 data line Dp-2 charges the p-2 data voltage DVp-2 of the first polarity. The twelfth sub-pixel SP12 connected to the p + 1th data line Dp + 1 charges the p + 1th data voltage DVp + 1 of the second polarity.

During the fifth period t5, the thirteenth, fourteenth, seventeenth, and eighteenth subpixels SP13, SP14, SP17, and SP18 charge the data voltage in response to the q + 1 th gate pulse GPq + 1. . The thirteenth sub-pixel SP13 connected to the p-1 th data line Dp-1 charges the p-1 data voltage DVp-1 of the second polarity. The fourteenth sub-pixel SP14 connected to the p-th data line Dp charges the p-th data voltage DVp of the first polarity. The seventeenth sub-pixel SP17 connected to the p + 1th data line Dp + 1 charges the p + 1th data voltage DVp + 1 of the second polarity. The eighteenth sub-pixel SP18 connected to the p + 2th data line Dp + 2 charges the p + 2th data voltage DVp + 2 of the first polarity.

During the sixth period t6, the twenty-first, twenty-second, twenty-third, and twenty-fourth subpixels SP21, SP22, SP23, and SP24 charge the data voltage in response to the q + 2 th gate pulse GPq + 2. . The twenty-first sub-pixel SP21 connected to the p-th data line Dp-1 charges the p-th data voltage DVp-1 having the second polarity. The twenty-second sub-pixel SP22 connected to the p-th data line Dp charges the p-th data voltage DVp of the first polarity. The twenty-third subpixel SP23 connected to the p + 1th data line Dp + 1 charges the p + 1th data voltage DVp + 1 of the second polarity. The 24 th sub-pixel SP24 connected to the p + 2 th data line Dp + 2 charges the p + 2 th data voltage DVp + 2 of the first polarity.

During the seventh period t7, the nineteenth and twentieth sub-pixels SP19 and SP20 charge the data voltage in response to the q + 3 th gate pulse GPq + 3. The nineteenth sub-pixel SP19 connected to the p-1 th data line Dp-1 charges the p-2 data voltage DVp-2 having the second polarity. The twentieth sub-pixel SP20 connected to the p th data line Dp charges the p th data voltage DVp of the second polarity.

In summary, the first sub-pixel SP1, the third sub-pixel SP3, the seventh sub-pixel SP7, the ninth sub-pixel SP9, the fourteenth sub-pixel SP14, and the twentieth sub-pixel SP20. ) Is the first sub-pixel SP1, the third sub-pixel SP3, the ninth sub-pixel SP9, the seventh sub-pixel SP7, the fourteenth sub-pixel SP14, and the twentieth sub-pixel SP20. In order, the data voltage of the first polarity is charged. The second sub-pixel SP2, the eighth sub-pixel SP8, the thirteenth sub-pixel SP13, the fifteenth sub-pixel SP15, the nineteenth sub-pixel SP19, and the twenty-first sub-pixel SP21 The second sub-pixel SP2, the eighth sub-pixel SP8, the fifteenth sub-pixel SP15, the thirteenth sub-pixel SP13, the twenty-first sub-pixel SP21, and the nineteenth sub-pixel SP19. 2 Charge the data voltage of polarity. The fourth sub-pixel SP4, the sixth sub-pixel SP6, the tenth sub-pixel SP10, the twelfth sub-pixel SP12, the seventeenth sub-pixel SP17, and the twenty-third sub-pixel SP23 In order of the sixth subpixel SP6, the fourth subpixel SP4, the tenth subpixel SP10, the twelfth subpixel SP12, the seventeenth subpixel SP17, and the twenty-third subpixel SP23. The data voltage of the second polarity is charged. The fifth sub-pixel SP5, the tenth sub-pixel SP10, the sixteenth sub-pixel SP16, the eighteenth sub-pixel SP18, the twenty-second sub-pixel SP22, and the twenty-fourth sub-pixel SP24 The fifth sub-pixel SP5, the tenth sub-pixel SP10, the sixteenth sub-pixel SP16, the eighteenth sub-pixel SP18, the twenty-second sub-pixel SP22, and the twenty-fourth sub-pixel SP24. 2 Charge the data voltage of polarity.

As a result, although each of the source drive ICs 12 supplies data voltages to the data lines in a column inversion manner, each of the first to twenty-fourth subpixels SP1 to SP24 has a polarity in which neighboring subpixels are opposite to each other. It is driven in a horizontal two-dot inversion scheme that is charged with the data voltage. As a result, the second embodiment of the present invention is a horizontal two-dot inversion method that can significantly reduce the power consumption (P) by the column inversion method and can suppress the DC afterimage, flicker, etc. of the liquid crystal. There is an advantage that can be driven. An effect of reducing power consumption (P) has been described in detail with reference to Equation (1).

As described above, the present invention forms sub-pixels so that the neighboring sub-pixels may be driven in a dot inversion manner in which neighboring sub-pixels are charged with data voltages of opposite polarities even though the source drive IC supplies data voltages of the same polarity for each line. do. As a result, the present invention can suppress the afterimage of the liquid crystal, flicker, and the like, and can reduce the power consumption of the source drive IC by reducing the number of polarity inversions of the data voltage.

In addition, the present invention controls two sub pixels that are continuous in the horizontal direction by using three gate lines, or controls four sub pixels that are continuous in the vertical direction by using six or seven gate lines. As a result, the present invention can increase the data voltage charging period than the DRD technology, thereby reducing the influence of the common voltage ripple. For this reason, the present invention can prevent image distortion and deterioration of image quality, and thus can improve image quality over DRD technology.

Furthermore, the present invention forms a common line in an undriven region where no data line is formed. As a result, the present invention can prevent the reduction of the aperture ratio due to the common line formed in the conventional drive region.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Pixel array 11: Timing controller
12: source drive IC 13: gate driving circuit

Claims (17)

A liquid crystal display panel including data lines, gate lines crossing the data lines, and a pixel array in which a plurality of sub pixels are formed;
A source drive integrated circuit configured to supply data voltages to the data lines such that polarities are alternately alternated every predetermined period in a column inversion manner; And
And a gate driving circuit for sequentially supplying gate pulses to the gate lines,
The pixel array may include two subpixels commonly connected to one data line among three subpixels existing on the same horizontal line, and one subpixel exclusively connected to another data line. A liquid crystal display device. The method of claim 1,
And two sub-pixels consecutive in the vertical direction are connected to two or three of the four consecutive gate lines. 3. The method of claim 2,
And a polarity between two sub pixels that are continuous in the vertical direction, and a polarity between two sub pixels that are continuous in the horizontal direction. 3. The method of claim 2,
The pixel array includes:
A first pixel including a first subpixel and a third subpixel connected to a j-1th data line, and a second subpixel connected to a jth data line;
A second pixel including a fourth subpixel connected to the jth data line, a fifth subpixel connected to a j + 1th data line, and a sixth subpixel connected to a j + 2th data line;
A third pixel including a seventh subpixel connected to a j-2th data line, an eighth subpixel connected to the j-1th data line, and a ninth subpixel connected to the jth data line; And
And a fourth pixel including a tenth and twelfth subpixels connected to the j + 1th and an eleventh subpixel connected to the jth + 2th data line. 5. The method of claim 4,
The first pixel and the second pixel are in a first horizontal line,
And the third and fourth pixels are on a second horizontal line which is a horizontal line different from the first horizontal line. 5. The method of claim 4,
The first subpixel, the second subpixel, the fifth subpixel, and the sixth subpixel are connected to a k-2 gate line, and the third subpixel, the fourth subpixel, the tenth subpixel, and the fifth subpixel are connected to the k-2 gate line. An eleventh subpixel is connected to a k-1th gate line, and the seventh subpixel, an eighth subpixel, a ninth subpixel, and a twelfth subpixel are connected to a kth gate line. . 5. The method of claim 4,
The source drive IC,
Supplying a data voltage of a first polarity to the j-2 th data line, the j th data line, and the j + 2 th data line, and a second polarity to the j-1 th data line and the j + 1 th data line A liquid crystal display device comprising supplying a data voltage of. The method of claim 7, wherein
The first subpixel, the third subpixel, and the eighth subpixel charge the data voltage of the second polarity in the order of the first subpixel, the third subpixel, and the eighth subpixel.
The second subpixel, the seventh subpixel, and the ninth subpixel charge the data voltage of the first polarity in the order of the second subpixel, the seventh subpixel, and the ninth subpixel.
The fourth subpixel, the sixth subpixel, and the eleventh subpixel charge the data voltage of the first polarity in the order of the sixth subpixel, the fourth subpixel, and the eleventh subpixel.
The fifth subpixel, the tenth subpixel, and the twelfth subpixel charge the data voltage of the second polarity in the order of the fifth subpixel, the tenth subpixel, and the twelfth subpixel. Display. 5. The method of claim 4,
The j-th data line is disposed between the first subpixel and the second subpixel and between the seventh and eighth subpixels.
The j th data line is disposed between the third and fourth sub pixels and between the ninth and tenth sub pixels.
The j + 1th data line is disposed between the fourth subpixel and the fifth subpixel and between the tenth and eleventh subpixels.
The common voltage line for supplying a common voltage to the common electrode may be disposed between the second and third subpixels, between an eighth and ninth subpixels, between the fifth and sixth subpixels. And an eleventh subpixel and a twelfth subpixel. The method of claim 1,
And four sub-pixels consecutive in the vertical direction are connected to four of six or seven consecutive gate lines. 11. The method of claim 10,
When divided into a first group including the upper two sub pixels and a second group including the lower two sub pixels among four consecutive sub pixels in the vertical direction,
The polarities of the subpixels in the first group are the same, the polarities of the subpixels in the second group are the same, and the polarities of the subpixels in the first group and the subpixels in the second group are different from each other. Liquid crystal display device. 11. The method of claim 10,
The pixel array includes:
A first pixel including a first sub pixel connected to a p-2 data line, a second sub pixel connected to a p-1 data line, and a third sub pixel connected to a p data line;
A second pixel including a fourth subpixel and a sixth subpixel connected to a p + 1th data line, and a fifth subpixel connected to a p + 2th data line;
A third pixel including a seventh subpixel connected to the p-2 data line, an eighth subpixel connected to the p-1 data line, and a ninth subpixel connected to the pth data line;
A fourth pixel including a tenth subpixel connected to the p + 1th and a twelfth subpixel, and an eleventh subpixel connected to the p + 2th data line;
A fifth pixel including a thirteenth and fifteenth subpixels connected to the p-1 data line, and a fourteenth subpixel connected to the pth data line;
A sixth pixel including a fifteenth subpixel connected to the pth data line, a sixteenth subpixel connected to a p + 1th data line, and a seventeenth subpixel connected to a p + 2th data line;
A seventh pixel including a nineteenth and twenty-first subpixels connected to the p-th data line and a twentieth subpixel connected to the p-th data line; And
An eighth pixel including a twenty-second subpixel connected to the p-th data line, a twenty-third subpixel connected to a p + 1th data line, and a twenty-fourth subpixel connected to a p + 2th data line Liquid crystal display device characterized in that. 13. The method of claim 12,
The first pixel and the second pixel are in a first horizontal line,
The third pixel and the fourth pixel are on a second horizontal line which is a horizontal line different from the first horizontal line,
The fifth and sixth pixels are on a third horizontal line which is a horizontal line different from the first and second horizontal lines,
And the seventh and eighth pixels are on a fourth horizontal line which is a horizontal line different from the first, second and third horizontal lines. 13. The method of claim 12,
The first subpixel and the sixth subpixel are connected to a q-3 gate line, and the second subpixel, the third subpixel, the fourth subpixel, and the fifth subpixel are connected to the q-2 gate line. And the eighth subpixel, the ninth subpixel, the tenth subpixel, and the eleventh subpixel are connected to the q-1 gate line, and the seventh subpixel, the twelfth subpixel, the fifteenth subpixel, and the seventh subpixel are connected. The sixteenth subpixel is connected to the qth gate line, the thirteenth subpixel, the fourteenth subpixel, the seventeenth subpixel, and the eighteenth subpixel are connected to the q + 1th gate line, the twenty-first subpixel, and the twenty-second subpixel The subpixel, the twenty-third subpixel, and the twenty-fourth subpixel are connected to a q + 2 gate line, and the 19th and 20th subpixels are connected to a q + 3 gate line. . 13. The method of claim 12,
The source drive IC,
Supply a data voltage having a first polarity to the p-2 data line, the p data line, and the p + 2 data line, and supply a second polarity to the p-1 data line and the p + 1 data line A liquid crystal display device comprising supplying a data voltage of. The method of claim 15,
The first subpixel, the third subpixel, the seventh subpixel, the ninth subpixel, the fourteenth subpixel, and the twentieth subpixel may include the first subpixel, the third subpixel, the ninth subpixel, and the seventh subpixel. The data voltage of the first polarity is charged in the order of the subpixel, the 14th subpixel, and the 20th subpixel,
The second subpixel, the eighth subpixel, the thirteenth subpixel, the fifteenth subpixel, the nineteenth subpixel, and the twenty-first subpixel include the second subpixel, the eighth subpixel, the fifteenth subpixel, and the thirteenth subpixel. A data voltage of the second polarity is charged in the order of the subpixel, the 21st subpixel, and the 19th subpixel,
The fourth subpixel, the sixth subpixel, the tenth subpixel, the twelfth subpixel, the seventeenth subpixel, and the twenty-third subpixel may include the sixth subpixel, the fourth subpixel, the tenth subpixel, and the twelfth subpixel. Charge the data voltage of the second polarity in the order of the sub-pixel, the seventeenth sub-pixel, and the twenty-third sub-pixel,
The fifth sub-pixel, the tenth sub-pixel, the sixteenth sub-pixel, the eighteenth sub-pixel, the twenty-second sub-pixel, and the twenty-fourth sub-pixel may include the fifth sub-pixel, the tenth sub-pixel, the sixteenth sub-pixel, and the eighteenth sub-pixel. And a data voltage of the second polarity in the order of the subpixel, the twenty-second subpixel, and the twenty-fourth subpixel. 13. The method of claim 12,
The p-1 data line is between the first subpixel and the second subpixel, between the seventh and eighth subpixels, between the thirteenth and fourteenth subpixels, and a nineteenth subpixel. Disposed between the subpixel and the twentieth subpixel,
The pth data line is between the third and fourth subpixels, between the ninth and tenth subpixels, between the fifteenth and sixteenth subpixels, and the twenty-first subpixel. Disposed between the twenty-second subpixels,
The p + 1th data line is between the fourth and fifth subpixels, between the tenth and eleventh subpixels, between the sixteenth and seventeenth subpixels, and a twenty-third subpixel. Disposed between the subpixel and the 24 th subpixel,
The common voltage line for supplying a common voltage to the common electrode may be disposed between the second and third subpixels, between an eighth and ninth subpixels, between a fourteenth and fifteenth subpixels. Between the 20th and 21st subpixels, between the fifth and sixth subpixels, between the eleventh and twelfth subpixels, between the seventeenth and eighteenth subpixels, and And a twenty-third subpixel and a twenty-fourth subpixel.

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