KR20130076458A - Method for fabricating nonvolatile memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a nonvolatile memory device is provided to increase the degree of integration by reducing the area of a unit. CONSTITUTION: A pass gate electrode layer (110) is formed on a substrate. A gate structure is formed on the pass gate electrode layer. A hole passing the gate structure and a part of the pass gate electrode layer is formed. The hole is separated from the grooves of the trench. A memory layer (140) and a channel layer (150A) are successively formed within the groove.

Description

Manufacturing method of nonvolatile memory device {METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE}

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a nonvolatile memory device having a three-dimensional structure in which a plurality of memory cells are stacked in a vertical direction from a substrate.

A nonvolatile memory device is a memory device in which stored data is retained even if the power supply is interrupted. Various non-volatile memory devices such as flash memory are widely used at present.

In particular, as the integration of a nonvolatile memory device having a two-dimensional structure that forms a memory cell as a single layer on a semiconductor substrate has recently reached its limit, a plurality of memory cells are formed along a channel layer protruding from the semiconductor substrate in a vertical direction. A nonvolatile memory device having a three-dimensional structure has been proposed. Specifically, the three-dimensional nonvolatile memory device is divided into a structure having a straight channel layer and a structure having a U-shaped channel layer.

1 is a perspective view illustrating a nonvolatile memory device having a three-dimensional structure according to the prior art.

Referring to FIG. 1, a three-dimensional nonvolatile memory device having a U-shaped channel layer includes a pair of main channels vertically protruding from the substrate 10 and a sub channel connecting the pair of main channels to each other. The channel layer 60, the memory layer 50 surrounding the channel layer 60, a plurality of interlayer insulating layers 30 and a plurality of gate electrodes 40 alternately stacked along the main channel, and the subchannel It may include an enclosing pass gate electrode 20.

Here, the U-shaped channel hole in which the channel layer 60 is buried forms a pair of main channel holes penetrating through the interlayer insulating film 30 and the gate electrode 40, and is formed in the pass gate electrode 20. The sacrificial layer pattern (not shown) may be removed to form sub channel holes connecting the pair of main channel holes to each other. However, in the related art, not only the main channel hole and the sub channel hole need to be formed separately, but also the sub channel hole is not exposed on the wafer surface, which causes a complicated and difficult manufacturing process.

On the other hand, there is a limit to repeatedly stacking the gate electrode 40 in the vertical direction from the substrate 10 in order to increase the degree of integration of the nonvolatile memory device. When the size of the device is reduced in the horizontal direction, the memory layer is formed in the U-shaped channel hole. The difficulty of forming the 50 and the channel layer 60 uniformly is such that there is a problem that the overall difficulty of the process is increased.

An embodiment of the present invention provides a method of manufacturing a nonvolatile memory device, in which a manufacturing process is simple and easy, and the density of a unit cell is reduced to increase the degree of integration.

A method of manufacturing a nonvolatile memory device according to an embodiment of the present invention includes forming a pass gate electrode layer on a substrate; Forming a gate structure in which a plurality of first material layers and a plurality of second material layers are alternately stacked on the pass gate electrode layer; Forming a hole passing through the gate structure and a part of the pass gate electrode layer; Forming a trench separating the gate structure while crossing the center of the hole to separate the hole into grooves on both sides of the trench; And sequentially forming a memory layer and a channel layer in the groove.

According to the present technology, it is possible to increase the density of the nonvolatile memory device by reducing the area occupied by the unit cell while simplifying and simplifying the manufacturing process.

1 is a perspective view illustrating a nonvolatile memory device having a three-dimensional structure according to the prior art.
2A to 2F are perspective views illustrating a nonvolatile memory device and a method of manufacturing the same according to the first embodiment of the present invention.
3A to 3G are perspective views illustrating a nonvolatile memory device and a method of manufacturing the same according to the second embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

2A to 2F are perspective views illustrating a nonvolatile memory device and a method of manufacturing the same according to the first embodiment of the present invention. In particular, FIG. 2F is a perspective view showing a nonvolatile memory device according to the first embodiment of the present invention, and FIGS. 2A to 2E are perspective views showing an example of an intermediate step in manufacturing the device of FIG. 2F.

Referring to FIG. 2A, a pass gate electrode layer 110 is formed on the substrate 100.

Here, the substrate 100 may be a semiconductor substrate such as single crystal silicon, and may include a predetermined lower structure (not shown). In addition, the pass gate electrode layer 110 may be formed of a conductive material, such as doped polysilicon or a metal, as the gate electrode of the pass transistor.

Subsequently, the plurality of interlayer insulating layers 120 and the plurality of gate electrode conductive layers 130 are alternately stacked on the pass gate electrode layer 110. Hereinafter, for convenience of description, a structure in which a plurality of interlayer insulating layers 120 and a plurality of gate electrode conductive layers 130 are alternately stacked will be referred to as a first gate structure.

The interlayer insulating layer 120 may be disposed on the lowermost and uppermost portions of the first gate structure, and the interlayer insulating layer 120 may be formed of an oxide-based material. In addition, the conductive layer 130 for the gate electrode is for forming the gate electrode of the memory cell or the selection transistor, and may be formed of a conductive material, for example, doped polysilicon or a metal. Meanwhile, although eight conductive layers 130 for gate electrodes are illustrated in this cross-sectional view, this is merely an example and may be formed above or below the gate electrode.

Referring to FIG. 2B, a portion of the conductive layer 130 for the gate electrode, the interlayer insulating layer 120, and the pass gate electrode layer 110 may be selectively etched to form a first trench T1 penetrating the first gate structure. The first trenches T1 may have a slit shape extending in one direction, and a plurality of first trenches T1 may be arranged in parallel.

As a result of this process, the first gate structure may be separated to have a line shape when viewed in plan view, and the remaining interlayer insulating layer 120 and the gate electrode conductive layer 130 may be respectively formed as the primary interlayer insulating layer pattern 120A. And the conductive layer pattern 130A for the gate electrode.

Referring to FIG. 2C, a hole H1 penetrating the first gate structure separated by selectively etching a portion of the conductive layer pattern 130A for the gate electrode, the first interlayer insulating layer pattern 120A, and the pass gate electrode layer 110. To form.

Here, the hole H1 may have an island shape having a short axis in the same direction as the first trench T1 and a long axis in a direction crossing the hole H1, and having a long axis of the separated first gate structure. Therefore, a plurality may be arranged in a line. The pass gate electrode layer 110 may be etched to a depth equal to the sum of the thicknesses of the memory layer and the channel layer, which will be described later.

Referring to FIG. 2D, the conductive layer pattern 130A for the gate electrode and the first interlayer insulating layer pattern 120A are selectively etched to form a second trench T2 penetrating the separated first gate structure. The second trench T2 may have a slit shape that extends in the same direction as the first trench T1 while crossing the center of the hole H1, and a plurality of second trenches T2 may be arranged in parallel.

As a result of this process, the first gate structure separated by the first trench T1 is separated again, and the remaining primary interlayer insulating film pattern 120A and the gate electrode conductive layer pattern 130A are respectively separated from the secondary interlayer insulating film pattern. Referred to as 120B and gate electrode 130B. In particular, the hole H1 is separated about the second trench T2 and forms a groove H2 recessed in a U shape along the inner wall of the second trench T2 in a direction crossing the second trench T2. The inner side surface of the separated first gate structure may have a concave-convex shape.

Referring to FIG. 2E, after forming the memory layer 140 along the inner wall of the second trench T2 including the groove H2, the semiconductor layer for the channel on the memory layer 140 may be filled with the groove H2. 150).

The memory film 140 may be formed by sequentially depositing a charge blocking film, a charge trap film, and a tunnel insulating film. At this time, the tunnel insulating film is for charge tunneling, for example, may be formed of an oxide film, and the charge trap film is for storing data by trapping charge, for example, made of a nitride film. It is for blocking the thing, for example, it may consist of an oxide film. That is, the memory layer 140 may have a triple layer structure of Oxide-Nitride-Oxide (ONO). Meanwhile, the channel semiconductor film 150 is for forming a channel layer, which will be described later, and may be formed of a semiconductor material, for example, polysilicon.

Referring to FIG. 2F, the channel semiconductor film 150 is separated to form the channel layer 150A in the groove H2. At this time, in order to separate the channel semiconductor film 150, an process such as etch-back may be performed until the inner surface of the memory film 140 is exposed.

Here, the channel layer 150A may include a portion used as a channel of a memory cell or a selection transistor and a portion used as a channel of a pass transistor, and the cross section may have a U shape.

By the manufacturing method described above, the nonvolatile memory device according to the first embodiment of the present invention as shown in FIG. 2F can be manufactured.

Referring to FIG. 2F, a nonvolatile memory device according to a first embodiment of the present invention may include a gate structure in which a plurality of secondary interlayer insulating layer patterns 120B and a plurality of gate electrodes 130B are alternately stacked, and the gate structure. A second trench T2 extending in one direction through the second trench T2, and a groove H2 recessed along an inner wall of the second trench T2 in a direction crossing the second trench T2 and a groove H2 The memory layer 140 may include a memory layer 140, a channel layer 150A on the memory layer 140, and a pass gate electrode layer 110 positioned below the gate structure and surrounding the channel layer 150A.

3A to 3G are perspective views illustrating a nonvolatile memory device and a method of manufacturing the same according to the second embodiment of the present invention. In the following description of the present embodiment, a detailed description of parts that are substantially the same as those of the above-described first embodiment will be omitted.

Referring to FIG. 3A, a pass gate electrode layer 110 is formed on the substrate 100. The substrate 100 may be a semiconductor substrate such as single crystal silicon, and the pass gate electrode layer 110 may be formed of a conductive material, for example, doped polysilicon or metal.

Subsequently, a plurality of interlayer insulating layers 120 and a plurality of sacrificial layers 125 are alternately stacked on the pass gate electrode layer 110. Hereinafter, for convenience of description, a structure in which a plurality of interlayer insulating layers 120 and a plurality of sacrificial layers 125 are alternately stacked will be referred to as a second gate structure.

The interlayer insulating layer 120 may be disposed on the lowermost and uppermost portions of the second gate structure, and the interlayer insulating layer 120 may be formed of an oxide-based material. In addition, the sacrificial layer 125 may be removed in a subsequent process and serve as a mold to provide a space in which a gate electrode, which will be described later, is formed. It can be formed of a material.

Referring to FIG. 3B, a portion of the sacrificial layer 125, the interlayer insulating layer 120, and the pass gate electrode layer 110 may be selectively etched to form a first trench T1 penetrating the second gate structure. The first trenches T1 may have a slit shape extending in one direction, and a plurality of first trenches T1 may be arranged in parallel.

As a result of this process, the second gate structure may be separated to have a line shape in plan view, and the remaining interlayer insulating film 120 and the sacrificial layer 125 may be respectively formed of the first interlayer insulating film pattern 120A and 1. It is referred to as a difference sacrificial layer pattern 125A.

Referring to FIG. 3C, a hole H1 penetrating a second gate structure separated by selectively etching a portion of the first sacrificial layer pattern 125A, the first interlayer insulating layer pattern 120A, and the pass gate electrode layer 110 may be formed. Form.

Here, the hole H1 may have an island shape having a short axis in the same direction as the first trench T1 and a long axis in a direction crossing the hole H1, and having a long axis of the separated second gate structure. Therefore, a plurality may be arranged in a line.

Referring to FIG. 3D, the first sacrificial layer pattern 125A and the first interlayer insulating layer pattern 120A are selectively etched to form a second trench T2 penetrating the separated second gate structure. The second trench T2 may have a slit form crossing the central portion of the hole H1 and extending in the same direction as the first trench T1.

As a result of this process, the second gate structure separated by the first trench T1 is separated again, and the remaining primary interlayer insulating layer pattern 120A and the primary sacrificial layer pattern 125A are respectively separated from the secondary interlayer insulating layer pattern ( 120B) and the second sacrificial layer pattern 125B. In particular, the hole H1 is separated about the second trench T2 and forms a groove H2 recessed in a U shape along the inner wall of the second trench T2 in a direction crossing the second trench T2. Done.

Referring to FIG. 3E, after forming the memory layer 140 along the inner wall of the second trench T2 including the groove H2, the semiconductor layer for the channel on the memory layer 140 may be filled with the groove H2. 150).

The memory layer 140 may be formed by sequentially depositing the charge blocking layer, the charge trap layer, and the tunnel insulating layer, and may have a triple layer structure of ONO (Oxide-Nitride-Oxide). Meanwhile, the channel semiconductor film 150 may be formed of a semiconductor material, for example, polysilicon.

Referring to FIG. 3F, the channel semiconductor film 150 is separated to form the channel layer 150A in the groove H2. At this time, in order to separate the channel semiconductor film 150, an process such as etch-back may be performed until the inner surface of the memory film 140 is exposed.

Here, the channel layer 150A may include a portion used as a channel of a memory cell or a selection transistor and a portion used as a channel of a pass transistor, and the cross section may have a U shape.

Referring to FIG. 3G, the second sacrificial layer pattern 125B exposed by the first trench T1 is removed. In this case, a wet etching process using an etching selectivity with the secondary interlayer insulating layer pattern 120B may be performed to remove the secondary sacrificial layer pattern 125B.

Subsequently, the gate electrode 160 is formed in the space where the second sacrificial layer pattern 125B is removed. Formation of the gate electrode 160 may be specifically performed by the following process. First, a conductive material such as a metal or a metal nitride is conformally deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form a secondary sacrificial layer pattern ( A conductive film for a gate electrode (not shown) is formed to fill the first trench T1 including the space from which 125B) is removed. Subsequently, the gate electrode conductive film formed in the first trench T1 is etched until the side surface of the second interlayer insulating layer pattern 120B is exposed to separate the gate electrode conductive film around the first trench T1. As a result of this process, the gate electrode 160 is formed between the secondary interlayer insulating film patterns 120B.

In the above-described second embodiment, after forming a structure in which a plurality of secondary interlayer insulating layer patterns 120B and a plurality of secondary sacrificial layer patterns 125B are alternately stacked, the second sacrificial layer pattern 125B is etched to form a structure. The gate electrode 160 is formed in a space from which the difference sacrificial layer pattern 125B is removed, which is different from the first embodiment.

According to the method of manufacturing the nonvolatile memory device according to the exemplary embodiment described above, the memory layer and the channel layer are formed through the trench having an opening larger than the hole while reducing the area occupied by the unit cell in order to increase the degree of integration. The buried property can be improved to form the memory film and the channel layer more uniformly. In addition, since the U-shaped channel layer can be formed at a time without a separate process using a sacrificial film pattern, the manufacturing process can be simplified and facilitated.

It should be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

100 substrate 110 pass gate electrode layer
120B: secondary interlayer insulating film pattern 125B: secondary sacrificial layer pattern
130B and 160: gate electrode 140: memory film
150A: channel layer H2: groove
T1: first trench T2: second trench

Claims (5)

Forming a pass gate electrode layer on the substrate;
Forming a gate structure in which a plurality of first material layers and a plurality of second material layers are alternately stacked on the pass gate electrode layer;
Forming a hole passing through the gate structure and a part of the pass gate electrode layer;
Forming a trench separating the gate structure while crossing the central portion of the hole to separate the hole into grooves on both sides of the trench; And
Sequentially forming a memory layer and a channel layer in the groove;
Method of manufacturing a nonvolatile memory device.
The method according to claim 1,
The first material layer is an interlayer insulating film,
The second material layer is a conductive layer
Method of manufacturing a nonvolatile memory device.
The method according to claim 1,
The first material layer is an interlayer insulating film,
The second material layer is a sacrificial layer
Method of manufacturing a nonvolatile memory device.
The method according to claim 1,
The hole is formed to have a short axis in the same direction as the trench and a long axis in a direction crossing the trench.
Method of manufacturing a nonvolatile memory device.
The method of claim 3,
After the memory film and channel layer forming step,
Etching the sacrificial layer to form a gate electrode in a space from which the sacrificial layer is removed;
Method of manufacturing a nonvolatile memory device.

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