CN108666323A - Semiconductor storage - Google Patents
Semiconductor storage Download PDFInfo
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- CN108666323A CN108666323A CN201711135070.8A CN201711135070A CN108666323A CN 108666323 A CN108666323 A CN 108666323A CN 201711135070 A CN201711135070 A CN 201711135070A CN 108666323 A CN108666323 A CN 108666323A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
Abstract
Embodiment provides a kind of semiconductor storage that can improve Reliability of Microprocessor.The semiconductor storage of one embodiment has：1st region (BLK), including along the 1st direction (X-direction) it is arranged side by side the 1st a plurality of wiring (SGD), by the 1st insulating film (SLT2) detached between the 1st adjacent wiring (SGD) and the 1st column (MP) being arranged in a manner of between the 1st adjacent wiring (SGD)；And the 2nd, the 3rd region (SLT1), it is positioned in a manner of the 1st region (BLK) is clipped in the middle on the 2nd direction (Y-direction), and include the 2nd insulating film.1st column (MP) includes conductive layer, gate insulating film and charge accumulating layer.Article number that the 1st wiring (SGD) in the 1st region (BLK) is arranged is odd number article.
Description
[related application]
The application was enjoyed with No. 2017-61208 (applying date of Japanese patent application：On March 27th, 2017) and Japan Patent
Apply for No. 2017-168249 (applying date：On September 1st, 2017) based on the priority applied.The application is by referring to the base
Plinth application and include basis application full content.
Technical field
Embodiment is related to a kind of semiconductor storage.
Background technology
It is known it is a kind of storage unit is dimensionally arranged made of semiconductor memory.
Invention content
Embodiment provides a kind of semiconductor storage that can improve Reliability of Microprocessor.
The semiconductor storage of embodiment has：1st region, including setting is square on a semiconductor substrate and along work
For direction in the face of semiconductor substrate the 1st direction it is arranged side by side the 1st a plurality of wiring, by the 1st adjacent wiring closet point
From the 1st insulating film and the 1st column that is arranged in a manner of across the 1st adjacent wiring closet；And the 2nd, the 3rd region, with half
The mode that the 1st region is clipped in the middle is positioned on direction and the 2nd direction different from the 1st direction in the face of conductor substrate, and is wrapped
Containing from semiconductor substrate setting to the 1st wiring height the 2nd insulating film.1st column includes conductive layer, gate insulating film and electricity
Lotus accumulation layer.Article number that the 1st wiring in the 1st region is arranged is odd number article.
Description of the drawings
Fig. 1 is the block diagram of the semiconductor storage of the 1st embodiment.
Fig. 2 is the circuit diagram of the memory cell array of the 1st embodiment.
Fig. 3 is the plane figure of the selection grid polar curve of the 1st embodiment.
Fig. 4 is the plane figure of the wordline of the 1st embodiment.
Fig. 5 is the sectional view of the block of the 1st embodiment.
Fig. 6 is the sectional view of the block of the 1st embodiment.
Fig. 7 is the sectional view of the memory cell transistor of the 1st embodiment.
Fig. 8 is the sectional view of the memory cell transistor of the 1st embodiment.
Fig. 9 is the sectional view of the memory cell transistor of the 1st embodiment.
Figure 10 is the sectional view of the memory cell transistor of the 1st embodiment.
Figure 11 is the equivalent circuit diagram of the storage column of the 1st embodiment.
Figure 12 is the plane figure of the selection grid polar curve of the 1st embodiment.
Figure 13 is the plane figure of the selection grid polar curve of the 1st embodiment.
The sequence diagram of various signals when Figure 14 is the reading operation of the 1st embodiment.
Figure 15 is the plane figure of the selection grid polar curve of the 1st change case of the 1st embodiment.
The sequence diagram of various signals when Figure 16 is the write activity of the 2nd embodiment.
The sequence diagram of various signals when Figure 17 is the write activity of the 2nd embodiment.
Figure 18 is the plane figure of the selection grid polar curve of the 3rd embodiment.
Figure 19 is the plane figure of the selection grid polar curve of the 3rd embodiment.
Figure 20 is the plane figure of the selection grid polar curve of the 3rd embodiment.
Figure 21 is the plane figure of the selection grid polar curve of the 3rd embodiment.
Figure 22 is the plane figure of the selection grid polar curve of the 1st change case of the 3rd embodiment.
Figure 23 is the plane figure of the selection grid polar curve of the 2nd change case of the 3rd embodiment.
Figure 24 is the plane figure of the selection grid polar curve of the 4th embodiment.
Figure 25 is the plane figure of the selection grid polar curve of the 1st change case of the 4th embodiment.
Figure 26 is the plane figure of the selection grid polar curve of the 2nd change case of the 4th embodiment.
Figure 27 is the plane figure of the wordline of the 1st change case of the 1st to the 4th embodiment.
Figure 28 is the equivalent circuit diagram of the storage column of the 2nd change case of the 1st to the 4th embodiment.
Figure 29 is the sectional view in a part of region of the storage column of the 3rd change case of the 1st to the 4th embodiment.
Specific implementation mode
Hereinafter, being illustrated to embodiment with reference to attached drawing.In addition, in the following description, to identical function and
The reference marks that the inscape mark of composition shares.
1. the 1st embodiment
The storage system of 1st embodiment is illustrated.Has NAND (Not AND, with non-) type flash hereinafter, enumerating
Memory for the storage system of semiconductor storage as illustrating.
1.1 about composition
The composition of the NAND type flash memory of present embodiment is illustrated.
1.1.1 about overall structure
First, the overall structure substantially of the NAND type flash memory of present embodiment is illustrated using Fig. 1.
As shown, NAND type flash memory 1 has memory cell array 2, row decoder 3 and sense amplifier 4.
Memory cell array 2 has multiple block BLK.4 block BLK0~BLK3, but its quantity are only shown in Fig. 1
And it is not limited.Block BLK, which is included in rows and columns, establishes association and dimensionally multiple storage units of lamination.In addition, block BLK
On a semiconductor substrate, slit SLT1 is arranged in setting between adjacent block.Hereinafter to the composition of memory cell array 2
Detailed content is described.
Row decoder 3 is decoded the row address being received externally.Then, row decoder 3 is selected based on decoding result
Select the line direction of memory cell array 2.More specifically, to for select line direction various wirings apply voltage.
Sense amplifier 4 reads the data read from either block BLK when reading data.In addition, in write-in data
When, voltage corresponding with write-in data is applied to memory cell array 2.
1.1.2 the composition about memory cell array 2
Next, being illustrated to the composition of the memory cell array 2 of present embodiment.
＜ constitutes ＞ about circuit
First, the circuit composition of memory cell array 2 is illustrated using Fig. 2.Fig. 2 is the equivalent circuit of block BLK
Figure.As shown, block BLK includes multiple memory group MG (MG0, MG1, MG2 ...).In addition, each memory group MG includes
Multiple NAND strings 50.Hereinafter, the NAND string of even number memory group MGe (MG0, MG2, MG4 ...) is known as NAND string 50e,
The NAND string of odd number memory group MGo (MG1, MG3, MG5 ...) is known as NAND string 50o.
Each NAND string 50 is for example comprising 8 memory cell transistor MT (MT0~MT7) and selection transistor ST1, ST2.
Memory cell transistor MT has control grid and charge accumulating layer, by data non-volatile preserves.Moreover, storage unit is brilliant
Body pipe MT is connected in series between the source electrode of selection transistor ST1 and the drain electrode of selection transistor ST2.
The grid of selection transistor ST1 in each memory group MGe be connected to selection grid polar curve SGD (SGD0,
SGD1、…).Selection grid polar curve SGD is independently controlled by row decoder 3.In addition, each even number memory group MGe
The grid of selection transistor ST2 in (MG0, MG2 ...) is for example common to be connected to selection grid polar curve SGSe, each odd number
The grid of selection transistor ST2 in memory group MGo (MG1, MG3 ...) is for example common to be connected to selection grid polar curve SGSo.Choosing
Selecting grid line SGSe and SGSo for example both can commonly connect, and can also can independently control.
In addition, memory cell transistor MT (MT0~MT7) included in memory group MGe in same block BLK
Grid is common respectively is connected to wordline WLe (WLe0~WLe7) for control.On the other hand, it is stored included in memory group MGo
The control grid of cell transistor MT (MT0~MT7) is common respectively to be connected to wordline WLo (WLo0~WLo7).Selection grid polar curve
WLe and WLo is independently controlled by row decoder 3.
Block BLK is, for example, the deletion unit of data.That is, the storage unit for being included in same block BLK is brilliant
The data that body pipe MT is preserved disposably are deleted.
In turn, positioned at the common company of drain electrode of the selection transistor ST1 of the NAND string 50 of same row in memory cell array 2
It is connected to bit line BL (BL0~BL (L-1), wherein the natural number that (L-1) is 2 or more).That is, bit line BL is in multiple storages
NAND string 50 is commonly connected between device group MG.In turn, the source electrode of multiple selection transistor ST2 is commonly connected to source electrode line
SL。
That is, memory group MG is connected to different bit line BL and is connected to same selection grid polar curve comprising multiple
The NAND string 50 of SGD.In addition, block BLK includes multiple memory group MG of multiple common word line WL.Moreover, storage unit battle array
Row 2 include multiple block BLK of shared bit line BL.Moreover, in memory cell array 2, by by the selection grid polar curve
SGS, wordline WL and selection grid polar curve SGD laminations side on a semiconductor substrate, and by memory cell transistor MT dimensionally laminations.
Plane figure ＞s of the ＜ about memory cell array
Next, the plane composition to memory cell array 2 illustrates.Fig. 3 indicates the semiconductor lining of a certain block BLK
The plane figure for the selection grid polar curve SGD for (being referred to as X/Y plane) in bottom surface.In this example, to including 8 in 1 block BLK
The case where selection grid polar curve SGD, illustrates.
As shown, (10-0~10-7, wherein 10-0 include 10-0a and 10- to 9 conductive layers 10 extended in X direction
0b) arranged along the Y-direction orthogonal with X-direction.Alternatively grid line SGD is functioned each conductive layer 10.If it is Fig. 3's
Example, then 2 wiring layers 10-0a and 10-0b being located at both ends along the Y direction in block BLK are alternatively grid lines
SGD0 is functioned.That is, 2 wiring layers 10 at the both ends in Y-direction mutually commonly connect, or solved by row
Code device 3 is controlled in an identical manner.Moreover, 7 wiring layer 10-1~10-7 between them are respectively as selection
Grid line SGD1~SGD7 is functioned.Therefore, in the case of being observed with X/Y plane in block BLK, memory group
MG1~MG7 is arranged along the Y direction, and in its both sides configuration memory group MG0.
10 not shown insulating film of wiring layer adjacent in the Y direction separates in block BLK.The insulating film will be set
Region be known as slit SLT2.In slit SLT2, insulating film will be for example from semiconductor substrate face at least to setting wiring layer 10
Layer until region embedment.In addition, in memory cell array 2, such as multiple areas shown in Fig. 3 are arranged in the Y direction
Block BLK.Moreover, also not shown insulating film separates between adjacent block BLK in the Y direction.The area of the insulating film is set
Domain is the slit SLT1 described in Fig. 1.Slit SLT1 is also identical as SLT2.
In turn, in the Y direction between adjacent wiring layer 10 setting respectively along Z-direction multiple storage column MP (MP0~
MP15).Z-direction is the direction orthogonal with the directions XY, that is, the direction vertical with semiconductor substrate face.
Specifically, setting storage the column MP0 and MP8 between wiring layer 10-1 and 10-2, in wiring layer 10-3 and 10-4
Between setting storage column MP1 and MP9, between wiring layer 10-5 and 10-6 setting storage column MP2 and MP10, in wiring layer 10-7
The setting storage column MP3 and MP11 between 10-0b.Storage column MP is to form selection transistor ST1 and ST2 and storage unit crystalline substance
The tectosome of body pipe MT, detailed content will be described hereinafter.
Storage column MP0~MP3 is arranged along the Y direction.In addition, storage column MP8~MP11 in the X direction with storage column
Mode adjacent MP0~MP3 arranges along the Y direction.That is, storage column MP0~MP3 and storage column MP8~MP11 is side by side
Ground arranges.
Moreover, bit line BL0 is arranged in the top of wiring layer 10 in a manner of being commonly connected to storage column MP0~MP3.
In addition, bit line BL2 is arranged in the top of wiring layer 10 in a manner of being commonly connected to storage column MP8~MP11.Hereinafter, having
When will storage column MP0~MP3 and storage column MP8~MP11 and bit line BL0 and BL2 be known as group a GR1.
In addition, setting storage the column MP4 and MP12 between wiring layer 10-0a and 10-1, wiring layer 10-2 and 10-3 it
Between setting storage column MP5 and MP13, between wiring layer 10-4 and 10-5 setting storage column MP6 and MP14, in wiring layer 10-6
The setting storage column MP7 and MP15 between 10-7.
Storage column MP4~MP7 is arranged along the Y direction, and storage column MP12~MP15 is also to arrange along the Y direction.Moreover, depositing
Column MP4~MP7 is stored up in the X direction to be located between storage column MP0~MP3 and storage column MP8~MP11.In addition, storage column MP12
~MP15 in a manner of storage column MP8~MP11 is clipped in the middle together with storage column MP4~MP7 to position in the X direction.Also
It is to say, storage column MP4~MP7 and storage column MP12~MP15 are arranged side by side.
Moreover, bit line BL1 is arranged in the top of wiring layer 10 in a manner of being commonly connected to storage column MP4~MP7.
In addition, bit line BL3 is arranged in the top of wiring layer 10 in a manner of being commonly connected to storage column MP12~MP15.Hereinafter,
It sometimes will storage column MP4~MP7 and storage column MP12~MP15 and bit line BL1 and BL3 a referred to as group GR2.
That is, storage column MP is across 2 wiring layers 10 and to be embedded to the one of any slit SLT2 in the Y direction
Partial mode is arranged, and there are 1 slit SLT2 between storage column MP adjacent in the Y direction.Moreover, for belonging to group GR1's
The slit SLT2 of storage column MP embedments, which is located at, to be belonged between 2 storage column MP of group GR2, for belonging to the storage column MP embedments of group GR2
Slit SLT2 be located at belong between 2 storage column MP of group GR1.
In addition, storage column MP is not arranged across slit SLT1 and between adjacent wiring layer 10-0a and 10-0b.
Fig. 4 indicates the plane figure of the wordline WL in X/Y plane in the same manner as Fig. 3.The area of 1 block size of Fig. 4 and Fig. 3
Domain corresponds to, and is provided in the layout for the wiring layer 11 that lower layer is more leaned on than wiring layer 10 illustrated in fig. 3.
As shown, (11-0~11-7, wherein 11-0 include 11-0a and 11- to 9 conductive layers 11 extended in X direction
0b) arrange along the Y direction.Each wiring layer 11-0~11-7 is arranged across insulating film in the underface of wiring layer 10-0~10-7.
Each conductive layer 10 is functioned as wordline WL7.Other wordline WL0~WL6 are also identical.If it is the example of Fig. 4,
So wiring layer 11-0a, 11-3,11-5,11-7 and 11-0b is functioned as wordline WLo7.Moreover, these wiring layers 11-
0a, 11-3,11-5,11-7 and 11-0b are drawn out to end (end is known as the 1st interconnecting piece) along the X direction, and phase
Mutually commonly connect.Moreover, in the 1st interconnecting piece, wiring layer 11-0a, 11-3,11-5,11-7 and 11-0b are connected to capable decoding
Device 3.
In addition, wiring layer 11-1,11-3,11-5 and 11-7 are functioned as wordline WLe7.Moreover, these wiring layers
11-1,11-3,11-5 and 11-7 are drawn out to the 2nd interconnecting piece being located in the X direction with the 1st interconnecting piece is opposite side, and phase
Mutually commonly connect.Moreover, in the 2nd interconnecting piece, wiring layer 11-1,11-3,11-5 and 11-7 are connected to row decoder 3.
Moreover, storage unit portion is arranged between the 1st interconnecting piece and the 2nd interconnecting piece.In storage unit portion, in the Y direction
Upper adjacent wiring layer 11 is separated by slit SLT2 illustrated in fig. 3.In addition, matching between adjacent block BLK in the Y direction
Line layer 11 is similarly separated by slit SLT1.In addition, in storage unit portion, storage is set in a manner of identical with Fig. 3
Column MP0~MP15.
It is described be formed in it is other formed wordline WL and selection grid polar curve SGS layers in it is also identical.
Cross-sectional configuration ＞s of the ＜ about memory cell array
Next, being illustrated to the cross-sectional configuration of memory cell array 2.Fig. 5 is cuing open for block BLK along the Y direction
View, and the cross-sectional configuration in the region for the bit line BL0 being showing along in Fig. 3 is as an example.
It is played as shown, being provided as selection grid polar curve SGS in the top of semiconductor substrate (such as p-type well region domain) 13
The wiring layer 12 of function.In the top of wiring layer 12, the 8 layers of wiring layer 11 functioned as wordline WL0~WL7 are along the side Z
To lamination.The plane figure of these wirings 11 and 12 is Fig. 4.Moreover, being provided as selection grid polar curve in the top of wiring layer 11
The wiring layer 10 that SGD is functioned.The plane figure of wiring layer 10 is as illustrated in Figure 3.
Moreover, by from wiring layer 10 in a manner of reaching semiconductor substrate 13 by slit SLT2 and storage column MP along the side Y
To being alternately arranged.As described above, the entity of slit SLT2 is insulating film.However, it is also possible to will be used for being arranged in semiconductor
It applies alive contact plunger etc. and is arranged in slit SLT2 in region in substrate 13.For example, it is also possible to be arranged for that will select
The source electrode of transistor ST2 is connected to the contact plunger of source electrode line.
Moreover, wiring layer 12 by slit SLT2 or storage column MP be clipped in the middle and alternately as selection grid polar curve SGSo or
SGSe is functioned.Similarly, wiring layer 11 by slit SLT2 or storage column MP be clipped in the middle and alternately as wordline WLo or
WLe is functioned.
In addition, slit SLT1 is arranged between block BLK adjacent in the Y direction.As described above, the entity of slit SLT1
It is insulating film.However, it is also possible to by being set for applying alive contact plunger etc. to the region in semiconductor substrate 13 is arranged
It sets in slit SLT1.For example, it is also possible to which the contact plunger for the source electrode of selection transistor ST2 to be connected to source electrode line is arranged
Or the conductor of groove shape.In addition, the width of slit SLT1 along the Y direction is more than the width of slit SLT2 along the Y direction.
Moreover, contact plunger 16 is set on storage column MP, and in a manner of being commonly connected to these contact plungers 16
The wiring layer 15 functioned as bit line BL is set along the Y direction.
Fig. 6 is the sectional view of block BLK along the X direction, the selection grid polar curve SGD3 being showing along in Fig. 3 and by depositing
Store up the cross-sectional configuration in the region of column MP5 and MP13 as an example.As illustrated in fig. 5, above semiconductor substrate 13 according to
It is secondary that wiring layer 12,11 and 10 is set.About storage unit portion, as illustrated by using Fig. 5.
In the 1st interconnecting piece, wiring layer 10~12 is for example stepped to be brought out.That is, when being seen with X/Y plane
When examining, the end upper surface of 7 layers of wiring layer 10 and wiring layer 12 is exposed in the 1st interconnecting piece.Moreover, being set on the region of the exposing
Contact plunger 17 is set, and contact plunger 17 is connected to metallic wiring layer 18.Moreover, by the metallic wiring layer 18, make as idol
What number selection grid polar curve SGD0, SGD2, SGD4 and SGD6, even wordline WLo and even number selection grid polar curve SGSo were functioned matches
Line layer 10~12 is electrically connected to row decoder 3.
On the other hand, in the 2nd interconnecting piece, in an identical manner by wiring layer 11 and 12 for example stepped extractions.Moreover,
Contact plunger 19 is set on the region that wiring layer 11 and 12 is exposed, and contact plunger 19 is connected to metallic wiring layer 20.And
And by the metallic wiring layer 20, make as odd number selection grid polar curve SGD1, SGD3, SGD5 and SGD7, positions of odd wordlines WLe and
The wiring layer 11 and 12 that odd number selection grid polar curve SGSe is functioned is electrically connected to row decoder 3.In addition, wiring layer 10 can also
It is electrically connected to row decoder 3 instead of the 1st interconnecting piece via the 2nd interconnecting piece, can also be connected via the 1st interconnecting piece and the 2nd
Both portions and connect.
＜ is about storage column and the construction ＞ of memory cell transistor
Next, being illustrated to the construction for storing column MP and memory cell transistor MT.
About the 1st
First, it is illustrated using Fig. 7 and Fig. 8 couples the 1st.Fig. 7 is the sectional view in the X/Y plane for store column MP, Fig. 8
It is the sectional view in YZ planes, the region of 2 memory cell transistor MT of setting is especially shown.In addition, the 1st is single in storage
The charge accumulating layer of first transistor MT uses insulating film.
As shown, storage column MP include the insulating layer 30, semiconductor layer 31 and the insulating layer 32 that are arranged along the Z direction to
34.Insulating layer 30 is, for example, silicon oxide film.Semiconductor layer 31 is arranged in a manner of surrounding around insulating layer 30, and as confession
The region for forming the channel of memory cell transistor MT functions.Semiconductor layer 31 is, for example, polysilicon layer.Insulating layer 32 is
It is arranged in a manner of surrounding around semiconductor layer 31, and the gate insulating film as memory cell transistor MT functions.
Insulating layer 32 is for example constructed with the lamination of silicon oxide film and silicon nitride film.Insulating layer 33 is to surround around semiconductor layer 31
Mode be arranged, and the charge accumulating layer as memory cell transistor MT functions.Insulating layer 33 is, for example, silicon nitride film.
Insulating layer 34 is to be arranged in a manner of surrounding around insulating layer 33, and sent out as the blocking insulating film of memory cell transistor MT
Wave function.Insulating layer 34 is, for example, silicon oxide film.Embedment has insulating layer 37 in the slit SLT2 in addition to the portions storage column MP.Absolutely
Edge layer 37 is, for example, silicon oxide film.
Moreover, such as AlO layers 35 are arranged around the storage column MP of the composition.Example is formed around AlO layers 35
Such as shielding metal leve (TiN film) 36.The conductive layer 11 that wordline WL is functioned is provided as around shielding metal leve 36.
Tungsten is for example arranged to material by conductive layer 11.
According to the composition 2 memory cell transistor MT are set along the Y direction in 1 storage column MP.Selection
Transistor ST1 and ST2 also composition having the same.
About the 2nd
Next, being illustrated using Fig. 9 and Figure 10 couples the 2nd.Fig. 9 is the sectional view in the X/Y plane for store column MP,
Figure 10 is the sectional view in YZ planes, especially shows the region of 2 memory cell transistor MT of setting.2nd is single in storage
The charge accumulating layer of first transistor MT uses conductive film.
As shown, storage column MP include the insulating layer 48 being arranged along the Z direction and 43, semiconductor layer 40, insulating layer 41,
Conductive layer 42 and insulating layer 46a~46c.Insulating layer 48 is, for example, silicon oxide film.Semiconductor layer 40 is to surround insulating layer 43-1
Around mode be arranged.Semiconductor layer 40 is, for example, polysilicon layer, and as the channel for forming memory cell transistor MT
Region function, in the same manner as the example of Fig. 7, between the memory cell transistor MT in same storage column MP not by
Separation.Insulating layer 41 is arranged around conductive layer 40, and the gate insulating film as each memory cell transistor MT functions.
That is, 2 regions are separated into the X/Y plane shown in Fig. 9 of insulating layer 41, and respectively as in same storage column MP
The gate insulating film of 2 memory cell transistor MT function.Insulating layer 41 is for example with silicon oxide film and silicon nitride film
Lamination construction.Conductive layer 42 is arranged around insulating layer 41, and is separated into 2 regions by insulating layer 43 along the Y direction.It leads
Electric layer 42 is, for example, polysilicon layer, and 2 regions made of detaching are respective respectively as 2 memory cell transistor MT
Charge accumulating layer functions.In addition, insulating layer 43 is, for example, silicon oxide film.Insulating layer is set gradually around conductive layer 42
46a, 46b and 46c.Insulating layer 46a and 46c are, for example, silicon oxide film, and insulating layer 46b is, for example, silicon nitride film, they are used as and deposit
The blocking insulating film of storage unit transistor MT functions.These insulating layers 46a~46b is separated into 2 areas also along Y-direction
Domain, and insulating layer 43 is set between them.In addition, insulating layer 43 is embedded in slit SLT2.Insulating layer 43 is, for example, oxygen
SiClx film.
Moreover, such as AlO layers 45 are arranged around the storage column MP of the composition.In turn, the shape around AlO layers 45
At such as shielding metal leve (TiN film etc.) 47.Moreover, being provided as what wordline WL was functioned around shielding metal leve 47
Conductive layer 11.
According to the composition 2 memory cell transistor MT are set along the Y direction in 1 storage column MP.Selection
Transistor ST1 and ST2 also composition having the same.Do not scheme in addition, being arranged between memory cell transistor adjacent in z-direction
The insulating layer shown, by the insulating layer and insulating layer 43 and 46, to charge accumulating layer 42 and each memory cell transistor
Each insulation.
About equivalent circuit
Figure 11 is the equivalent circuit diagram of the storage column MP of the composition.As shown, forming 2 in 1 storage column MP
NAND string 50o and 50e.That is, being arranged mutually different selection is connected in the selection transistor ST1 of same storage column MP
Grid line SGD, memory cell transistor MT are connected to mutually different wordline WLo and WLe, and selection transistor ST2 is also connected to
Mutually different selection grid polar curve SGSo and SGSe.Moreover, 2 NAND strings 50o and 50e in same storage column MP are connected to together
One bit line BL, in addition, being connected to same source line SL.But current path is electrically separated from each other.
1.2 about reading operation
Next, being illustrated to the reading method of the data in the NAND type flash memory of the composition.
First, the selected states of selection grid polar curve SGD are illustrated using Figure 12 and Figure 13.On Figure 12 and Figure 13 is
The plane figure of the selection grid polar curve SGD in X/Y plane corresponding with Fig. 3 illustrated in text, and pair with selected selection
The corresponding wiring layers 10 of grid line SGD mark oblique line and indicate.
As shown in figure 12, when selecting any of grid line SGD1~SGD7 to be selected, corresponding 1 wiring is selected
Any of layer 10-1~10-7.The selected situations of selection grid polar curve SGD1 are shown in FIG. 12.By selecting wiring layer
10-1, and it is alternatively provided at 4 memory cell transistor MT of storage column MP0, MP4, MP8 and MP12.That is, by belonging to
In the 4 memory cell transistor MT shapes for the wiring layer 11-1 corresponding with any wordline WL being arranged immediately below wiring layer 10-1
At page 1.The situation is selected also the same in selection grid polar curve SGD2~SGD7.
In contrast, being selected simultaneously positioned at both the wiring layer 10-0a and 10-0b at both ends in block BLK.The situation
It is equivalent to the selected situations of selection grid polar curve SGD0.The state is shown in Figure 13.
As shown, when selecting grid line SGD0 to be selected, selection is located at immediately below wiring layer 10-0a and setting is being deposited
Store up 2 memory cell transistor MT of column MP4 and MP12 with immediately below wiring layer 10-0b and setting in storage column MP3 and
2 memory cell transistor MT of MP11.That is, forming page 1 by this 4 memory cell transistor MT.
Figure 14 is to indicate to select odd-numbered selection grid polar curve SGDo (namely odd number memory group MG) and wordline
The sequence diagram of the voltage change of various wirings when WLo0.
As shown, first, in moment t1, voltage VSG is applied to all selection grid polar curve SGD in selection block BLK,
Selection transistor ST1 is set as on-state.In turn, voltage VREAD is applied to all wordline, no matter preserving how data will
Memory cell transistor MT is set as on-state.In turn, voltage VSG is applied to all selection grid polar curve SGS, by selection transistor
ST2 is set as on-state.As a result, in selecting block BLK, all NAND strings 50 become conducting state, and by VSS (such as 0V)
It is transmitted to channel.
Then, in moment t3, sense amplifier 4 is to bit line BL into line precharge.At this point, belonging to the even bitlines of group GR1
BL0 and BL2 is precharged to voltage VBL2, and the odd bit lines BL1 and BL3 for belonging to group GR2 are precharged to more than voltage VBL2
Voltage VBL1.
Then, in moment t4, voltage VSG is applied to selected selection grid polar curve SGD and SGSo, to selecting wordline WLo0
Apply read-out voltage VCGRV, voltage VNEG is applied to non-selection wordline WLe0, and apply other non-selection wordline WL1~WL7.
Voltage VCGRV is voltage corresponding with level is read, and is the preservation number for judging selected memory cell transistor MT
According to the voltage for being " 0 " or " 1 ".Voltage VNEG is, for example, negative voltage or 0V, is for making memory cell transistor MT disconnect
Voltage.
Above result is, if selected memory cell transistor MT is connected, electric current will be flowed from bit line BL
It, will not circulating current if selected memory cell transistor MT is disconnected to source electrode line SL.It is selected thereby, it is possible to judge
The preservation data of the memory cell transistor MT selected.
The effect of 1.3 present embodiments
According to the present embodiment, the deviation of the memory cell characteristics between memory group MG can be corrected, is partly led to improve
The Reliability of Microprocessor of body storage device.This effect is illustrated below.
If it is the semiconductor storage of present embodiment, then as illustrated by Fig. 3 and Fig. 4,1 storage column MP
It is to be arranged in a manner of across arranged in X/Y plane 2 selection grid polar curve SGD and 2 wordline WL.Moreover, in the storage column
2 memory cell transistor MT are set in MP, and by 2 selection grid polar curve SGD and wordline WL controls.
Moreover, if it is this composition, then there is storage column MP and corresponding 2 wordline WL (and selection grid polar curve SGD)
Position relationship generate deviation the case where.More specifically, in Fig. 3 and Fig. 4, the case where being conceived to a certain storage column MP
Under, the central part in the Y-direction of column MP is preferably stored in the middle of corresponding 2 wordline.This is because passing through
Configuration storage column MP in this way, and become by the size of 2 memory cell transistor MT of corresponding 2 wordline WL controls
It is equal.
However, if the position of storage column MP shifts, the size of corresponding 2 memory cell transistor MT is not
Together.For example, if it is the example of Fig. 3 and Fig. 4, then storage column MP is deviated towards the sides wiring layer 10-0a along the Y direction.Its result
For when being conceived to wiring layer 10-1 and 11-1 and storage column MP0 and MP4, storage column MP0 is Chong Die with wiring layer 10-1 and 11-1
Distance d1, storage column MP4 and wiring layer 10-1 and 11-1 overlap distance d2, and there are the relationships of d1 ＞ d2.The situation is storing
There is also identical relationships between column MP8 and MP12.
That is, in the case where being conceived to memory group MG1, it is connected to the storage unit crystal of even bitlines BLe
The unit size of pipe MT is big, and the unit size for being connected to the memory cell transistor MT of odd bit lines BLo is small.Unit size it is big
The size of the small current driving ability that can also be said to be memory cell transistor MT.
That is, can define according to fig. 3, in the case where having selected even-numbered selection grid polar curve SGDe, it is connected to
The memory cell transistor MT of bit line BL0 and BL2, the size for the memory cell transistor MT for namely belonging to group GR1 are small.It is another
Aspect is connected to the ruler of the memory cell transistor MT of bit line BL1 and BL3, the memory cell transistor for namely belonging to group GR2
It is very little big.
On the contrary, in the case where having selected odd-numbered selection grid polar curve SGDo, it is connected to the storage of bit line BL0 and BL2
Cell transistor MT, the size for the memory cell transistor MT for namely belonging to group GR1 are big.On the other hand, it is connected to bit line BL1
And the memory cell transistor MT of BL3, the size for the memory cell transistor for namely belonging to group GR2 are small.
As described above, when the position for storing column MP shifts, in same one page, the different storage unit crystal of size
Pipe MT is alternately arranged.Therefore, in the present embodiment, sense amplifier 4 is according to selected memory cell transistor MT's
Size controls precharge potential when reading operation.
More specifically, when selecting even-numbered selection grid polar curve SGDe, namely even number memory group MGe,
Sense amplifier 4 applies the bit line BL of group GR1 big precharge potential VBL1, applies small preliminary filling to the bit line BL of group GR2
Electric potential VBL2.On the other hand, when selecting odd-numbered selection grid polar curve SGDo, namely odd number memory group MGo,
Sense amplifier 4 applies the bit line BL of group GR1 small precharge potential VBL2, applies big preliminary filling to the bit line BL of group GR2
Electric potential VBL1.
As a result, electricity caused by unit size of the precharge potential counteracting because of memory cell transistor MT can be utilized
The difference for flowing driving force, residual quantity of the cell current of bit line BL between bit line is flowed in reading operation so as to reduce.Also
It is to say, the memory cell transistor MT to being not easy flow-through cell electric current assigns the condition for the big cell current that fully circulates, right
The memory cell transistor MT for being easy to flow-through cell electric current assigns the condition for inhibiting cell current.Thereby, it is possible to inhibit especially to come
From the generation of the memory cell transistor MT for being not easy flow-through cell electric current misread out, so as to improve semiconductor storage
Reliability of Microprocessor.
In addition, if it is the composition of present embodiment, then as shown in figure 3, being located at the wiring layer at the both ends of block BLK
10-0a and 10-0b is selected simultaneously, and alternatively grid line SGD0 is functioned.This is because in other wiring layer 10-
1~10-7 is respectively formed 4 storage column MP (memory cell transistor MT), in contrast, at wiring layer 10-0a and 10-0b points
2 storage column MP (memory cell transistor MT) are not only formed.Accordingly, with respect to the both ends of block BLK, make 2 wiring layer 10-
0a and 10-0b is electrically functioned as 1 selection grid polar curve SGD, even if selecting selection grid polar curve SGD0 as a result,
When, it is identical when can also make the size of page 1 with the case where having selected other selection grid polar curve SGD1~SGD7.
Moreover, making the page size consistent results be in the above-described manner, as shown in figure 3, the alternatively grid in 1 block BLK
The number for the wiring layer 10 that polar curve SGD is functioned becomes odd number in X/Y plane.The situation for making as shown in Figure 4
It is also identical for the wiring layer 11 functioned for wordline WL.In other words, when being observed with X/Y plane, it is located at slit
The quantity of wiring layer between SLT1 becomes odd number.
In addition, the offset manner of storage column MP may be the situation opposite with Fig. 3 and Fig. 4.By state in this case
It is shown in Figure 15.Figure 15 indicates the plane figure of the selection grid polar curve SGD of the change case of present embodiment.As shown, in this example,
The case where storing position and Fig. 3 of column MP is on the contrary, be to be deviated along the Y direction towards the sides wiring layer 10-0b.As a result, when having in mind
When wiring layer 10-1 and 11-1 and storage column MP0 and MP4, storage column MP0 and wiring layer 10-1 and 11-1 overlap distance d2 is deposited
Store up column MP4 and wiring layer 10-1 and 11-1 overlap distance d1.In this case, voltage and the institute of bit line BL are applied to when reading
The case where stating embodiment is opposite.
That is, when selecting even-numbered selection grid polar curve SGDe, namely even number memory group MGe, read
Go out amplifier 4 and apply small precharge potential VBL2 to the bit line BL of group GR1, big precharge is applied to the bit line BL of group GR2
Current potential VBL1.On the other hand, it when selecting odd-numbered selection grid polar curve SGDo, namely odd number memory group MGo, reads
Go out amplifier 4 and apply big precharge potential VBL1 to the bit line BL of group GR1, small precharge is applied to the bit line BL of group GR2
Current potential VBL2.
2. the 2nd embodiment
Next, being illustrated to the semiconductor storage of the 2nd embodiment.Present embodiment is about the described 1st
Write activity in embodiment.Hereinafter, only a pair aspect different from the 1st embodiment illustrates.
2.1 the 1st
First, the 1st is illustrated.The write activity of data includes：Programming action injects electrons into charge accumulation
Layer and make changes of threshold；And programming verification action, confirm whether result, the i.e. threshold value of programming action reaches specified value.1st is
In programming action, the voltage for being applied to bit line BL is different from GR2 in group GR1.
Figure 16 is to indicate to select odd-numbered selection grid polar curve SGDo (namely odd number memories when data are written
Group MG) and various wirings when wordline WLo0 voltage change sequence diagram.
As shown in FIG. 12 and 13, in the case where selecting odd-numbered selection grid polar curve SGDo, belong to a group GR1 (BL0,
BL2 the size of memory cell transistor MT) is big, and the memory cell transistor MT for belonging to a group GR2 (BL1, BL3) is small.Because of word
Line WL and the more big then coupling ratio of overlapping area of storage column MP are bigger, so the writing speed of memory cell transistor MT is faster.
That is, the writing speed of group GR1 is fast, group GR2 is slow.
Therefore, in moment t2, sense amplifier 4 applies relatively high voltage to the bit line BL0 and BL2 that belong to group GR1
VCH2, bit line BL1 and BL3 to belonging to group GR2 apply low voltage VCH1.Certainly, VCH2 ＞ VCH1.
Then, in moment t3, row decoder 3 applies voltage VPASS to all wordline WL0~WL7, and then makes in moment t5
The voltage of selection wordline WLo0 rises to VPGM from VPASS.No matter voltage VPASS is to preserve how data make storage unit brilliant
The voltage that body pipe MT is connected and channeling potential can be made fully to increase by coupling in non-selected NAND string 50.In addition,
Voltage VPGM is to inject electrons into charge accumulating layer then for being worn by FN (Fowler-Nordheim, Fowler-Nordheim)
High voltage, and VPGM ＞ VPASS.
According to this method, by increasing bit-line voltage corresponding with the higher memory cell transistor MT of writing speed, energy
Enough reduce its writing speed.Thereby, it is possible to reduce the difference of the writing speed group between GR1 and GR2.
2.2 the 2nd
Next, being illustrated to the 2nd.2nd is to change in group GR1 and GR2 in programming action and be applied to choosing
Select the value of the voltage VPGM of wordline WL.
Figure 17 is the sequence diagram of the potential change of the selection wordline WL and bit line BL that indicate this example, and indicates to have selected idol
The case where several memory group MG, namely even-numbered selection grid polar curve SGDe.
As described above, write activity includes programming action and programming verification action.The group is collectively referred to as program cycles.And
And in write activity, the data of the amount of page 1 are written by being repeated a number of times program cycles.
If it is this example, then in programming action, 2 kinds of program voltages VPGM1 and VPGM2 are applied to selection wordline WL,
And there are the relationships of VPGM2 ＞ VPGM1.In the case where having selected even number memory group MG, belong to a group GR1 (BL0,
BL2 the writing speed of memory cell transistor MT) is slow, belongs to the write-in of the memory cell transistor MT of a group GR2 (BL1, BL3)
Speed is fast.Therefore, voltage VPGM1 is used as the program voltage of group GR2, and voltage VPGM2 is used as the programming electricity of group GR1
Pressure.
Specifically, in a period of applying voltage VPGM1, writing prohibition voltage is applied to bit line BL0, BL2 of group GR1
VBL applies write-in voltage (being, for example, 0V, be less than the voltage of VBL) to bit line BL1, BL3 of group GR2.As a result, data quilt
It is programmed into the memory cell transistor MT for being connected to bit line BL1 and BL3.
On the other hand, in a period of applying voltage VPGM2, writing prohibition voltage is applied to bit line BL1, BL3 of group GR2
VBL applies write-in voltage to bit line BL0, BL2 of group GR1.As a result, data, which are programmed into, is connected to bit line BL0 and BL2
Memory cell transistor MT.
According to this method, the memory cell transistor MT slow to writing speed uses high programming voltage, fast to writing speed
Memory cell transistor use low program voltage.Thereby, it is possible to reduce the difference of the writing speed group between GR1 and GR2.This
Outside, the boosting amplitude △ VPGM of program voltage VPGM can also be changed in group GR1 and GR2.Certainly, the group slow in writing speed
In, △ VPGM are set as larger.
2.3 the 3rd
Next, being illustrated to the 3rd.3rd is to reduce the group slow to writing speed when programming verification action
Thus precharge potential makes cell current relatively reduce.Implement with the 1st that is, applying alive method to bit line BL
Figure 14 illustrated in mode is identical.
It is repeated a number of times with by program cycles in the slow memory cell transistor of writing speed according to this method
And the threshold value of unit is got higher, and to become to be not easy flow-through cell electric current, therefore is easy by programming verification.As a result, can
The difference of writing speed between reduction group GR1 and GR2.
The effect of 2.4 present embodiments
According to the present embodiment, even if the situation different between the memory cell transistor for belonging to same one page in writing speed
Under, it can also make them by programming the program cycles number needed for verification as same degree.Therefore, it is possible to cut down program cycles time
Number, speed is bought in so as to improve.In addition, the memory cell transistor that writing speed can be inhibited fast is readily through programming
Verification is carried out interference etc. caused by write activity by the slow memory cell transistor of writing speed for a long time later,
To can also improve write activity reliability.
3. the 3rd embodiment
Next, being illustrated to the semiconductor storage of the 3rd embodiment.Present embodiment is about with described
2 bit lines are arranged as an example in the different plane figure of 1 and the 2nd embodiment on 1 storage column.Hereinafter, only pair with
The different aspect of 1st and the 2nd embodiment illustrates.
3.1 about plane figure
Figure 18 and Figure 19 indicates the plane figure of the selection grid polar curve SGD in the X/Y plane of a certain block BLK.Figure 18 and
Fig. 3 illustrated in 1 embodiment is corresponded to, and the state of bit line BL is also shown.In Figure 19, by the diagram letter in storage unit portion
Change, is especially conceived to the composition of the 1st interconnecting piece and the 2nd interconnecting piece.In addition, in this example, to including 4 in 1 block BLK
The case where selection grid polar curve SGD, illustrates.
As shown, also including that 9 extended in X direction lead in the same manner as composition illustrated in fig. 3 in this example
Electric layer 10.But in this example, wiring layer 10-1~10-7 and 10-0b illustrated in fig. 3 are renamed as into wiring layer respectively
10-1a, 10-2a, 10-3a, 10-0b, 10-1b, 10-2b, 10-3b and 10-0c.Slit is set between each wiring layer 10
SLT2 this aspect is also identical as the 1st embodiment.
Moreover, in being located at 2 wiring layer 10-0a and 10-0c at both ends along the Y direction in block BLK and being located at
Alternatively grid line SGD0 is functioned the wiring layer 10-0b of centre.This 3 wiring layer 10-0 are as shown in Figure 19, such as
It is mutually commonly connected by contact plunger 49 and metallic wiring layer 51 in the 1st interconnecting piece, and then is connected to row decoder
3.In addition, wiring layer 10-1a and 10-2b is commonly connected in the 2nd interconnecting piece by contact plunger 52 and metallic wiring layer 53
It connects, and then is connected to row decoder 3.In turn, wiring layer 10-2a and 10-2b passes through contact plunger 52 and gold in the 2nd interconnecting piece
Belong to wiring layer 53 and commonly connect, and then is connected to row decoder 3.Moreover, wiring layer 10-3a and 10-3b is in the 1st interconnecting piece
In commonly connected by contact plunger 49 and metallic wiring layer 51, and then be connected to row decoder 3.
In addition, as shown in figure 18,2 bit line BL pass through 1 top storage column MP.Wherein, it is connected in 2 bit line BL
The bit line for storing column MP is only any of which item.
That is, 2 bit lines BL0 and BL1 are arranged in the top of storage column MP0~MP3.Bit line BL0 is commonly connected
It is commonly connected to storage column MP0 and MP3 in storage column MP1 and MP2, bit line BL1.In addition, in the upper of storage column MP4~MP7
Side's setting 2 bit lines BL2 and BL3.Bit line BL2 is commonly connected to storage column MP4 and MP5, and bit line BL3, which is commonly connected to, to be deposited
Store up column MP6 and MP7.In turn, 2 bit lines BL4 and BL5 are set in the top of storage column MP8~MP11.Bit line BL4 commonly connects
It is connected to storage column MP9 and MP10, bit line BL5, which is commonly connected to, stores column MP8 and MP11.Moreover, storage column MP12~
2 bit lines BL6 and BL7 are arranged in the top of MP15.It is common that bit line BL6 is commonly connected to storage column MP12 and MP13, bit line BL7
Ground is connected to storage column MP14 and MP15.Therefore, in the case of this example, bit line BL0, BL1, BL4 and BL5 and storage column
MP0~MP3 and MP8~MP11 belongs to a group GR1, and bit line BL2, BL3, BL6 and BL7 and storage column MP4~MP7 and MP12~
MP15 belongs to a group GR2.
Other compositions are as illustrated in the 1st embodiment.
The selection methods of page 3.2
Next, the selection method of page when to the readings of data and when write-in illustrates.
As illustrated in described 3.1, in this example, 2 or 3 wiring layers 10 are commonly connected.Therefore, common
Multiple wiring layers 10 of ground connection are selected simultaneously.Figure 20 and Figure 21 is in X/Y plane corresponding with Figure 18 explained hereinbefore
Selection grid polar curve SGD plane figure, pair corresponding with a selected selection grid polar curve SGD wiring layer 10 mark oblique line and
It indicates.
As shown in figure 20, when selecting any bar in grid line SGD1~SGD3 to be selected, corresponding 2 wirings are selected
Layer 10.In fig. 20, the selected situations of selection grid polar curve SGD1 are shown.In this case, by selecting 2 wiring layer 10-
1a and 10-1b, and be alternatively provided at storage column MP0, MP4, MP8 and MP12 and store column MP2, MP6, MP10 and MP14
8 memory cell transistor MT.That is, being arranged immediately below wiring layer 10-1a and 10-1b with any wordline by belonging to
8 memory cell transistor MT of the corresponding wiring layer 11-1a and 11-1b of WL form page 1.The situation is in selection grid polar curve SGD2
And SGD3 it is selected in the case of it is also identical.
In contrast, selected in selection grid polar curve SGD0, as shown in figure 21, except being located in block BLK
Other than the wiring layer 10-0a and 10-0c at both ends, also simultaneous selection is located at this 3 wirings of the wiring layer 10-0b in the centers block BLK
Layer 10.Selection is located at immediately below wiring layer 10-0a and 2 memory cell transistors in storage column MP4 and MP12 is arranged as a result,
MT, immediately below wiring layer 10-0c and it is arranged in 2 memory cell transistor MT of storage column MP3 and MP11 and positioned at matching
Immediately below line layer 10-0b and 4 memory cell transistor MT in storage column MP1, MP6, MP9 and MP14 are set.Namely
It says, page 1 is formed by this 8 memory cell transistor MT.
The reading method and wiring method of data are as illustrated in the 1st and the 2nd embodiment.
The effect of 3.3 present embodiments
According to the present embodiment, it is functioned by making 2 or more wiring layers 10 be used as 1 selection grid polar curve SGD, energy
Enough increase the size of page 1.In addition, the mode of connection of the selection grid polar curve SGD if it is this example, then having selected multiple wirings
When layer 10, it can make to establish the interference effect (packet between the unit suffered by associated memory cell transistor MT with each wiring layer
Influence containing capacitance or resistance) it is almost equal in wiring interlayer.
Such as in Figure 19, in the case where having selected selection grid polar curve SGD2, wiring layer 10-2a and 10-2b are driven.
The wiring layer 10 adjacent with wiring layer 10-2a is to function as wiring layer SGD1 and sent out as wiring layer SGD3 in Y-direction
Wave the 10-1a and 10-3a of function.Moreover, the wiring adjacent with another wiring layer 10-2b selected simultaneously in the Y direction
Layer 10 is also the wiring layer 10-1b and 10-3b that alternatively grid line SGD1 and SGD3 are functioned.So, 1 selection
Grid line SGD is separated into 2 wirings in storage unit portion, and the combination of adjacent selection grid polar curve is in separation institute in the Y direction
2 wiring closets obtained are common.That is, 2 separating obtained wirings are almost the same by being influenced from adjacent wiring.
Situation all same in the case where having selected any selection grid polar curve SGD.Therefore, it is possible to inhibit between selection grid polar curve SGD
Characteristic deviation, to improve Reliability of Microprocessor.
Figure 22 is the vertical view in the X/Y plane of the selection grid polar curve SGD of the change case of present embodiment.As shown, this
Exemplify the case where quantity of the wiring 10 in 1 block BLK is set as 17.As shown, being for example arranged in order along the Y direction
Wiring layer 10-0a, 10-1a, 10-2a, 10-3a, 10-4a, 10-5a, 10-6a, 10-7a, 10-0b, 10-1b, 10-2b, 10-
3b, 10-4b, 10-5b, 10-6b, 10-7b and 10-0c.Moreover, being located at the wiring layer 10-0a and 10-0c at both ends and being located at
Alternatively grid line SGD0 is functioned the wiring layer 10-b in center.In addition, wiring layer 10-1a and 10-1b alternatively grid
Polar curve SGD1 is functioned, and alternatively grid line SGD2 is functioned by wiring layer 10-2a and 10-2b, same as below.Such one
Come, the item number of wiring layer 10 can suitably increase.
If expressed to generalization, can be explained as Figure 23.Figure 23 is also the plane of selection grid polar curve SGD
Layout.As shown, arranging (2n+1) a wiring layer 10-1~10- (2n+1) along the Y direction.Wherein, n is oneself of 2 or more
So number.Moreover, the 1st layer of wiring layer 10-1, centrally located wiring layer 10- (n+1) and last wiring layer 10- (2n+1) are common
Ground connects.About remaining wiring layer 10, i-th layer commonly connect with (i+n) layer.Wherein, i is the natural number of 2~n.
4. the 4th embodiment
Next, being illustrated to the semiconductor storage of the 4th embodiment.Present embodiment is about alternatively
The mode of connection for the wiring layer 10 that grid line SGD the is functioned example different from the 3rd embodiment.Hereinafter, only pair with
The different aspect of 1st to the 3rd embodiment illustrates.
4.1 about plane figure
Figure 24 is the plane figure of the selection grid polar curve SGD in the X/Y plane of a certain block BLK, and in the 3rd embodiment
Illustrated Figure 19 is corresponded to.Though the diagram of bit line BL is omitted, it is identical as the 3rd embodiment.
As shown, if it is the layout of this example, then 2 wiring layer 10-0a and 10-0c along the Y direction and across 1
A wiring layer 10 and the 1 wiring layer 10-0b adjacent with the wiring layer 10-0a or 10-0c at both ends is drawn out to along the Y direction
1 interconnecting piece and common connection.Moreover, this 3 wiring layers 10-0a, 10-0b and 10-0c are alternatively grid line SGD0 performances
Function.About remaining wiring layer 10, across 1 wiring layer 10, adjacent along the Y direction 2 each other in the common company of interconnecting piece
It connects.That is, as shown in figure 24, wiring layer 10-1a and 10-1b is drawn out to the 2nd interconnecting piece and common connection, and as choosing
Grid line SGD1 is selected to function.In addition, wiring layer 10-2a and 10-2b is drawn out to the 1st interconnecting piece and common connection, and make
It is functioned for selection grid polar curve SGD2.Moreover, wiring layer 10-3a and 10-3b is drawn out to the 2nd interconnecting piece and common connection,
And alternatively grid line SGD3 is functioned.
When reading and when write-in, 2 or 3 wiring layers 10 commonly being connected in the 1st interconnecting piece or the 2nd interconnecting piece
It is driven via storage capacitors simultaneously.
The effect of 4.2 present embodiments
As described above, the mode of connection of the selection grid polar curve SGD illustrated in the 3rd embodiment can also be used as this reality
Apply method as mode.Moreover, according to the present embodiment, because of the case where intersecting there is no multiple wiring layers 10, institute
Multiple wiring layers 10 can commonly be connected in the layer of wiring layer 10.That is, being not necessarily to as Figure 19 by connecing
Plug is touched with metallic wiring layer to utilize other layers.Thereby, it is possible to so that manufacturing method is simplified.
Figure 25 is the plane figure of the selection grid polar curve SGD of the change case of present embodiment, is shown in the same manner as Figure 22 by 1
The quantity of wiring layer 10 in block BLK is set as 17 situations.As shown, 2 wiring layers 10 at both ends along the Y direction
It is drawn out to the 1st interconnecting piece, and alternatively grid line SGD0 with the wiring layer 10 for the 3rd layer from the end number in Y-direction
It functions.Other wiring layers are identical as Figure 24, and across a certain wiring layer 10,2 wiring layers 10 adjacent in the Y direction exist
1st interconnecting piece or the 2nd interconnecting piece are commonly connected.
Figure 26 is showing along the state that Y-direction arranges (2n+1) a wiring layer 10-1~10- (2n+1).Wherein, 2 n
Above natural number.Moreover, the 1st layer of wiring layer 10-1, the 3rd layer of wiring layer 10-3 and last wiring layer 10- (2n+1) are common
Ground connects.About remaining wiring layer 10, kth layer is commonly connect with (k+2) layer.Wherein, k 2,5,6,7,10 ... 10-
(2n-3) and 10- (2n-2).
5. change case etc.
As described above, the semiconductor storage of the embodiment has：1st region (being in figure 3 BLK), including
Be arranged on a semiconductor substrate side and along the 1st direction (being in figure 3 X-direction) in direction in the face as semiconductor substrate simultaneously
That arranges a plurality of the 1st wiring (being in figure 3 SGD), will be detached between adjacent the 1st wiring (being in figure 3 SGD) to row
1 insulating film (being in figure 3 SLT2) and it is arranged in a manner of between adjacent the 1st wiring (in figure 3 for SGD)
1st column (being in figure 3 MP)；And the 2nd, the 3rd region (being in figure 3 SLT1), with the direction in the face of semiconductor substrate and with
1st direction positions the mode that the 1st region (BLK) is clipped in the middle on different the 2nd directions (being in figure 3 Y-direction), and includes
From 2nd insulating film of the setting until the height of the 1st wiring (being in figure 3 SGD) in semiconductor substrate.1st column (MP) includes
Conductive layer, gate insulating film and charge accumulating layer (Fig. 7-10).The 1st wiring in the 1st region (being in figure 3 BLK) is set
(SGD) item number is odd number item (Fig. 3).
According to this composition, the Reliability of Microprocessor of semiconductor storage can be improved.In addition, implementation explained hereinbefore
Mode is only an example, can carry out various change.
For example, in said embodiment, in case of the bit line BL by storing on column MP is 1 or 2 into
It has gone explanation, but may be 3 or 4 or 4 or more.In addition, the item number of selection grid polar curve SGD is also not limited to 9
Or 17 the case where.In turn, the composition of 2 NAND strings of setting is not limited in the 1st embodiment in storage column MP
Illustrated in construction.About this construction, such as it is documented in entitled " semiconductor storage and its manufacturing method
(SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME) " 2015
The U.S. Patent application 14/819,706 that on August is filed an application for 6, the entirety of the patent application be by referring to and quote
In the description of the present application.
In addition, in said embodiment, the plane figure of wordline WL is illustrated using Fig. 4.However, 1 block
The item number of wordline WL included in BLK can be selected suitably, and the connection method of wordline WL also can be selected suitably.In addition, example
Such as, as shown in figure 27, can also be to be constituted made of composition shown in Fig. 4 is arranged 2 sections in the Y direction.If it is this composition,
So slit SLT1 is not only provided at the both ends along the Y direction of 1 block BLK, is additionally arranged at the centers block BLK.Moreover, if
It is the example of Figure 27, then across the side of slit SLT1,4 articles of wordline WL are commonly connected in the 1st interconnecting piece, remaining
3 articles of wordline WL are commonly connected in the 2nd interconnecting piece.On the other hand, across the other side of slit SLT1,4 wordline WL exist
2nd interconnecting piece is commonly connected, and remaining 3 articles of wordline WL are commonly connected in the 1st interconnecting piece.Moreover, across slit
2 groups of wordline WL groups of SLT1 are connected by wiring layer 60 and 61.If it is this composition, then can make from the 1st interconnecting piece side
Article number (being in figure 27 9 articles) of the wordline WL of driving is equal with article number of wordline WL driven from the 2nd interconnecting piece side.
In turn, selection transistor ST2 can also include such as 2 transistor configurations.Figure 28 is comparable to 1 storage column MP
Equivalent circuit diagram.As shown, selection transistor ST2 can also include 2 transistors ST2-1 and ST2-2 of common connection.
Figure 29 is the sectional view of selection transistor ST2.As shown, selection transistor ST2-1 is formed in storage column MP, but select crystal
Pipe 2-2 is formed on p-type well region domain 13.That is, gate insulating film 70 is formed on well area 13, in gate insulating film 70
Upper setting gate electrode 12.In turn, the p-type impurity diffusion layer 71 that source region functions is provided as in well area 13.
According to this composition, it can utilize and current potential is applied to the backgate of transistor ST2-2 such as diffusion layer 71.
In addition, in each embodiment related to the present invention,
(1) for example, memory cell transistor MT can preserve 2 bit datas, and its threshold voltage is followed successively by from low to high
" Er ", " A ", " B ", " C " level are applied to institute in the reading operation of " A " level in the case where " Er " level is deletion state
The voltage of the wordline of selection is, for example, between 0V~0.55V.It's not limited to that, can also be set as 0.1V~0.24V, 0.21V
Any one range in~0.31V, 0.31V~0.4V, 0.4V~0.5V, 0.5V~0.55V.
The voltage for being applied to the wordline selected in the reading operation of " B " level is, for example, between 1.5V~2.3V.Not
It is defined in this, any one model that can also be set as in 1.65V~1.8V, 1.8V~1.95V, 1.95V~2.1V, 2.1V~2.3V
It encloses.
The voltage for being applied to the wordline selected in the reading operation of " C " level is, for example, between 3.0V~4.0V.Not
It is defined in this, can also be set as in 3.0V~3.2V, 3.2V~3.4V, 3.4V~3.5V, 3.5V~3.6V, 3.6V~4.0V
Any one range.
As the time (tR) of reading operation, such as 25 μ s of μ s~38,38 μ s of μ s~70,70 μ of μ s~80 s can also be set as
Between.
(2) write activity includes that programming action is acted with verification.In write activity,
The voltage of selected wordline is, for example, between 13.7V~14.3V when being initially applied to programming action.It does not limit
In this, such as any one range that can also be set as in 13.7V~14.0V, 14.0V~14.6V.
The voltage for being initially applied to selected wordline and write-in idol when odd-numbered wordline is written can also be changed
The voltage for being initially applied to selected wordline when several wordline.
Programming action is being set as ISPP (Incremental Step Pulse Program, incremental step pulse programming)
When mode, as the voltage of boosting, such as 0.5V or so can be enumerated.
As the voltage for being applied to non-selected wordline, such as can also be set as between 6.0V~7.3V.It is not limited to
The situation, such as can also be set as between 7.3V~8.4V, 6.0V or less can also be set as.
It can also be odd-numbered wordline or even-numbered wordline according to non-selected wordline and change and to be applied
Pass through voltage.
As the time (tProg) of write activity, such as 1700 μ s of μ s~1800,1800 μ of μ s~1900 can also be set as
S, between 1900 μ of μ s~2000 s.
(3) in deletion action,
It is initially applied to be formed in semiconductor substrate top and the voltage example of the trap that configures the storage unit above
Such as between 12V~13.6V.Be not limited to the situation, for example, may be 13.6V~14.8V, 14.8V~19.0V,
Between 19.0~19.8V, 19.8V~21V.
As the time (tErase) of deletion action, such as 3000 μ s of μ s~4000,4000 μ of μ s~5000 can also be set as
S, between 4000 μ of μ s~9000 s.
(4) construction of storage unit is
With the charge accumulation across the tunnel insulator film configuration that film thickness is 4~10nm in semiconductor substrate (silicon substrate)
Layer.The charge accumulating layer can be set as the polysilicon that the insulating films such as the SiN that film thickness is 2~3nm or SiON are 3~8nm with film thickness
Lamination constructs.Alternatively, it is also possible to add the metals such as Ru in polysilicon.There is insulating film on charge accumulating layer.The insulation
The film that the upper layer High-k films that film is for example 3~10nm with film thickness with the lower layer's High-k films for being 3~10nm by film thickness clip
Thickness is the silicon oxide film of 4~10nm.About High-k films, HfO etc. can be enumerated.In addition, the film thickness of silicon oxide film can be thicker than High-
The film thickness of k films.It is 30nm~70nm that the work function adjustment for being 3~10nm across film thickness on insulating film forms film thickness with material
Coordination electrode.Herein, work function adjustment is the metal nitride films such as the metal oxide films such as TaO, TaN with material.Coordination electrode can
Use W etc..
In addition, air gap can be formed between storage unit.
In turn, in said embodiment, it as semiconductor storage, is carried out by taking NAND type flash memory as an example
Illustrate, but be not limited to NAND type flash memory, can be applied to other all semiconductor memories, in turn, Neng Gouying
For the various storage devices other than semiconductor memory.
Several embodiments of the present invention are illustrated, but these embodiments are proposed as example
, it is not intended to limit the range of invention.These embodiments can be implemented in a manner of various other, and can not departed from
Various omissions, substitutions and changes are carried out in the range of inventive concept.These embodiments or its variation included in invention range or
In purport, in the range of the invention and its equalization that are also contained in recorded in claims.
[explanation of symbol]
1 NAND type flash memory
2 memory cell arrays
3 row decoders
4 sense amplifiers
10~12,15,18,19 wiring layers
16,17,19 contact plunger
30,32~35,41,43,45,46a~46c insulating layers
31,36,40,42,47 conductive layer
50 NAND strings
Claims (9)
1. a kind of semiconductor storage, it is characterised in that have：
1st region, including setting is square on a semiconductor substrate and along the 1st side in direction in the face as the semiconductor substrate
To arranged side by side the 1st a plurality of wiring, the 1st insulating film that adjacent the 1st wiring closet is detached and with across adjacent
The 1st wiring closet the 1st column that is arranged of mode；And
2nd, the 3rd region, will with the direction in the face of the semiconductor substrate and on the 2nd direction different from the 1st direction
The mode that 1st region is clipped in the middle positions, and includes the height being arranged from the semiconductor substrate to the 1st wiring
The 2nd insulating film；And
1st column includes conductive layer, gate insulating film and charge accumulating layer,
Article number that the 1st wiring in the 1st region is arranged is odd number article.
2. semiconductor storage according to claim 1, it is characterised in that：
2 article of the 1st wiring for being located at the both ends on the 2nd direction in a plurality of 1st wiring is electrically connected to each other.
3. semiconductor storage according to claim 2, it is characterised in that：
Positioned at the both ends 2 article of the 1st wiring so that in being located on the 2nd direction in the 1st wiring of the odd number article
1st wiring of centre is electrically connected to each other.
4. semiconductor storage according to claim 2, it is characterised in that：
Positioned at the both ends 2 article of the 1st wiring so that on the 2nd direction be located at from positioned at one end the 1st with line number
The 1st wiring for the 2nd article is electrically connected to each other.
5. semiconductor storage according to any one of claim 1 to 4, it is characterised in that：
In the 1st column, the 1st adjacent wiring is being used as respectively across the setting of the region of the 1st adjacent wiring
From gate electrode the 1st selection transistor and the 2nd selection transistor,
The 1st wiring described in the 1st selection transistor and the area of charge accumulating layer opposite direction and the 2nd selection are brilliant
1st wiring described in body pipe is different from the area of charge accumulating layer opposite direction.
6. semiconductor storage according to claim 5, it is characterised in that：
1st region is also equipped with：
2nd wiring, below square on the semiconductor substrate and the 1st wiring, arranged side by side along the 1st direction
It is a plurality of；And the 1st insulating film, adjacent the 2nd wiring closet is detached；And
1st column is arranged along the lamination direction of the 1st wiring and the 2nd wiring, and with across adjacent the 2nd wiring
Mode be arranged.
7. semiconductor storage according to claim 6, it is characterised in that：
In the 1st column, the 2nd adjacent wiring is being used as respectively across the setting of the region of the 2nd adjacent wiring
From gate electrode the 1st memory cell transistor and the 2nd memory cell transistor,
The 2nd wiring is deposited with the area of charge accumulating layer opposite direction and the described 2nd described in the 1st memory cell transistor
2nd wiring described in storage unit transistor is different from the area of charge accumulating layer opposite direction.
8. semiconductor storage according to claim 7, it is characterised in that：
2nd region is also equipped with the 2nd column, and the 2nd column is arranged in a manner of across the 1st adjacent wiring closet,
The semiconductor storage is also equipped with：
1st bit line is electrically connected to the 1st column；And
2nd bit line is connected to the 2nd column；And
1st column across 2 article of the 1st adjacent wiring in one article with the 2nd column across it is described adjacent
2 article of the 1st wiring in one article be shared wiring, another is different wirings,
The precharge potential of the 1st bit line and the 2nd bit line when reading operation is different.
9. semiconductor storage according to claim 8, it is characterised in that：
In the 2nd column, the 1st adjacent wiring is being used as respectively across the setting of the region of the 1st adjacent wiring
From gate electrode the 3rd selection transistor and the 4th selection transistor,
1st selection transistor and the 3rd selection transistor common grid electrode,
The 1st wiring described in the 1st selection transistor and the area of charge accumulating layer opposite direction are more than the described 2nd and select
The area of 1st wiring and charge accumulating layer opposite direction described in transistor,
The precharge potential of 1st bit line is less than the precharge potential of the 2nd bit line.
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| JP2017168249A JP2018164070A (en) | 2017-03-27 | 2017-09-01 | Semiconductor memory |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI771943B (en) | 2022-07-21 |
| JP2018164070A (en) | 2018-10-18 |
| TW201836074A (en) | 2018-10-01 |
| TW201929150A (en) | 2019-07-16 |
| TW202147525A (en) | 2021-12-16 |
| TWI644399B (en) | 2018-12-11 |
| TWI724338B (en) | 2021-04-11 |
| CN108666323B (en) | 2022-01-11 |
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