CN106571368B - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN106571368B
CN106571368B CN201610883987.5A CN201610883987A CN106571368B CN 106571368 B CN106571368 B CN 106571368B CN 201610883987 A CN201610883987 A CN 201610883987A CN 106571368 B CN106571368 B CN 106571368B
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semiconductor
pattern
channel structure
insulating layer
thickness
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CN106571368A (en
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李雄燮
崔钟允
辛镇铉
李东植
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

A semiconductor device is provided. The semiconductor device includes: a stack including insulating layers and gate electrodes alternately and repeatedly stacked on a substrate; a lower semiconductor pattern protruding from the substrate into the stack in a vertical direction; an upper portion of the lower semiconductor pattern having a width gradually decreasing in a direction away from the substrate; a channel structure vertically penetrating the stack and connected to the lower semiconductor pattern; and an insulation gap filling pattern inside the channel structure, wherein a bottom surface of the insulation gap filling pattern is lower than a bottom of an upper portion of the lower semiconductor pattern.

Description

Semiconductor device with a plurality of semiconductor chips
This application claims priority from U.S. provisional patent application No. 62/239,061 filed at the U.S. patent and trademark office at 10/8/2015 and korean patent application No. 10-2015-0174317 filed at korean patent office at 12/8/2015, each of which is incorporated herein by reference in its entirety.
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same.
Background
For a conventional two-dimensional semiconductor device or a planar semiconductor device, the degree of integration can be determined by the area occupied by the unit memory cells, which can be related to the level of fine patterning technology used to form these cells. However, the expense associated with processing equipment for fine patterning can limit the integration of two-dimensional or planar semiconductor devices.
To overcome such a limitation, a three-dimensional (3D) semiconductor device including memory cells arranged three-dimensionally has been proposed. However, there may be significant manufacturing obstacles in achieving low cost, high volume production of 3D semiconductor memory devices (particularly in the high volume production of 3D devices that maintain or exceed the operational stability of their 2D counterparts).
Disclosure of Invention
In some embodiments, a method of fabricating a semiconductor device may include forming a channel hole in a vertical stack of alternating insulating and sacrificial layers to form a recess in a substrate. Selective epitaxial growth may be performed to dispose the lower semiconductor pattern in the recess using a material of the substrate as a seed, and the recess may be formed to penetrate an upper surface of the lower semiconductor pattern through the channel hole. The selectively epitaxially growing the lower semiconductor pattern may include selectively epitaxially growing the lower semiconductor pattern in the recess to form an upper surface of the lower semiconductor pattern into an upwardly inclined profile in which a central portion of the upper surface of the lower semiconductor pattern is protruded with respect to an outer peripheral portion of the upper surface of the lower semiconductor pattern. Forming the recess may include forming the recess to include a bottom surface below an outermost portion of an upper surface of the lower semiconductor pattern.
In some embodiments, a semiconductor device may include a stack including insulating layers and gate electrodes alternately and repeatedly stacked on a substrate. The lower semiconductor pattern may protrude from the substrate into the stack in a vertical direction. An upper portion of the lower semiconductor pattern may have a width gradually decreasing in a direction away from the substrate. A channel structure may vertically penetrate the stack and be connected to the lower semiconductor pattern, and an insulation gap fill pattern may be inside the channel structure, wherein a bottom surface of the insulation gap fill pattern is lower than a bottom of an upper portion of the lower semiconductor pattern.
In some embodiments, a semiconductor device may include a stack including insulating layers and gate electrodes alternately and repeatedly stacked on a substrate. The lower semiconductor pattern may protrude from the substrate into the stack in a vertical direction. An upper portion of the lower semiconductor pattern may have a width gradually decreasing in a direction away from the substrate, and a channel structure may penetrate the stack and be connected to the lower semiconductor pattern, wherein a lower portion of the channel structure may penetrate the upper portion of the lower semiconductor pattern.
In some embodiments, a semiconductor device may include a stack including insulating layers and gate electrodes alternately and repeatedly stacked on a substrate. The lower semiconductor pattern may protrude from the substrate into the stack in a vertical direction. A channel structure may be in the stack and connected to the lower semiconductor pattern, and an insulation gap fill pattern may be in the channel structure, wherein the insulation gap fill pattern has a curved bottom surface.
In some embodiments, a method of manufacturing a semiconductor device may include: alternately and repeatedly stacking an insulating layer and a sacrificial layer on a substrate; a channel hole is formed through the insulating layer and the sacrificial layer and exposes the substrate. A selective epitaxial growth process may be performed to grow a lower semiconductor pattern from the top of the substrate exposed through the channel hole, wherein an upper portion of the lower semiconductor pattern is formed to have a width gradually decreasing in a direction away from the substrate. The recess region may be formed to penetrate through an upper portion of the lower semiconductor pattern. A channel structure may be formed to fill the channel hole and the recess region, and the sacrificial layer may be replaced with a gate electrode.
Drawings
Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings represent non-limiting exemplary embodiments as described herein.
Fig. 1 is a circuit diagram schematically illustrating a cell region of a three-dimensional semiconductor memory device according to some embodiments of the inventive concepts.
Fig. 2 is a perspective view illustrating a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.
Fig. 3 is an enlarged sectional view of a portion 'M' of fig. 2.
Fig. 4 to 8, 10, and 12 to 15 are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.
Fig. 9 and 11 are enlarged views showing a portion 'M' of fig. 8 and 10, respectively.
Fig. 16 is a perspective view illustrating a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.
Fig. 17 is a cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concepts.
Fig. 18 is a perspective view illustrating a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.
Fig. 19 is an enlarged sectional view of a portion 'M' of fig. 18.
Fig. 20 is a cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concepts.
Fig. 21 is an enlarged sectional view of a portion 'M' of fig. 20.
Detailed Description
Fig. 1 is a circuit diagram schematically illustrating a cell region of a three-dimensional semiconductor memory device according to some embodiments of the inventive concepts.
Referring to fig. 1, a cell array of a three-dimensional semiconductor memory device may include a common source line CSL, a plurality of BIT lines BIT, and a plurality of cell strings CSTR disposed between the common source line CSL and the BIT lines BIT.
The common source line CSL may be a conductive pattern disposed on the substrate or a doped region formed in the substrate. In some embodiments, the common source line CSL may be a conductive pattern (e.g., a metal line) disposed on and vertically spaced apart from the substrate. The BIT line BIT may be a conductive pattern (e.g., a metal line) disposed on and vertically spaced apart from the substrate. In some embodiments, the BIT line BIT may be disposed to cross the common source line CSL and may be vertically spaced apart from the common source line CSL. The BIT lines BIT may be arranged two-dimensionally, and a plurality of cell strings CSTR may be connected in parallel to each BIT line BIT. The cell strings CSTR may be commonly connected to the common source line CSL. For example, a plurality of cell strings CSTR may be disposed between the BIT line BIT and the common source line CSL. In some embodiments, the plurality of common source lines CSL may be two-dimensionally disposed on the substrate. In some embodiments, the common-source lines CSL may be applied with the same voltage, but in some embodiments, the common-source lines CSL may be separated from each other and thus may be independently biased.
Each cell string CSTR may include a ground selection transistor GST coupled to the common source line CSL, a string selection transistor SST coupled to the BIT line BIT, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Also, the selection transistor GST, the string selection transistor SST, and the memory cell transistor MCT may be connected in series.
The common source line CSL may be commonly connected to a source region of the ground selection transistor GST. In addition, at least one lower selection line LSL, a plurality of word lines WL0-WL3, and a plurality of upper selection lines USL may be disposed between the common source line CSL and the BIT line BIT to serve as gate electrodes of the ground selection transistor GST, the memory cell transistor MCT, and the string selection transistor SST, respectively. In addition, each memory cell transistor MCT may include a data storage element.
Fig. 2 is a perspective view illustrating a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Fig. 3 is an enlarged sectional view of a portion 'M' of fig. 2.
Referring to fig. 2 and 3, a substrate 100 may be provided. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The substrate 100 may include a common source region 120 doped with impurities. Each common source region 120 may be a line structure extending in a first direction D1 parallel to the top surface of the substrate 100. The common source regions 120 may be disposed to be spaced apart from each other in a second direction D2 crossing the first direction D1.
The insulating layer 110 and the gate electrode 155 may be alternately and repeatedly stacked on the substrate 100 to form a stack SS. In certain embodiments, multiple stacks SS may be provided on the substrate 100, but for the sake of brevity, the following description will refer to an example in which only a single stack SS is provided. When viewed in plan, stack SS may be a linear structure extending in a first direction D1. The common source regions 120 may be disposed at both sides of the stack SS. The lower insulating layer 105 may be disposed between the substrate 100 and the stack SS. The lower insulating layer 105 may include a silicon nitride layer or a high-k dielectric layer (e.g., aluminum oxide or hafnium oxide). The thickness of the lower insulating layer 105 may be smaller than that of the insulating layer 110.
The gate electrodes 155 may be stacked in a third direction D3 perpendicular to both the first direction D1 and the second direction D2. The gate electrodes 155 may be vertically separated from each other by the insulating layer 110 disposed between the gate electrodes 155. In some embodiments, the lowermost gate electrode 155G of the gate electrodes 155 may be used as a gate electrode (i.e., a lower selection line) of the ground selection transistor GST described with reference to fig. 1. The uppermost gate electrode 155S of the gate electrodes 155 may be used as a gate electrode (i.e., an upper selection line) of the string selection transistor SST described with reference to fig. 1. The gate electrode 155 positioned between the lowermost gate electrode 155G and the uppermost gate electrode 155S may be used as a gate electrode (i.e., a word line) of the memory cell transistor MCT described with reference to fig. 3. For example, the gate electrode 155 may be formed of or include at least one of doped silicon, metal (e.g., tungsten), metal nitride, and metal silicide. The insulating layer 110 may be formed of or include silicon oxide.
The substrate 100 may include a lower semiconductor pattern LSP at a lower portion of the substrate 100. The lower semiconductor pattern LSP may protrude upward from the top surface of the substrate 100 and may pass through the lower insulating layer 105 and the lowermost gate electrode 155G. The lower semiconductor pattern LSP may be disposed to penetrate a portion of the insulating layer 110 on the lowermost gate electrode 155G. In other words, the lower semiconductor pattern LSP may have a top surface positioned between the bottom surface and the top surface of the insulating layer 110.
The lower semiconductor pattern LSP may be formed of or include a semiconductor material having the same conductivity type as that of the substrate 100. In some embodiments, the lower semiconductor pattern LSP may be an epitaxial pattern epitaxially grown using the substrate 100 as a seed layer. In this case, the lower semiconductor pattern LSP may have a single crystal or polycrystalline structure. The lower semiconductor pattern LSP may be formed of or include silicon.
Referring back to fig. 3, the lower semiconductor pattern LSP may be formed through a Selective Epitaxial Growth (SEG) process, and thus, a top surface of the lower semiconductor pattern LSP may have a non-zero curvature (non-planar). For example, each lower semiconductor pattern LSP may have a convex top surface protruding in an upward direction. As an example, each lower semiconductor pattern LSP may include an upper portion UP having a width (or an inclined profile) gradually decreasing in a direction away from the substrate 100 (i.e., in the third direction D3) and a lower portion LP under the upper portion UP. The width of the lower part LP may be substantially uniform in the third direction D3. In some embodiments, the lower semiconductor pattern LSP may have a substantially flat top surface. In other words, the upper portion UP of the lower semiconductor pattern LSP may not have a tapered profile.
In each lower semiconductor pattern LSP, the first recessed area RS1 may be formed to penetrate through the upper portion UP. The first recessed area RS1 may have a bottom RS1b positioned at a lower level than the bottom level UPB of the upper UP.
Referring back to fig. 2, the gate insulating layer GI may be disposed between the lower semiconductor pattern LSP and the lowermost gate electrode 155G adjacent to the lower semiconductor pattern LSP. As an example, the gate insulating layer GI may be formed of or include silicon oxide.
A plurality of channel structures CS may be disposed through the stack SS and may be electrically connected to the substrate 100. The channel structures CS may be arranged along the first direction D1 when viewed in a plan view. In some embodiments, the channel structure CS may be provided to have a zigzag arrangement in the first direction D1. The inner space of each channel structure CS may be filled with the insulation gap fill pattern 150.
A vertical insulator 145 may be disposed between the stack SS and each channel structure CS. The vertical insulator 145 may extend in the third direction D3. The vertical insulator 145 may be a tubular structure or a hollow powder structure with top and bottom openings.
Referring back to fig. 3, the vertical insulator 145 may include a blocking insulating layer BL, a charge storage layer CL, and a tunneling insulating layer TL, which are sequentially stacked. The blocking insulating layer BL may contact the sidewall of the gate electrode 155 and contact the upper portion UP of the lower semiconductor pattern LSP. The tunneling insulating layer TL may be in contact with the channel structure CS. The charge storage layer CL may be disposed between the blocking insulating layer BL and the tunneling insulating layer TL.
The charge storage layer CL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer (trap layer). The tunneling insulation layer TL may include a material having a band gap larger than that of the charge storage layer CL. For example, the tunneling insulating layer TL may be a silicon oxide layer. The blocking insulating layer BL may include at least one of materials having a band gap greater than that of the charge storage layer CL. As an example, the blocking insulating layer BL may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
The vertical insulator 145 may include: a horizontal extension part HE disposed between the lower semiconductor pattern LSP and the first semiconductor pillar SP1 (further described); the vertical extension VE extends from the horizontal extension HE in the third direction D3. The horizontal extension portion HE may be disposed to directly cover the top surface of the lower semiconductor pattern LSP. Since the upper portion UP of the lower semiconductor pattern LSP has a convex structure and the horizontal extension portion HE is formed to cover the top surface of the lower semiconductor pattern LSP, the horizontal extension portion HE may have an inclined profile.
Each channel structure CS may include a first semiconductor pillar SP1 and a second semiconductor pillar SP 2. The first semiconductor pillar SP1 may be disposed to surround an outer sidewall of the second semiconductor pillar SP 2. The first semiconductor pillars SP1 may also be disposed to cover inner sidewalls of the stack SS. The first semiconductor pillar SP1 may be a tubular structure or a hollow powder structure having top and bottom openings. The first semiconductor pillar SP1 may be spaced apart from the substrate 100. The second semiconductor pillar SP2 may be a tubular structure having a closed bottom or a hollow powder structure.
The second semiconductor pillar SP2 may include a lower portion passing through the bottom of the first semiconductor pillar SP1 and inserted into the first recessed region RS 1. In other words, the bottom surface of the second semiconductor pillar SP2 may be positioned at a lower level than the bottom surface of the first semiconductor pillar SP 1. Further, a lower portion of the second semiconductor pillar SP2 may sequentially pass through the tunneling insulation layer TL, the charge storage layer CL, and the blocking insulation layer BL and may contact the lower semiconductor LSP. Accordingly, the second semiconductor pillars SP2 may allow the first semiconductor pillars SP1 to be electrically connected to the substrate 100 or the lower semiconductor pattern LSP. The second semiconductor pillars SP2 may be provided to allow the bottom surfaces 150b of the insulation interstitial patterns 150 therein to be positioned at a lower level than the bottom level UPB of the upper portion UP of the lower semiconductor pattern LSP.
An upper portion of each channel structure CS may have a first thickness T1 when measured in a direction parallel to the top surface of the substrate 100. In other words, the sum of the thicknesses of the first and second semiconductor pillars SP1 and SP2 may be the first thickness T1. The lower portion of each channel structure CS may have a second thickness T2 when measured in a direction parallel to the top surface of the substrate 100. In other words, the thickness of the second semiconductor pillars SP2 in contact with the vertical insulator 145 may be the second thickness T2. Here, the second thickness T2 may be less than the first thickness T1; for example, the second thickness T2 may be about 10% to 40% of the first thickness T1.
In the case where the second semiconductor pillars SP2, which are in contact with the vertical insulator 145, have a relatively small thickness (e.g., the second thickness T2), the grain size of the second semiconductor pillars SP2 may be reduced. The reduction in the grain size of the second semiconductor pillars SP2 may enable shortening of the path length of electrons and reduction in the density of trap sites (trap sites). As a result, it is possible to increase electron mobility on the channel region and improve electrical characteristics of the semiconductor device.
As an example, the first and second semiconductor pillars SP1 and SP2 may be in an undoped state or may be doped to have the same conductivity type as the substrate 100. The first semiconductor pillar SP1 and the second semiconductor pillar SP2 may have a polycrystalline structure or a single crystal structure. As an example, the first semiconductor pillar SP1 and the second semiconductor pillar SP2 may be formed of or include silicon. The insulation gap fill pattern 150 may be formed of or include silicon oxide.
Conductive pads 137 may be disposed through the stack SS and may be connected to the channel structures CS, respectively. A top surface of conductive pad 137 may be substantially coplanar with a top surface of stack SS, and a bottom surface of conductive pad 137 may be in contact with channel structure CS. The vertical insulating member 145 may extend in the third direction D3 and may be disposed between the conductive pad 137 and the insulating layer 110 adjacent thereto. Conductive pad 137 may include a conductive material (e.g., at least one of a doped semiconductor and a metallic material).
BIT lines BIT may be disposed on stack SS to intersect stack SS. The BIT line BIT may be coupled to the conductive pad 137 through a BIT line plug BPLG.
Fig. 4 to 8, 10, and 12 to 15 are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Fig. 9 and 11 are enlarged views showing a portion 'M' of fig. 8 and 10, respectively.
Referring to fig. 4, a sacrificial layer 151 and an insulating layer 110 may be alternately and repeatedly deposited on a substrate 100 to form a layered structure TS. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate.
The sacrificial layers 151 may be formed to have substantially the same thickness. However, in some embodiments, the lowermost sacrificial layer and the uppermost sacrificial layer among the sacrificial layers 151 may be formed to have a thickness greater than that of the other sacrificial layers 151 disposed therebetween. The insulating layers 110 may be formed to have substantially the same thickness, but in some embodiments, some of the insulating layers 110 may be formed to have a thickness different from the thickness of other insulating layers 110.
The sacrificial layer 151 may be formed of, for example, a silicon nitride layer, a silicon oxynitride layer, or a silicon layer. The insulating layer 110 may be formed of a silicon oxide layer. For example, the sacrificial layer 151 and the insulating layer 110 may be deposited using a thermal chemical vapor deposition process, a plasma-enhanced chemical vapor deposition (PE-CVD) process, a physical CVD process, or an Atomic Layer Deposition (ALD) process.
Further, a lower insulating layer 105 may be formed between the substrate 100 and the layered structure TS. The lower insulating layer 105 may be formed of a material having high etch selectivity with respect to the sacrificial layer 151 and the insulating layer 110. The lower insulating layer 105 may include a silicon nitride layer or a high-k dielectric layer (e.g., aluminum oxide or hafnium oxide). The lower insulating layer 105 may be formed to have a thickness smaller than those of the sacrificial layer 151 and the insulating layer 110.
Referring to fig. 5, the channel hole CH may be formed to penetrate the layered structure TS and thus expose the substrate 100. The channel hole CH may be formed to have the same arrangement as the channel structure CS described with reference to fig. 2.
The forming of the channel hole CH may include forming a first mask pattern on the layered structure TS to have an opening defining a position and a shape of the channel hole CH and etching the layered structure TS using the first mask pattern as an etching mask. The etching process may be performed in an over-etching manner to etch the top surface of the substrate 100, and thus, the top surface of the substrate 100 may be partially recessed. Then, the first mask pattern may be removed.
Referring to fig. 6, lower semiconductor patterns LSP may be formed to fill lower regions of the channel holes CH, respectively. The lower semiconductor pattern LSP may be formed through a Selective Epitaxial Growth (SEG) process in which the substrate 100 exposed through the channel hole CH is used as a seed layer. In this case, the lower semiconductor pattern LSP and the substrate 100 may be continuously connected to each other, thereby forming a single semiconductor structure.
Each of the lower semiconductor patterns LSP may be a pillar-shaped structure that protrudes upward from the top surface of the substrate 100 and fills a corresponding one of lower regions of the channel holes CH. The lower semiconductor pattern LSP may be formed to cover sidewalls of the lowermost sacrificial layer 151 among the sacrificial layers 151. The lower semiconductor pattern LSP may be formed to have a top surface positioned between the bottom surface and the top surface of the lowermost insulating layer 110 among the insulating layers 110.
As a result of the SEG process, each lower semiconductor pattern LSP may be formed to have a top surface that is convex upward. For example, the lower semiconductor pattern LSP may have an upper portion having a gradually decreasing width in the third direction D3.
The lower semiconductor pattern LSP may be formed of or include a semiconductor material having the same conductivity type as that of the substrate 100. The lower semiconductor pattern LSP may be in-situ doped with impurities during the selective epitaxial growth process. Alternatively, the lower semiconductor pattern LSP may be doped by an ion implantation process after the selective epitaxial growth process. The lower semiconductor pattern LSP may have a single crystal or polycrystalline structure; for example, the lower semiconductor pattern LSP may be formed of a single crystal silicon layer or a polycrystalline silicon layer.
Referring to fig. 7, a vertical insulating layer 140 and a first semiconductor layer SL1 may be sequentially formed on the inner sidewall of the channel hole CH. The vertical insulating layer 140 and the first semiconductor layer SL1 may be formed to partially fill each channel hole CH. That is, the vertical insulating layer 140 and the first semiconductor layer SL1 may not fill the entire area of the channel hole CH. The vertical insulating layer 140 may be formed to cover a top surface of the lower semiconductor pattern LSP exposed through the channel hole CH. Accordingly, the vertical insulating layer 140 and the first semiconductor layer SL1 may have a lower portion extending parallel to the top surface of the lower semiconductor pattern LSP and having an inclined profile.
Specifically, the formation of the vertical insulating layer 140 may include sequentially forming a blocking insulating layer BL, a charge storage layer CL, and a tunneling insulating layer TL on inner sidewalls of each channel hole CH (e.g., see fig. 9). The blocking insulating layer BL may be formed of or include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The charge storage layer CL may be formed of or include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer. The tunneling insulating layer TL may be formed of or include a silicon oxide layer. For example, each of the blocking insulating layer BL, the charge storage layer CL, and the tunneling insulating layer TL may be deposited using a plasma enhanced chemical vapor deposition (PE-CVD) process, a physical CVD process, or an Atomic Layer Deposition (ALD) process.
The first semiconductor layer SL1 may have a polycrystalline structure or a single crystal structure. As an example, the first semiconductor layer SL1 may be formed of a polycrystalline silicon layer, a single crystal silicon layer, or an amorphous silicon layer. The first semiconductor layer SL1 may be formed using an ALD or CVD process.
Referring to fig. 8 and 9, the first semiconductor layer SL1 and the vertical insulating layer 140 may be anisotropically etched, and as a result, the first semiconductor pillars SP1 and the vertical insulators 145 may be formed in each channel hole CH. Each of the first semiconductor pillar SP1 and the vertical insulator 145 may be a tubular structure or a hollow powder structure having top and bottom openings. Accordingly, the first semiconductor pillars SP1 and the vertical insulating members 145 may be formed to expose a portion of the lower semiconductor pattern LSP.
An anisotropic etching process may be performed in an over-etching manner to etch the first semiconductor layer SL1 and the vertical insulating layer 140, and thus, first recessed regions RS1 may be formed in the lower semiconductor patterns LSP, respectively.
Referring back to fig. 9, the first recessed area RS1 may be formed as follows: a bottom RS1b of the first recessed area RS1 is lower than a bottom level UPB of the upper portion UP of the lower semiconductor pattern LSP. As understood by the entity of the present invention, at a position where the convex portion (or the inclined surface) of the upper portion UP starts, if the anisotropic etching process is not performed in an over-etching manner, it is difficult to expose the lower semiconductor pattern LSP in the process of etching the first semiconductor layer SL1 and/or the vertical insulating layer 140. Otherwise, the lower semiconductor pattern LSP is electrically separated from the channel structure CS so that the semiconductor device cannot be normally operated. As understood by the present entity, in contrast, according to some embodiments of the inventive concept, process conditions capable of achieving higher anisotropy and higher etch rate may be utilized for an anisotropic etch process; that is, the anisotropic etching process may be performed under an enhanced over-etching condition. Accordingly, the first recessed region RS1 may be formed to completely penetrate the upper portion UP of the lower semiconductor pattern LSP, and as a result, the lower semiconductor pattern LSP may be reliably exposed.
Referring back to fig. 8 and 9, a second semiconductor layer SL2 may be formed in the channel hole CH. The second semiconductor layer SL2 may be too thin to fill the entire inner space of the channel hole CH and may be conformally formed in the channel hole CH. For example, the second semiconductor layer SL2 may be formed to have a third thickness T3. Here, the sum of the thicknesses of the first semiconductor pillar SP1 and the second semiconductor layer SL2 may be the fourth thickness T4.
The second semiconductor layer SL2 may be formed to electrically connect the substrate 100 to the first semiconductor column SP 1. The second semiconductor layer SL2 may have a polycrystalline structure or a single crystal structure. As an example, the second semiconductor layer SL2 may be formed of a polycrystalline silicon layer, a single crystal silicon layer, or an amorphous silicon layer. The second semiconductor layer SL2 may be formed by an ALD or CVD process.
Referring to fig. 10 and 11, a cleaning process may be performed on the second semiconductor layer SL2, and then, an insulating interstitial layer may be formed to completely fill the channel hole CH. The insulating interstitial layer may be a silicon oxide layer formed using spin-on-glass (SOG) techniques. Then, the second semiconductor layer SL2 and the upper portion of the insulating gap fill layer may be recessed to form the second semiconductor pillars SP2 and the insulating gap fill patterns 150 in each channel hole CH. In some embodiments, the first semiconductor pillars SP1 may also be recessed during the recess of the second semiconductor layer SL 2. The first semiconductor pillar SP1 and the second semiconductor pillar SP2 may constitute a channel structure CS.
In the channel hole CH, the second semiconductor pillar SP2 may have a tubular or hollow cylindrical structure having one end closed; for example, the second semiconductor pillars SP2 may be cup-like in shape. The insulation gap fill pattern 150 may be a bar-shaped structure filling the channel hole CH provided with the second semiconductor pillars SP 2.
In addition, conductive pads 137 may be formed on and connected to the channel structures CS, respectively. The conductive pad 137 may be formed by filling the trench structure CS and the recessed region of the insulation gap fill pattern 150 with a conductive material. As an example, the conductive pad 137 may be formed of a silicon layer doped to have the same conductivity type as that of the substrate 100. A planarization process may be performed on the top of the layered structure TS.
Referring back to fig. 11, a cleaning process may be performed on the second semiconductor layer SL2 to reduce the thickness of the second semiconductor layer SL2 (e.g., the thickness T3). For example, as a result of the processes described with reference to fig. 10 and 11, the second semiconductor pillars SP2 may have a second thickness T2 less than the third thickness T3.
In some embodiments, the cleaning process may be a standard clean 1(SC) process. For example, the cleaning process may be performed using a cleaning solution in which ammonium hydroxide and hydrogen peroxide are mixed. In this case, the exposed portion of the second semiconductor layer SL2 may be oxidized during the cleaning process, and then, the oxidized portion of the second semiconductor SL2 may be removed. That is, the thickness of the second semiconductor layer SL2 may be reduced by a cleaning process.
According to some embodiments of the inventive concept, the first recessed region RS1 may be deeply formed through an over-etching process, which may be capable of completely exposing a portion of the second semiconductor layer SL2 in contact with the vertical insulating member 145. Therefore, when the cleaning process is performed, the portion of the second semiconductor layer SL2 in contact with the vertical insulating member 145 may be more easily exposed to the cleaning solution. That is, as a result of the cleaning process, a portion of the second semiconductor layer SL2 in contact with the vertical insulator 145 may have a reduced thickness (e.g., a second thickness T2).
The sum of the thicknesses of the first and second semiconductor pillars SP1 and SP2 may be the first thickness T1. Here, the second semiconductor pillar SP2 may be formed to have a second thickness T2 that is much smaller than the thickness of the first semiconductor pillar SP 1; for example, the second thickness T2 may be about 10% to 40% of the first thickness T1.
The insulation gap fill pattern 150 may have a bottom surface 150b adjacent to the bottom RS1b of the first recessed region RS 1. For example, the bottom surface 150b of the insulation gap fill pattern 150 may be lower than the bottom horizontal plane UPB of the upper portion UP of the lower semiconductor pattern LSP.
Referring to fig. 12, the layer structure TS may be patterned to form trenches TR, each of which is disposed between the channel structures CS to expose a portion of the substrate 100. For example, the forming of the trench TR may include forming a second mask pattern (not shown) on the layered structure TS to define the position and shape of the trench TR, and then etching the layered structure TS using the second mask pattern as an etching mask. The process of etching the layered structure TS may be performed in an over-etching manner. For example, a process of etching the layered structure TS may be performed to partially recess the top surface of the substrate 100. Then, the second mask pattern may be removed.
The trench TR may be formed to expose sidewalls of the sacrificial layer 151 and the insulating layer 110. In addition, the trench TR may be formed to expose a sidewall of the lower insulating layer 105.
As a result of the formation of the trenches TR, the layer structure TS may be divided into a plurality of linear portions, each extending parallel to the trenches TR. In some embodiments, a plurality of channel structures CS may be provided to extend through each linear portion of the layered structure TS.
Referring to fig. 13, the sacrificial layer 151 exposed through the trench TR may be selectively removed to form a second recessed region RS 2. Since the sacrificial layer 151 is removed, the second recessed area RS2 may be an empty space. In the case where the sacrificial layer 151 includes a silicon nitride layer or a silicon oxynitride layer, the process of removing the sacrificial layer 151 may be performed using an etching solution including phosphoric acid. The second recessed area RS2 may be formed to partially expose the vertical insulating member 145. Further, the second recessed area RS2 may be formed to partially expose a side surface of the lower semiconductor pattern LSP.
The gate insulating layer GI may be formed to cover the exposed side surface of the lower semiconductor pattern LSP. For example, an oxidation process may be performed to form an oxide layer (i.e., the gate insulating layer GI) on the exposed side surface of the lower semiconductor pattern LSP.
Referring to fig. 14, the conductive layer 153 may be conformally formed to fill the second recessed region RS 2. The conductive layer 153 may be formed of or include at least one of a doped polysilicon layer, a metal layer (e.g., tungsten), or a metal nitride layer. In some embodiments, the conductive layer 153 may be formed as follows: the entire region of each trench TR is not filled with the conductive layer 153.
Referring to fig. 15, an etching process may be performed to remove portions of the conductive layer 153 from the trenches TR and to leave other portions (i.e., limited portions) of the conductive layer 153 in the second recessed regions RS 2. The remaining portion of the conductive layer 153 in the second recessed region RS2 may be used as the gate electrode 155. The gate electrode 155 and the insulating layer 110 may be stacked on the substrate 100, thereby forming a stack SS.
After the gate electrode 155 is formed, the common source region 120 may be formed on the substrate 100. The common source region 120 may be formed by an ion implantation process and the common source region 120 may be formed in the substrate 100 exposed through the trench TR. The common source region 120 combined with the substrate 100 may provide a pn junction.
Referring back to fig. 2, BIT line plugs BPLG may be formed on the conductive pads 137 and may be connected to the conductive pads 137, respectively, and BIT lines BIT may be formed on the BIT line plugs BPLG and may be connected to the BIT line plugs BPLG. The BIT line BIT may be electrically connected to the channel structure CS through the BIT line plug BPLG.
Fig. 16 is a perspective view illustrating a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. In the following description of the present embodiment, elements described hereinbefore with reference to fig. 2 and 3 may be denoted by similar or identical reference numerals without repeating their overlapping description.
Referring to fig. 16, a horizontal insulator 185 may be disposed between the gate electrode 155 and the vertical insulator 145. Each horizontal insulating member 185 may horizontally extend to have a portion disposed between the gate electrode 155 and the insulating layer 110. Accordingly, each horizontal insulator 185 may have a 'U' -shaped cross-section.
As described with reference to fig. 3, the vertical insulator 145 may include a charge storage layer CL and a tunneling insulation layer TL. In some embodiments, unlike the description with reference to fig. 3, the vertical insulating member 145 may be formed not to include the blocking insulating layer BL. In this case, the horizontal insulating member 185 may include a barrier insulating layer.
As another example, the vertical insulator 145 may include a tunneling insulation layer TL, as described with reference to fig. 3. However, unlike the description with reference to fig. 3, the vertical insulating member 145 may be formed not to include the charge storage layer CL and the blocking insulating layer BL. In this case, the horizontal insulating member 185 may include a blocking insulating layer and a charge storage layer.
Fig. 17 is a cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concepts. In the following description of the present embodiment, elements or steps described hereinbefore with reference to fig. 4 to 15 may be denoted by similar or identical reference numerals without repeating their overlapping descriptions.
Referring to fig. 17, a horizontal insulating layer 180 may be conformally formed on the structure of fig. 13. The horizontal insulating layer 180 may be formed to conformally cover the inner surface of the second recessed region RS 2. For example, the horizontal insulating layer 180 may be deposited using a plasma enhanced chemical vapor deposition (PE-CVD) process, a physical CVD process, or an Atomic Layer Deposition (ALD) process. Then, the conductive layer 153 may be conformally formed to fill the remaining space of the second recessed region RS 2.
Referring back to fig. 16, an etching process may be performed to remove a portion of the conductive layer 153 and the horizontal insulating layer 180 from the trench TR while the other portion of the conductive layer 153 remains in the second recessed region RS2 together with the horizontal insulating layer 180. The conductive layer 153 and the portion of the horizontal insulating layer 180 remaining in the second recessed region RS2 may be used as the horizontal insulator 185 and the gate electrode 155.
After the gate electrode 155 is formed, the common source region 120 may be formed in the substrate 100. Next, BIT line plugs BPLG may be formed on and connected to the conductive pads 137, and BIT lines BIT may be formed on and connected to the BIT line plugs BPLG, respectively.
Fig. 18 is a perspective view illustrating a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Fig. 19 is an enlarged sectional view of a portion 'M' of fig. 18. In the following description of the present embodiment, elements described hereinbefore with reference to fig. 2 and 3 may be denoted by similar or identical reference numerals without repeating their overlapping description.
Referring to fig. 18 and 19, in each lower semiconductor pattern LSP, the first recessed area RS1 may be formed to penetrate through the upper portion UP of the lower semiconductor pattern LSP. The first recessed area RS1 may be formed to have a non-planar bottom. The second semiconductor pillar SP2 may include a lower portion penetrating into the first recessed region RS1 through the bottom of the first semiconductor pillar SP 1. Accordingly, the second semiconductor pillars SP2 may allow the first semiconductor pillars SP1 to be electrically connected to the substrate 100 or the lower semiconductor pattern LSP.
The insulation gap fill pattern 150 in the second semiconductor pillars SP2 may have a curved shape in the first recessed region RS 1. For example, the bottom surface 150b of the insulation gap fill pattern 150 may have a curved shape (regardless of the inner corners). A lowermost portion of the bottom surface 150b of the insulation gap fill pattern 150 may be lower than the bottom horizontal plane UPB of the upper portion UP of the lower semiconductor pattern LSP.
The lower portion 150LP of the insulation gap filling pattern 150 may have a vertically varying width. For example, the width of the lower portion 150LP may be greatest at its top level (e.g., the first width W1) and may gradually decrease as the distance to the substrate 100 decreases. For example, at a level below the top level, the lower portion 150LP may have a second width W2 that is less than the first width W1.
In the first recess region RS1, the second semiconductor pillars SP2 may have a vertically varying width. For example, the second semiconductor pillar SP2 may have a fifth thickness T5 at a region adjacent to a sidewall of the insulation gap fill pattern 150 in the first recess region RS 1. At a region under the lower portion 150LP of the insulation gap fill pattern 150, the second semiconductor pillars SP2 may have a sixth thickness T6 greater than the fifth thickness T5. The fifth thickness T5 may be less than the second thickness T2. Since the second semiconductor pillars SP2 have a relatively small thickness (e.g., the sixth thickness T6), the carrier mobility in the second semiconductor pillars SP2 may be increased.
In some embodiments, the lower portion 150LP of the insulation gap filling pattern 150 may not have a curved side surface. In other words, as shown in fig. 3, the lower portion 150LP of the insulation gap fill pattern 150 may have a flat side surface. However, the bottom surface 150b of the insulation gap-fill pattern 150 and a portion adjacent to the bottom surface 150b may have a curved shape. Further, the fifth thickness T5 may be substantially equal to the second thickness T2.
Fig. 20 is a cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concepts. Fig. 21 is an enlarged sectional view of a portion 'M' of fig. 20. In the following description of the present embodiment, elements or steps described hereinbefore with reference to fig. 4 to 15 may be denoted by similar or identical reference numerals without repeating their overlapping descriptions.
Referring to fig. 20 and 21, a cleaning process may be performed on the structure of fig. 8, and an insulating interstitial layer may be formed. As a result, the second semiconductor pillars SP2 and the insulation gap fill pattern 150 may be formed in each channel hole CH.
Referring back to fig. 21, a cleaning process may be performed on the second semiconductor layer SL2 of fig. 9. The second semiconductor pillars SP2 may have a vertically varying width after the cleaning process as a result of the over-etching process or due to the presence of the first recessed region RS1 having a large depth. For example, the second semiconductor layer SL2 in the first recessed region RS1 may be partially removed to have a curved surface due to the eddy current of the cleaning solution supplied into the channel hole CH. As a result, the second semiconductor pillars SP2 may have several different thicknesses (e.g., the second thickness T2, the fifth thickness T5, and the sixth thickness T6) in a direction toward the substrate 100.
In some embodiments, the second semiconductor layer SL2 may be partially removed to have a curved surface only in a region adjacent to the bottom of the first recessed region RS 1. In this case, the second thickness T2 and the fifth thickness T5 of the second semiconductor pillar SP2 may be substantially equal to each other.
The insulation gap-fill pattern 150 in the first recess region RS1 may be formed to have a curved shape due to the curved surface of the second semiconductor pillar SP 2. For example, the lower portion 150LP of the insulation gap filling pattern 150 may have at least two different widths in a direction toward the substrate 100; for example, the lower portion 150LP may have a first width W1 and a second width W2 that is less than the first width W1.
The subsequent processes may be performed in substantially the same manner as the processes described with reference to fig. 12 to 15.
According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device may include etching a lower semiconductor pattern exposed through a channel hole in an over-etching manner to form a deep recess region in an upper portion of the lower semiconductor pattern. This may enable allowing the channel structure formed in the channel hole to be stably connected to the lower semiconductor pattern. That is, the channel structure can be prevented from being electrically separated from the substrate. Further, a portion of the channel structure adjacent to the recessed region may be formed to have a relatively thin thickness, which may enable the portion of the channel structure to have a reduced grain size. Therefore, it is possible to increase the mobility of electrons flowing through the channel structure and thus improve the electrical characteristics of the semiconductor device.
While example embodiments of the inventive concept have been particularly shown and described, it will be understood by those of ordinary skill in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (20)

1. A semiconductor device, the semiconductor device comprising:
a stack including insulating layers and gate electrodes alternately and repeatedly stacked on a substrate;
a lower semiconductor pattern protruding from the substrate into the stack in a vertical direction;
an upper portion of the lower semiconductor pattern having a width gradually decreasing in a direction away from the substrate;
a channel structure vertically penetrating the stack and connected to the lower semiconductor pattern; and
an insulation gap filling pattern inside the channel structure, wherein a bottom surface of the insulation gap filling pattern extends into the lower semiconductor pattern beyond an upper portion of the lower semiconductor pattern to be lower than a bottom level of the upper portion of the lower semiconductor pattern,
wherein the channel structure includes a second semiconductor pillar and a first semiconductor pillar surrounding the second semiconductor pillar, a bottom surface of the second semiconductor pillar is lower than a bottom surface of the first semiconductor pillar, and the second semiconductor pillar contacts the lower semiconductor pattern,
wherein the second semiconductor pillar has a second thickness that is less than a thickness of the first semiconductor pillar such that a grain size of the second semiconductor pillar is reduced.
2. The semiconductor device of claim 1, wherein the lower semiconductor pattern includes a recessed region penetrating an upper portion of the lower semiconductor pattern, and
the lower portion of the second semiconductor pillar is located in the recess region of the lower semiconductor pattern.
3. The semiconductor device according to claim 2, wherein an upper portion of the channel structure includes the first semiconductor pillar and the second semiconductor pillar and has a first thickness, and
the lower portion of the channel structure includes a second semiconductor pillar and has a second thickness less than the first thickness.
4. The semiconductor device according to claim 3, wherein the second thickness is 10% to 40% of the first thickness.
5. The semiconductor device of claim 1, wherein a lowermost gate electrode of the gate electrodes includes a ground selection line, and the lower semiconductor pattern passes through the ground selection line.
6. The semiconductor device of claim 1, further comprising a vertical insulator between the gate electrode and the channel structure,
wherein the vertical insulator includes a horizontal extension between the channel structure and the lower semiconductor pattern, an
The horizontal extension is parallel to the top surface of the lower semiconductor pattern and has an inclined profile.
7. The semiconductor device of claim 6, wherein the horizontal extension directly covers a top surface of the lower semiconductor pattern.
8. The semiconductor device according to claim 6, wherein the vertical insulating member includes a tunnel insulating layer, a blocking insulating layer, and a charge storage layer between the tunnel insulating layer and the blocking insulating layer,
the tunneling insulating layer is arranged to directly cover the outer side wall of the channel structure, an
The blocking insulating layer directly covers an inner sidewall of the gate electrode.
9. The semiconductor device according to claim 6, further comprising a blocking insulating layer between the vertical insulator and the gate electrode,
wherein, vertical insulating part includes:
the tunneling insulating layer directly covers the outer side wall of the channel structure; and
and a charge storage layer between the tunneling insulating layer and the blocking insulating layer.
10. A semiconductor device, the semiconductor device comprising:
a stack including insulating layers and gate electrodes alternately and repeatedly stacked on a substrate;
a lower semiconductor pattern protruding from the substrate into the stack in a vertical direction;
an upper portion of the lower semiconductor pattern having a width gradually decreasing in a direction away from the substrate; and
a channel structure penetrating the stack and connected to the lower semiconductor pattern, a lower portion of the channel structure penetrating an upper portion of the lower semiconductor pattern and extending beyond the upper portion of the lower semiconductor pattern,
wherein a bottom surface and a top surface of a bottom of the channel structure are lower than a bottom level of an upper portion of the lower semiconductor pattern,
wherein the channel structure includes a second semiconductor pillar and a first semiconductor pillar surrounding the second semiconductor pillar, a bottom surface of the second semiconductor pillar is lower than a bottom surface of the first semiconductor pillar, and the second semiconductor pillar contacts the lower semiconductor pattern,
wherein the second semiconductor pillar has a second thickness that is less than a thickness of the first semiconductor pillar such that a grain size of the second semiconductor pillar is reduced.
11. The semiconductor device according to claim 10, wherein an upper portion of the channel structure includes the first semiconductor pillar and the second semiconductor pillar and has a first thickness, and
the lower portion of the channel structure includes a second semiconductor pillar and has a second thickness that is 10% -40% of the first thickness.
12. The semiconductor device according to claim 10, further comprising an insulation gap fill pattern inside the channel structure,
wherein a bottom surface of the insulation gap fill pattern is lower than a bottom level of an upper portion of the lower semiconductor pattern.
13. The semiconductor device according to claim 10, further comprising a vertical insulator between the gate electrode and the channel structure,
wherein the vertical insulator includes a horizontal extension portion disposed between the channel structure and the lower semiconductor pattern, an
The lower portion of the channel structure passes through the horizontal extension portion and is connected to the lower semiconductor pattern.
14. The semiconductor device of claim 13, wherein the horizontal extension is parallel to a top surface of the lower semiconductor pattern and has an inclined profile.
15. The semiconductor device according to claim 13, wherein the vertical insulating member includes a tunnel insulating layer, a blocking insulating layer, and a charge storage layer between the tunnel insulating layer and the blocking insulating layer,
the tunneling insulating layer directly covers the outer side wall of the channel structure; and
the blocking insulating layer directly covers an inner sidewall of the gate electrode.
16. The semiconductor device according to claim 13, further comprising a blocking insulating layer between the vertical insulator and the gate electrode, wherein the vertical insulator comprises:
the tunneling insulating layer directly covers the outer side wall of the channel structure; and
and a charge storage layer between the tunneling insulating layer and the blocking insulating layer.
17. A semiconductor device, the semiconductor device comprising:
a stack including insulating layers and gate electrodes alternately and repeatedly stacked on a substrate;
a lower semiconductor pattern protruding from the substrate into the stack in a vertical direction;
a channel structure in the stack and connected to the lower semiconductor pattern; and
an insulation gap filling pattern in the channel structure, wherein the insulation gap filling pattern has a curved bottom surface,
wherein an upper portion of the lower semiconductor pattern has a width gradually decreasing in a direction away from the substrate, and a lowermost portion of the curved bottom surface of the insulation gap fill pattern is lower than a bottom level of the upper portion of the lower semiconductor pattern,
wherein the channel structure includes a second semiconductor pillar and a first semiconductor pillar surrounding the second semiconductor pillar, a bottom surface of the second semiconductor pillar is lower than a bottom surface of the first semiconductor pillar, and the second semiconductor pillar contacts the lower semiconductor pattern,
wherein the second semiconductor pillar has a second thickness that is less than a thickness of the first semiconductor pillar such that a grain size of the second semiconductor pillar is reduced.
18. The semiconductor device according to claim 17, wherein a lower portion of the insulation gap fill pattern has a width gradually decreasing in a direction toward the substrate.
19. The semiconductor device of claim 18, wherein the channel structure has a third thickness at a region adjacent to a lower portion of the insulation gap fill pattern,
the channel structure has a fourth thickness at a region under a lower portion of the insulation gap fill pattern, an
The fourth thickness is greater than the third thickness.
20. The semiconductor device of claim 17, wherein the lower semiconductor pattern has a recessed region, a lower portion of the second semiconductor pillar is inserted into the recessed region of the lower semiconductor pattern, and a second thickness of the lower portion of the second semiconductor pillar has a vertically varying thickness.
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