KR20130070124A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20130070124A
KR20130070124A KR1020110137287A KR20110137287A KR20130070124A KR 20130070124 A KR20130070124 A KR 20130070124A KR 1020110137287 A KR1020110137287 A KR 1020110137287A KR 20110137287 A KR20110137287 A KR 20110137287A KR 20130070124 A KR20130070124 A KR 20130070124A
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KR
South Korea
Prior art keywords
wiring
resistor
pad
test
wire
Prior art date
Application number
KR1020110137287A
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Korean (ko)
Inventor
최승만
백동천
여명수
윈두사리
이미지
정태영
최현준
Original Assignee
삼성전자주식회사
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Priority to KR1020110137287A priority Critical patent/KR20130070124A/en
Publication of KR20130070124A publication Critical patent/KR20130070124A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields

Abstract

It is to provide a semiconductor device which minimizes defects of a test wiring pattern before and after and during evaluation of metal wiring even when a resistor having a large resistance is connected to a structure for evaluating metal wiring to form an electrostatic discharge protection element. . The semiconductor device may include a test wiring pattern, a first wiring and a second wiring connected to one side and the other side of the test wiring pattern, respectively, and a first pad electrically connected to each other through the first wiring and the first resistor. A second pad electrically connected via a second wiring and a second resistor, third and fourth wires branched from the first and second wires, and a third pad electrically connected to the third wire; And a fourth pad electrically connected to the fourth wiring.

Description

Semiconductor device

The present invention relates to a semiconductor device.

As semiconductor devices have recently been highly integrated, it is essential to use multilayer metal wiring. In addition, in order to improve the problem of RC delay of metal wiring caused by the integration of semiconductor devices, an insulating film having weakened mechanical / physical characteristics is used, thereby ensuring reliability as well as electrical characteristics of the metal wiring. It is becoming very important.

In the semiconductor device production process on a substrate, the metallization process belongs to the back end process (BEOL). In order to evaluate the electrical characteristics and the reliability of the wiring itself, it is possible to evaluate only the second half process (BEOL) without performing the front end process (FEOL) including the transistor fabrication process. However, the structure for evaluating the electrical characteristics of the metal wiring is wrapped in an insulating film and placed in an electrically floating state. For this reason, when the electrostatic discharge protection diode cannot be formed because the FEOL process is not performed, the electrostatic discharge (ESD) is very vulnerable in evaluating the electrical characteristics of the metal wiring. That is, the scale of the metal wiring becomes further smaller with the high integration of the semiconductor element. When electrostatic discharge is applied to the smaller metal wires as described above, defects occur in the metal wires by Joule heating.

The problem to be solved by the present invention is that, even when a resistor having a large resistance is connected to the structure for evaluating the metal wiring, and the electrostatic discharge protection element is not formed, the defect of the test wiring pattern before and after and during the evaluation of the metal wiring is prevented. It is to provide a semiconductor device that minimizes.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

An aspect of the semiconductor device of the present invention for solving the above problems is a test wiring pattern, first wiring and second wiring connected to one side and the other side of the test wiring pattern, respectively, the first wiring and the first wiring A first pad electrically connected through a resistor, a second pad electrically connected through the second wire, and a second resistor; third wires and fourth wires branched from the first wire and the second wire, respectively; And a third pad electrically connected to the third wire, and a fourth pad electrically connected to the fourth wire.

Other specific details of the invention are included in the detailed description and drawings.

1 is a schematic view of a semiconductor device according to example embodiments.
2 is a perspective view illustrating a semiconductor device in accordance with an embodiment of the present invention.
3 is a perspective view illustrating a semiconductor device in accordance with another embodiment of the present invention.
4 is a plan view of FIG. 3.
5 is a cross-sectional view taken from AA when FIG. 4 is implemented on a substrate.
6 to 11 are plan views showing step by step methods for manufacturing a semiconductor device according to another embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

1 is a schematic view of a semiconductor device according to example embodiments. 2 is a perspective view illustrating a semiconductor device in accordance with an embodiment of the present invention.

First, referring to FIG. 1, a first wiring 200 and a first resistor 300 are sequentially connected to one side of a test wiring pattern 100. The first resistor 300 is electrically connected to the first pad 400a for applying a test bias. The second wiring 210 and the second resistor 310 are sequentially connected to the other side of the test wiring pattern 100. The second resistor 310 is electrically connected to the second pad 400b for applying a test bias. The third wire 220 is branched from the first wire 200 and electrically connected to the third pad 400c. The fourth wiring 230 is branched from the second wiring 210 and electrically connected to the fourth pad 400d. Although not shown in FIG. 1, a third resistor (see 320 in FIG. 3) is disposed between the third wiring 220 and the third pad 400c and between the fourth wiring 230 and the fourth pad 400d, respectively. The fourth resistor 330 of FIG. 3 may be disposed.

A test bias is applied using the first pad 400a and the second pad 400b. The characteristics of the test wiring pattern 100 due to the applied test bias are measured using the third pad 400c and the fourth pad 400d. The source for applying the test bias to the first pad 400a and the second pad 400b may be, for example, a voltage source, but is not limited thereto. For example, the third pad 400c and the fourth pad 400d may measure a voltage applied to the test wiring pattern 100. The third pad 400c and the fourth pad 400d are formed of the third wiring 220 and the fourth wiring branched from the first wiring 200 and the second wiring 210 closest to the test wiring pattern 100. Respectively electrically connected to the 230. Therefore, by using the third pad 400c and the fourth pad 400d, the characteristics of the test wiring pattern 100 may be measured by minimizing the influence of other patterns. In other words, it may be difficult to measure the characteristics of the wiring pattern 100 under test due to the influence of the first resistor 300 and the second resistor 310, and thus may be avoided through the third pad 400c and the fourth pad 400d. The characteristics of the test wiring pattern 100 may be directly measured.

Referring to FIG. 1, the role of the first resistor 300 and the second resistor 310 connected to one side and the other side of the test wiring pattern 100 will be described. If an electrostatic discharge is applied before, during, or during measurement of the characteristics of the test wiring pattern 100 in which the ESD protection device is not formed below, a defect may occur in the test wiring pattern 100. . That is, when the electrostatic discharge voltage is applied to the first pad 400a and the second pad 400b, Joule heat generation may occur, and the heat may cause a defect in the wiring pattern 100 to be tested. Joule heating value is inversely proportional to the resistance value when the voltage is constant. Therefore, since the static discharge voltage will generally be constant, increasing the resistance value between the first pad 400a and the second pad 400b may minimize the defect of the test wiring pattern 100. Since the space for the test pattern of the semiconductor device on the substrate is limited, in order to increase the resistance value between the first pad 400a and the second pad 400b, the first resistor 300 and the second resistor 310 are increased. ). Specifically, the first wire 200 and the first pad 400a are connected to each other through the first resistor 300 having a high resistance value, and the second wire (the second resistor 310 has a high resistance value). 210 and the second pad 400b are connected. As described above, the resistance value between the first pad 400a and the second pad 400b is increased to lower the amount of heat generated even when the electrostatic discharge voltage is applied. As a result, failure of the test wiring pattern 100 due to Joule heat generation can be prevented or reduced.

In addition, in order to minimize the occurrence of defects due to Joule heat generation, the third resistor 220 as shown in FIG. 3 is also used to measure the characteristics of the wiring pattern 100 under test 100. ) And the fourth resistor 330 may be introduced.

1 and 2, a semiconductor device according to an embodiment of the present invention may include a test wiring pattern 100, first to fourth wirings 300, 310, 320, and 330, and a first resistor 300. , The second resistor 310 and the first to fourth pads 400a, 400b, 400c, and 400d. The via pattern 100, the first wiring 200, the second wiring 210, the first resistor 300, and the second resistor 310 may further include a via 500, respectively.

Referring to FIG. 2, the first wiring 200, the first resistor 300, and the x-direction connecting wiring 600 are sequentially connected to one side of the test wiring pattern 100. The x-direction connecting wire 600 is electrically connected to the first pad 400a. The second wiring 210, the second resistor 310, and the x-direction connecting wiring 600 are sequentially connected to the other side of the test wiring pattern 100. The x-direction connecting wire 600 is electrically connected to the second pad 400b. The x-direction connecting wires 600 respectively connected to the first pad 400a and the second pad 400b are shown in FIG. 2 but are not limited thereto. That is, the x-direction connecting wire 600 may be sequentially arranged in the first direction x, and may include a metal pattern and a resistor connected in series. In FIG. 2, the test wiring pattern 100, the first and second wirings 200 and 220, the first and second resistors 300 and 310, and the x-direction connecting wire 600 all have a first direction (x). Although illustrated as being arranged in, but is not limited thereto. In other words, the test wiring pattern 100, the first and second wirings 200 and 220, the first and second resistors 300 and 310, and the x-direction connecting wiring 600 may be connected to each other in series. And need not be arranged in the same direction.

Referring to FIG. 2, the third wiring 220 may be branched from the first wiring 200, and the fourth wiring 230 may be branched from the second wiring 210. The third wire 220 is electrically connected to the third pad 400c and the fourth wire 230 is electrically connected to the fourth pad 400d. The third wiring 220 and the fourth wiring 230 are branched from the wiring closest to the test wiring pattern 100, but are not limited thereto. However, in order to more accurately measure the characteristics of the test wiring pattern 100, the third wiring 220 and the fourth wiring 230 may be branched from the wiring closest to the test wiring pattern 100. The first wire 200 and the third wire 220 may be included in the first metal pattern 200a. The first metal pattern 200a may form a T-shaped pattern, but is not limited thereto. The second wiring 210 and the fourth wiring 230 may be included in the second metal pattern 200b. The second metal pattern 200b may form a T-shaped pattern, but is not limited thereto. In FIG. 2, the third wiring 220 and the fourth wiring 230 are elongated in the second direction (y) and are shown to be spaced apart from each other, but are not limited thereto.

In detail, the first resistor 300 and the second resistor 310 may be, for example, poly Si having a higher resistance than a metal. The first resistor 300 and the second resistor 310 may be formed together, for example, when the gate polysilicon is formed on a substrate, but is not limited thereto. That is, the first resistor 300 and the second resistor 310 may be formed while the metal process is performed after the process of forming the transistor. For example, the first resistor 300 and the second resistor 310 may be doped with p-type impurities or n-type impurities.

The via 500 may be formed using, for example, tungsten (W). Each via formed on the first resistor 300 and the second resistor 310 may further include an adhesive film, for example, to improve bonding characteristics with the resistor. The test wiring pattern 100 may be connected to the first wiring 200 and the second wiring 210 through the via 500, respectively. Through the via, the first resistor 300 may be connected to the first wire 200, and the second resistor 310 may be connected to the second wire 210. Since the via 500 generally has a larger resistance than the metal used for the wiring, the via 500 also serves to protect the test wiring pattern 100 from the electrostatic discharge (ESD).

The metal pattern of the first to fourth wirings 200, 210, 220, and 230 and the x-direction connecting wire 600 may be, for example, aluminum (Al) or copper (Cu). The first to fourth wires 200, 210, 220, and 230 and the x-direction connecting wire 600 may be wires formed at the same time. The first to fourth wirings 200, 210, 220, and 230 and the x-direction connecting wire 600 may be connected to, for example, a contact with a source, a drain, and a gate of a transistor formed on a substrate. That is, the first to fourth wires 200, 210, 220, and 230 and the x-direction connecting wire 600 may be M1 wires of a semiconductor device, but are not limited thereto.

The test wiring pattern 100 may be, for example, aluminum (Al) or copper (Cu). The test wiring pattern 100 may be, for example, an M2 wiring connected to an M1 wiring of a semiconductor device, but is not limited thereto.

3 to 5, a semiconductor device according to another embodiment of the present invention will be described. This embodiment is substantially the same as the above-described embodiment except that a resistor is further connected to each of the third wiring 220 and the fourth wiring 230. Therefore, the same reference numerals are used to describe parts overlapping with the above-described embodiment, and description thereof will be briefly or omitted.

3 is a perspective view illustrating a semiconductor device in accordance with another embodiment of the present invention. 4 is a plan view of FIG. 3, and FIG. 5 is a cross-sectional view taken from AA when FIG. 4 is implemented on a substrate.

Referring to FIG. 3, the test wiring pattern 100 may be connected to the first wiring 200 and the second wiring 210. The first resistor 300 and the second resistor 310 may be connected to the first wire 200 and the second wire 210, respectively. The first pad 400a and the second pad 400b may be electrically connected to the first pad 400a and the second pad 400b through the x-direction connecting wire 600, respectively.

Referring to FIG. 3, the third resistor 320 and the y-direction connecting wire 610 are sequentially connected to the third wiring 220 branched from the first wiring 200. The fourth resistor 330 and the y-direction connecting wiring 610 are sequentially connected to the fourth wiring 230 branched from the second wiring 210. The y-direction connecting wire 610 may be connected to the third pad 400c and the fourth pad 400d, respectively. The y-direction connecting wire 610 is shown alone in FIG. 3, but is not limited thereto. That is, the y-direction connecting wire 610 may be sequentially arranged in the second direction y and may include a metal pattern and a resistor connected in series. The third wiring 220, the third resistor 320, and the y-direction connecting wire 610, and the fourth wiring 230, the fourth resistor 330, and the y-direction connecting wire 610 may each have a second direction ( y) but is not limited thereto.

In detail, the third resistor 320 and the fourth resistor 330 may be, for example, poly Si having a larger resistance than metal. The third resistor 320 and the fourth resistor 330 may be formed together, for example, when forming the gate polysilicon on the substrate, but is not limited thereto. In addition, the first to fourth resistors 300, 310, 320, and 330 may be formed at the same time, for example, an impurity may be doped.

The third resistor 320 may be connected to the third wire through the via 500, and the fourth resistor 330 may be connected to the fourth wire 230. Each via 500 between the third resistor 320 and the third wire 220, and between the fourth resistor 330 and the fourth wire 230, is a third wire 220 and a fourth wire from the electrostatic discharge. The wiring 230 may be protected.

Referring to FIG. 4, the x-direction connecting wiring 600, the first resistor 300, the first wiring 200, the test wiring pattern 100, the second wiring 210, the second resistor 310 and The conductive wire L including the x-direction connecting wire 600 is disposed in the first direction x. Each component of the conductive wire L is connected in series to form a chain structure. The third wiring 220, the third resistor 320, and the y-direction connecting wiring 610 are connected to the conductive wiring L in parallel and form a chain structure. The fourth wiring 230, the fourth resistor 330, and the y-direction connecting wiring 610 are connected in parallel to the conductive wiring L, and also form a chain structure. Looking at only the x-direction connecting wiring 600, the first resistor 300, the first wiring 200, the third wiring 220, the third resistor 320 and the y-direction connecting wiring 610, this continuous wiring diagram is shown. It has a chain structure.

Referring to FIG. 5, a first resistor 300 and a second resistor 310 are disposed on the substrate 10. Insulation layers 300i and 310i may be disposed below the first resistor 300 and the second resistor 310, respectively. The first resistor 300 and the second resistor 310 may be formed like a gate polysilicon, and an insulating layer may be disposed below, but is not limited thereto. That is, when the first resistor 300 and the second resistor 310 are formed during the metal wiring process, the insulating film may not be formed.

The first interconnection 200, the second interconnection 210, and the x-direction interconnection line 600 are disposed on the interlayer insulating layer 20. Through the via 500, the first resistor 300 is connected to the first wiring 200 and the x-direction connecting wire 600, and the second resistor 310 is connected to the second wiring 210 and the x-direction. It is connected to the wiring 600, respectively. The test wiring pattern 100 is disposed in the inter-wire insulating film 30. For example, an upper surface of the test wiring pattern 100 may be exposed, but is not limited thereto. That is, the test wiring pattern 100 may be surrounded by the inter-wire insulating film 30, and only a part thereof may be surrounded by the inter-wire insulating film 30.

Referring to FIG. 5, the x-direction connecting wire 600 is connected to the first resistor 300 and the via 500, and the first resistor 300 is connected to the first wire 200 and the via. The first wiring 200 is connected to the test wiring pattern 100 and the via 500 again, and the test wiring pattern 100, the second wiring 210, the second resistor 310, and the x-direction connecting wiring are connected to each other. 600 is sequentially connected to via 500. 4 and 5, components disposed between the first pad 400a and the second pad 400b are connected in series with each other, and form a chain structure through the via 500.

6 to 11, a method of forming a semiconductor device according to another exemplary embodiment of the present invention will be briefly described. 6 to 11 are plan views showing step by step methods for manufacturing a semiconductor device according to another embodiment of the present invention. For the sake of clarity, the semiconductor device described with reference to FIGS. 2 and 3 will hereinafter be referred to as a test structure.

Referring to FIG. 6, a substrate 10 in which an active region 10b and a test region 10a are defined is provided. The test structure described above with reference to FIGS. 2 and 3 may be formed in, for example, the test area 10a, but is not limited thereto.

Referring to FIG. 7, first to fourth resistors 300, 310, 320, and 330 are formed on the test region 10a. The first resistor 300 and the second resistor 310 are shown to have a different length from the third resistor 320 and the fourth resistor 330, but are not limited thereto. In addition, the first to fourth resistors 300, 310, 320, and 330 are illustrated as rectangular, but are not intended to be limited to the exemplary embodiments of the present disclosure.

Referring to FIG. 8, an interlayer insulating film 20 is formed on the test region 10a. The interlayer insulating layer 20 may include an opening 20a exposing portions of the first to fourth resistors 300, 310, 320, and 330. The interlayer insulating film 20a may be, for example, silicon oxide, but is not limited thereto. Although not shown in FIG. 8, the opening 20a may be filled with a metal, for example tungsten (W), to form a via.

9, an M1 metal is formed on the interlayer insulating film 20. The metal M1 includes the first to fourth wirings 200, 210, 220, and 230, a metal pattern of the x-direction connecting wire 600, and a metal pattern of the y-direction connecting wire 610. The M1 metal may be, for example, aluminum (Al) or copper (Cu), but is not limited thereto. In FIG. 8, the M1 metal may be connected to the first through fourth resistors 300, 310, 320, and 330 under the interlayer insulating layer 20 through the vias 500 filling the openings 20a.

10 and 11, an intermetallic insulating film 30 is formed on the M1 metal. The inter-wire insulating film 30 may include an opening 30a exposing a portion of the first wire 200 and the second wire of the M1 metal. The inter-wire insulating film 30 may be, for example, an insulating film having a lower dielectric constant than silicon oxide, but is not limited thereto. Although not shown in FIG. 10, the opening 30a may be filled with a metal, for example tungsten (W), to form a via. In FIG. 11, the test wiring pattern 100 is formed on the intermetallic insulating film 30. Through the via 500 filling the opening 30a in the inter-wire insulating film 30, one side of the test wiring pattern 100 is formed of the first wiring 200, and the other side of the test wiring pattern 100 is formed of the first wiring 200. 2 may be connected to the wiring 210. First pads (not shown) and second pads (not shown) may be formed at both ends of the x-direction connecting wire 600, respectively, and third pads (not shown) at one end of the y-direction connecting wire 610. ) And a fourth pad (not shown) may be formed.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: test wiring pattern 200: first wiring
210: second wiring 220: third wiring
230: fourth wiring 300: first resistor
310: first resistor 320: third resistor
330: fourth resistor 500: via

Claims (10)

Test wiring pattern;
First and second wirings connected to one side and the other side of the test wiring pattern, respectively;
A first pad electrically connected through the first wire and the first resistor, and a second pad electrically connected through the second wire and the second resistor;
Third and fourth wirings branched from the first and second wirings, respectively; And
And a third pad electrically connected to the third wiring, and a fourth pad electrically connected to the fourth wiring. The method according to claim 1,
A semiconductor device which applies a test bias using the first pad and the second pad and measures a characteristic of the test wiring pattern using the third pad and the fourth pad. The method according to claim 1,
The first resistor and the second resistor is polysilicon. The method according to claim 1,
The first resistor is connected to the first wiring, and the second resistor is connected to the second wiring through a via, respectively. The method according to claim 1,
The first wiring and the third wiring form a T-shaped pattern, and the second wiring and the fourth wiring form a T-shaped pattern. The method according to claim 1,
The first resistor, the first wiring, the test wiring pattern, the second wiring and the second resistor are arranged and connected in a first direction,
The third wiring and the fourth wiring are arranged in a second direction different from the first direction. The method according to claim 1,
A third resistor connecting the third wire and the third pad;
And a fourth resistor connecting the fourth wiring and the fourth pad to each other. The method of claim 7, wherein
The third resistor and the fourth resistor are polysilicon. The method of claim 7, wherein
The third resistor is connected to the third wiring, and the fourth resistor is connected to the fourth wiring via a via. The method of claim 7, wherein
A conductive wiring including the first resistor, the first wiring, the test wiring pattern, the second wiring, and the second resistor forms a chain structure connected in series;
And the third wiring, the third resistor, the fourth wiring and the fourth resistor are connected in parallel with the conductive wiring to form a chain structure.
KR1020110137287A 2011-12-19 2011-12-19 Semiconductor device KR20130070124A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510746B2 (en) 2017-09-28 2019-12-17 Samsung Electronics Co., Ltd. Semiconductor device including electrostatic discharge protection patterns

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510746B2 (en) 2017-09-28 2019-12-17 Samsung Electronics Co., Ltd. Semiconductor device including electrostatic discharge protection patterns

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