KR20130067131A - Method and system for accelerating graphic dispsplay on multi-channel image system - Google Patents

Abstract

PURPOSE: A system for output acceleration in a multi channel image system and a method thereof are provided to prevent system resources from being wasted, by rendering a full screen to add a screen according to each channel as one module, and performing the rendering process separately from a decoding process which operates according to each channel. CONSTITUTION: A decoding unit(100) decodes input image data according to each channel. A writer unit(300) writes the decoded data in a buffer according to each channel. A rendering unit(400) forms data according to a channel written in the buffer with a full screen, and performs the rendering of the full screen. [Reference numerals] (100) Decoding unit; (200) Memory unit; (20a) First preprocessing unit; (20b) Second preprocessing unit; (20c) Third preprocessing unit; (20d) Fourth preprocessing unit; (30) Output signal; (300) Writer unit; (40) Control unit; (400) Rendering unit; (AA) System memory; (BB) Video memory

Description

METHOD AND SYSTEM FOR ACCELERATING GRAPHIC DISPSPLAY ON MULTI-CHANNEL IMAGE SYSTEM}

The present invention relates to a system and method for output acceleration in a multichannel imaging system. More specifically, the present invention relates to a system that renders a multi-channel image as a full screen to increase the efficiency of using system resources and to speed up image processing by not storing decoded image data in a memory.

As an example of receiving video signals from a plurality of channels and outputting them to one screen, there is a security system that supports multi-channel monitoring.

Such a multi-channel system is capable of recording and displaying a multi-channel image input from a plurality of cameras. For example, a system may be configured to display image signals input from four cameras in four divisions within a screen of one display device, and to display and record image information for each channel.

The multi-channel image requires more system resources such as memory, CPU, etc. in order to render the multi-channel, the larger the resolution of the input image, the more the number of times per second of the input image.

1 is a diagram illustrating a process of decoding and rendering in a conventional multichannel image processing system.

Referring to FIG. 1, the compressed image for each channel received from the imaging apparatus is output as a divided image in the entire screen of the display apparatus 500 through decoding and rendering for each channel.

Conventionally, since decoding and rendering of each of the first to fourth compressed images input from each of the first to fourth channels must be performed, modules (a, b, c, and d) for each channel must be separately provided. did. Therefore, since the number of rendering times the number of frames multiplied by the number of channels, more memory resources are required as the number of channels increases.

In addition, conventionally, decoded image information is placed in a system memory or a video memory, and then transferred to a buffer for output. However, this method has a problem that additional system resources for storing the decoded data in the memory are additionally required and time is delayed.

SUMMARY OF THE INVENTION The present invention has been made to solve all the problems of the prior art described above.

According to the present invention, the screen for each channel is configured as a whole screen to perform rendering as one module, and the rendering process is moved separately from the decoding process for each channel.

In another embodiment of the present invention, the decoded image stream data is not stored in the system memory or the video memory, but is directly written to the buffer by the writer.

In order to accomplish the above object, a representative structure of the present invention is as follows.

The present invention provides a decoding unit for decoding input image data for each channel; A writer for writing the decoded data into a buffer for each channel; And a rendering unit configured to configure data for each channel written in the buffer into a full screen, and render the entire screen. It provides a multi-channel video output acceleration system comprising a.

In the present invention, the lighter unit is characterized in that the asynchronous operation with the decoding unit.

In the present invention, the writer unit does not occupy a memory when writing the decoded data to the buffer.

In the present invention, the lighter unit writes image data at a suitable position of the buffer using identification information and position information of each channel.

In the present invention, the decoded input data is transmitted directly to the writer without being stored in the memory.

In addition, the present invention, the step of decoding the input image data for each channel; Writing the decoded data into a buffer for each channel; And organizing data for each channel written in the buffer into a full screen, and rendering the full screen. It provides a multi-channel video output acceleration method comprising a.

In the present invention, the writing to the buffer may be performed asynchronously with the decoding.

In the present invention, the writing to the buffer is characterized in that it does not occupy a memory when writing the decoded data to the buffer.

In the present invention, the step of writing to the buffer is characterized in that the image data is written to an appropriate position of the buffer by using the identification information and the position information for each channel.

In the present invention, the decoded input data is not stored in the memory, but is written directly to the buffer for each channel.

According to the present invention, rendering is performed as a module for the entire screen in which the screens for each channel are combined, and the rendering process is performed separately from the decoding process for each channel to prevent waste of system resources.

In addition, according to the present invention, the decoded image stream data is not stored in the system memory or the video memory, but is directly written to the buffer by the writer, thereby increasing the efficiency of using system resources and increasing the image processing speed.

1 is a diagram illustrating a process of decoding and rendering in a conventional multichannel image processing system.
2 is a diagram schematically illustrating a multi-channel image output system according to an embodiment of the present invention.
3 is a diagram illustrating an internal configuration of a multi-channel image output acceleration system according to an embodiment of the present invention.
4 is a diagram illustrating a part of an image processing process according to an embodiment of the present invention.
5 is a view illustrating a method in which a writer writes image data in a buffer unit according to an embodiment of the present invention.
6 is a diagram illustrating a case where an entire screen area displaying multiple channels is rendered as one module according to an embodiment of the present invention.
7 is a flowchart illustrating a process procedure of a multi-channel video acceleration system according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, the specific shapes, structures, and characteristics described herein may be implemented by changing from one embodiment to another without departing from the spirit and scope of the invention. It should also be understood that the location or arrangement of individual components within each embodiment may be varied without departing from the spirit and scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention should be construed as encompassing the scope of the appended claims and all equivalents thereof. In the drawings, like reference numbers designate the same or similar components throughout the several views.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to which the present invention pertains.

2 is a diagram schematically illustrating a multi-channel image output system according to an embodiment of the present invention.

Referring to FIG. 2, the multichannel imaging system may include a plurality of imaging devices 10a, 10b, 10c, and 10d, a multichannel image output acceleration system 10, and an output device.

The plurality of imaging devices 10a, 10b, 10c, and 10d are installed in respective areas where imaging is required, and provide an image of the corresponding area. The plurality of imaging devices 10a, 10b, 10c, and 10d are devices capable of capturing an image and may be, for example, a camera, a camcorder, or a CCTV. In addition, although the plurality of imaging devices 10a, 10b, 10c, and 10d may additionally receive and provide sound as well as an image, sound input is not essential to the practice of the present invention. The number of the plurality of imaging devices 10a, 10b, 10c, and 10d may vary depending on the actual implementation of the present invention. Each image captured by the plurality of imaging devices 10a, 10b, 10c, and 10d may occupy one channel.

Images captured by the plurality of imaging devices 10a, 10b, 10c, and 10d are transmitted to the multi-channel image output acceleration system 10. The multi-channel image output acceleration system 10 generates an output signal by performing preprocessing including an analog / digital conversion on the received image, decoding the channel, recording the buffer, and rendering the image. The multi-channel image output acceleration system 10 transmits an output signal to the display apparatus 500. Each configuration of the multi-channel video output acceleration system 10 will be described in more detail below.

The display apparatus 500 refers to a device capable of obtaining a multi-channel image and dividing and outputting one screen. The multi-channel display apparatus 500 may be adopted as the display apparatus 500 of the present invention as long as it is a device having a screen capable of dividing a screen and outputting the screen, without being limited to a TV and a monitor. The display apparatus 500 displays an image processed by the multi-channel image output acceleration system 10. In addition, the display unit may display various setting screens for controlling the multi-channel image output acceleration system 10.

3 is a diagram illustrating an internal configuration of a multi-channel image output acceleration system 10 according to an embodiment of the present invention.

Referring to FIG. 3, the multi-channel image output acceleration system 10 may include a preprocessor 20a, 20b, 20c, and 20d, a decoder 100, a memory 200, a writer 300, and a renderer. The unit 400 includes an output unit 30 and a control unit 40.

First, the preprocessors 20a, 20b, 20c, and 20d convert input data provided from the plurality of imaging devices 10a, 10b, 10c, and 10d into analog signals. The analog-digital changer may be provided by each imaging device, and each preprocessor 20a, 20b, 20c, and 20d may be provided for each imaging device and one channel. The plurality of imaging devices 10a, 10b, 10c, and 10d may provide imaging data corresponding to each of the preprocessing units 20a, 20b, 20c, and 20d.

Next, the decoding unit 100 is an apparatus including one or more decoders 120a, 120b, 120c, and 120d to be described later. The decoders 120a, 120b, 120c, and 120d may decode an input signal and transmit the decoded signal to the memory unit 200 or the writer unit 300. The decoder 100 may include decoders 120a, 120b, 120c, and 120d for each input channel, and may perform decoding for each channel.

Next, the memory unit 200 temporarily stores the decoded input image. The memory unit 200 may store images of multiple channels in units of one frame or one field for each channel. The memory unit 200 may control video signal writing and reading to display a plurality of divided screens on one screen.

More specifically, the memory unit 200 includes a computer storage medium in the form of removable or non-removable, volatile or nonvolatile memory. In the illustrated embodiment, the system memory can include read only memory (ROM) and random access memory (RAM). In addition, a basic input / output program including a basic routine to help information transfer between components in the controller 40 may also be stored in the memory unit 200.

In addition, the memory unit 200 may be configured of a system memory and a video memory. In a typical image output system, transferring the image information stored in the system memory to an output buffer to be described later uses a large amount of system resources such as a CPU and consumes a lot of time. Also, moving image information in the video memory to the output buffer is fast but limited by the size of the video memory. That is, the operation of storing the image data in the memory unit 200 and then moving the image data back to the output buffer is time consuming or uses a large amount of system resources, and may be affected by the performance of the memory unit 200 itself.

Accordingly, the multi-output image output acceleration system according to an exemplary embodiment of the present invention may transmit the decoded image data directly to the writer 300 without storing the decoded image data in the memory 200. When the image data is transmitted to the writer 300 without passing through the memory unit 200, the ratio of memory resources for storing the decoded data can be reduced, and the time for storing the decoded data in the memory and the image data of the memory are output again. You can reduce the time to write to the buffer.

Next, the writer 300 may serve to write the decoded image data to the buffer. When processing multi-channel images at the same time, it is necessary to temporarily store data in a buffer and render it for efficient work. The writer 300 may include writers 310a, 310b, 310c, and 310d for each channel to be described later and a buffer 320 to write decoded image stream data to a buffer.

In addition, the decoding unit 100 and the lighter unit 300 may operate asynchronously. When the decoding unit 100 and the writer unit 300 operate asynchronously, the subsequent rendering process and the decoding process are separated independently from each other, so the performance of the other side should be limited to either performance of decoding or rendering. System resources can be used efficiently.

Next, the renderer 400 may serve to render the image data temporarily recorded in the buffer. In this case, the rendering unit 400 may configure a separate channel as one screen to perform rendering for the entire screen area at once. That is, in the multi-channel image acceleration system according to an exemplary embodiment of the present invention, the multi-channel image acceleration system does not render the screen for each channel but renders the entire display area displaying the multi-channel.

Therefore, unlike the conventional multichannel rendering method in which the number of rendering is to be performed by N * isp multiplied by the number of images N times the number of frames per second (ips), only 1 * frames (ips) are rendered. As a result, even if the number of channels increases, the amount of system resources required for rendering can be kept constant. That is, the rendering unit 400 renders the entire screen instead of rendering each of the multiple channels, thereby minimizing system resources required for rendering.

Next, the output unit 30 may generate an output signal for each channel of the image rendered by the renderer 400 as a full screen. The output signal may be generated using the image in the front buffer while the renderer 400 renders the image in the back buffer. The display apparatus 500 may receive image data to be output to the divided region of the screen and display the image on the screen as a full screen.

Finally, the controller 40 controls the flow of data between the decoding unit 100, the memory unit 200, the writer unit 300, the memory unit 200, the writer unit 300, and the renderer 400. Function can be performed. That is, the control unit 40 according to the present invention controls the data flow between the components of the multi-channel image acceleration system, the decoding unit 100, the memory unit 200, the writer unit 300 and the rendering unit 400 Each can control its own function and control the processes of each part.

4 is a diagram illustrating a part of an image processing process according to an embodiment of the present invention.

Referring to FIG. 4, it may be assumed that four channels are formed on one screen of the display apparatus 500 according to an embodiment of the present invention.

The decoding unit 100 may include frame queues 110a, 110b, 110c, and 110d for each channel, and decoders 120a, 120b, 120c, and 120d for each channel. Referring to FIG. 4, each of the frame queues 110a, 110b, 110c, and 110d may store an image transmitted from the imaging apparatuses 10a, 10b, 10c, and 10d forming one channel.

In addition, the decoders 120a, 120b, 120c, and 120d may obtain and decode image frame data from each of the frame queues 110a, 110b, 110c, and 110d. The decoders 120a, 120b, 120c, and 120d decode image frame data for each channel, convert the image frame data received from the frame queues 110a, 110b, 110c, and 110d into image stream data, and then write the lighter unit 300. Can be sent to.

In addition, referring to FIG. 4, the image stream data transmitted from the decoding unit 100 may be directly transmitted to the writer 300 without passing through the memory 200. As described above, in general, the image data is stored in the system memory or video memory and then moved to the buffer for output and output, but the decoded image data is output directly without passing through the memory as in the exemplary embodiment of the present invention. Writing to the buffer has the effect of saving system resources and reducing processing time.

In addition, referring to FIG. 4, the lighter unit 300 may include lighters 310a, 310b, 310c, and 310d and a buffer unit 320 for each channel. The writers 310a, 310b, 310c, and 310d may receive image stream data from the decoding unit 100 and write the image stream data to the buffer unit 320. The writer 300 for each channel receives the image stream data from the corresponding decoder 120a, 120b, 120c, or 120d for each channel, and performs a role of writing the buffer 320 to the back buffer in more detail. Can be.

In addition, the writers 310a, 310b, 310c, and 310d may convert the received image data into a buffer size to write the buffer 320. In addition, the process of writing the image to the buffer unit 320 by the lighters 310a, 310b, 310c, and 310d does not occupy memory space on the system, unlike the memory unit 200 writes image data to the system memory or the video memory. Do not.

The position at which the writers 310a, 310b, 310c, 310d write image data in the buffer unit 320 may be set by the controller 40 in advance. That is, when the writer writes an image in the buffer unit 320, the image data may be written at an appropriate position of the buffer using the identification information and the position information of each channel.

In addition, the buffer unit 320 temporarily stores image stream data in order to render the multi-channel image before final output. Although not shown in FIG. 4, the buffer unit 320 may include a front buffer and a back buffer. The writers 310a, 310b, 310c, and 310d of each channel can write image stream data to the back buffer, and the data written to the back buffer is rendered by the rendering unit 400 and then moved to the front buffer (or, front). After the functions of the buffers and back buffers are changed, output signal data can be formed.

5 is a view illustrating a method in which a writer writes image data in a buffer unit according to an embodiment of the present invention.

Referring to FIG. 5, each of the lighter modules 311a, 311b, 311c, and 311d occupies a predetermined area of the entire buffer unit 320, and a lighter module corresponding to each channel at a designated position includes channel identification information and position. You can see that the information is used to write image stream data. The rendering unit 400 may read and render the entire screen area including the image for each channel written by each writer module at an appropriate position of the buffer from the buffer unit 320.

In addition, as described above, the decoding unit 100 and the lighter unit 300 operate asynchronously. Therefore, since the decoding unit 100 and the writer unit 300 do the work independently without being influenced by the performance of each other, the decoding unit 100 and the lighter unit 300 do not need to wait until the completion of one operation can efficiently use the resources of the system.

Next, the rendering unit 400 may serve to render the data recorded in the buffer before outputting as described above. As described above, the renderer 400 is different from the decoders 120a, 120b, 120c, and 120d or the writers 310a, 310b, 310c, and 310d per channel, respectively. Perform rendering on the.

6 is a diagram illustrating a case where an entire screen area displaying multiple channels is rendered as one module according to an embodiment of the present invention.

The decoding and rendering process will be described with reference to FIG. 6 and FIG. 1 as described above.

First, as described above, in the general monitoring viewer of FIG. 1, when rendering each camera input image, each input image is configured as a module to generate and operate necessary resources. In this case, memory for input image and memory space and resources for rendering are required, and n rendering processes should be performed when an image of n frames per second is input. That is, in FIG. 1, one rendering module (a, b, c, d) for rendering per channel is provided, and a compressed image is decoded for each channel in each module, and the decoded image is rendered by each display. It is shown as a split screen on the device 500.

In contrast to FIG. 1, referring to FIG. 6 according to an exemplary embodiment of the present invention, the multi-channel image output acceleration system 10 of the present invention also includes compressed channels 11a, 11b, 11c, and 11d for each channel. It can be seen that it is decoded by the star decoders 120a, 120b, 120c, and 120d. However, unlike the configuration of FIG. 1, it can be seen that in FIG. 6, the image data decoded for each channel is rendered by one renderer 400.

That is, in the conventional multichannel image processing system of FIG. 1, the structure of the decoding and rendering software module of the display device is configured as one module for each channel, but the multichannel image output acceleration system of the present invention displays a multichannel. The module can be designed to share the system's resources by configuring the entire screen area of a single module to perform rendering at once. In other words, even if the number of channels increases, the number of renderings can be kept constant, thereby minimizing system resources required for rendering.

7 is a flowchart illustrating a process procedure of a multi-channel video acceleration system according to an embodiment of the present invention.

Referring to Fig. 7, first, a plurality of image information to be displayed on the display device is generated by the plurality of imaging window values (step S1).

Next, the preprocessing units 20a, 20b, 20c, and 20d perform preprocessing necessary for analog-to-digital conversion and image output on the images acquired by the imaging apparatuses 10a, 10b, 10c, and 10d (step S2).

Next, the decoding unit 100 decodes the image frame data that has been preprocessed for each channel (step S3). In this case, the decoding unit 100 may transmit the decoded image stream data directly to the writer 300 without passing through the memory.

Next, the writer 300 may play a role of writing the received image stream data to the buffer unit 320 using the module writer 310a, 310b, 310c, 310d for each channel (step S4). The lighter modules 310a, 310b, 310c, and 310d of the lighter unit 300 operate for each channel, but operate asynchronously with the decoding unit 100 and do not occupy memory.

Next, the image written in the buffer is rendered by the rendering unit 400 (step S5). In this case, as the lighter unit 300 operates asynchronously with the decoding unit 100, the rendering unit 400 operates asynchronously with the decoding unit 100, and thus is composed of a full screen regardless of the performance of the decoding unit 100. Render the image.

Finally, an output signal for an area capable of outputting respective channels to the display apparatus 500 is generated based on the rendered full screen data (step S6).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Those skilled in the art will appreciate that various modifications and changes may be made thereto without departing from the scope of the present invention. In addition, the components described as a system in the present invention can be implemented in a method having the same features, and vice versa.

Accordingly, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all ranges that are equivalent to or equivalent to the claims of the present invention as well as the claims .

10: multi-channel video output acceleration system
10a, 10b, 10c, and 10d: imaging device
11a, 11b, 11c, 11d: compressed video
20: preprocessing unit 30: output unit
40: control unit 100: decoding unit
110: frame cue 120: decoder
200: memory portion 300: lighter portion
310: lighter 320: buffer unit
400: rendering unit 500: display device

Claims (10)

A decoder which decodes input image data for each channel;
A writer for writing the decoded data into a buffer for each channel; And
A rendering unit which configures data for each channel written in the buffer into a full screen and renders the entire screen;
Multi-channel video output acceleration system including The method of claim 1,
And the writer unit operates asynchronously with the decoding unit. The method of claim 1,
And wherein the writer does not occupy a memory when writing the decoded data to the buffer. The method of claim 1,
And the writer unit writes image data at an appropriate position of the buffer using identification information and position information of each channel. The method of claim 1,
The decoded input data is transmitted to the writer unit directly without being stored in the memory. Decoding input image data for each channel;
Writing the decoded data into a buffer for each channel; And
Constructing a full screen of data for each channel written in the buffer, and rendering the entire screen;
Multi-channel video output acceleration method comprising a The method according to claim 6,
And writing to the buffer operates asynchronously with the decoding. The method according to claim 6,
And the writing to the buffer does not occupy a memory when writing the decoded data to the buffer. The method according to claim 6,
The writing to the buffer is a multi-channel video output acceleration method, characterized in that for writing the image data in the appropriate position of the buffer using the identification information and position information for each channel. The method according to claim 6,
The decoded input data is not stored in the memory, but is written to the buffer for each channel, multi-channel video output acceleration method.

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