JP2011101273A - Image processing apparatus, method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the characteristics of an electronic shutter approximate to the characteristics of a mechanical shutter. <P>SOLUTION: A timing generation circuit 31 generates timing pulses for controlling the electronic shutter. When the electronic shutter is used as a front curtain, and the mechanical shutter is used as a rear curtain, the mechanical shutter has a possibility that exposure time may differ by line since speed changes to perform an acceleration motion. The timing pulses are generated by the timing generation circuit 31 so that the control of the electronic shutter is performed to match the change in the speed of the mechanical shutter. Namely, the timing pulses are generated so that the number of lines to be read simultaneously gradually increases, as in: one line, two lines, four lines, eight lines, with the passage of time from the start of reading. The invention is applicable to digital still cameras. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, method, and program, and more particularly, to an image processing apparatus, method, and program suitable for use in controlling an electronic shutter of an imaging apparatus including a mechanical shutter and an electronic shutter.

  In an imaging apparatus represented by a digital still camera or the like, a mechanical shutter (hereinafter referred to as a mechanical shutter) and an electronic shutter (hereinafter referred to as an electronic shutter) incorporated in a sensor are used. The sensor is, for example, a CMOS image sensor.

  FIG. 1 shows the operation characteristics of each shutter when a mechanical shutter and an electronic shutter are used. The mechanical shutter (front curtain) is physically accelerating because it is driven by a spring, and its operation is shown by a high-order curve as shown by a thin line in FIG. On the other hand, since the electronic shutter drives the shutter by sequentially specifying addresses (rolling shutter), its operation is linear as shown by a bold line in FIG.

  In the mechanical shutter, the characteristics of the front curtain and the rear curtain are the same, so the exposure time T0 is the same in every row. On the other hand, if the mechanical shutter (front curtain) is replaced with an electronic shutter to reduce the number of parts, the exposure time T1 varies depending on the row due to the difference between the linear characteristics of the electrons and the higher-order characteristics of the rear curtain.

  The exposure time is preferably equal for each row. Therefore, in order to eliminate the difference in exposure time due to the use of the electronic shutter for the front curtain and the mechanical shutter for the rear curtain, the characteristics of the electronic shutter are combined with a plurality of linear characteristics, as shown by the bold lines in FIG. It has been proposed to perform a nonlinear operation by approximating the polygonal line. Thus, a method for approximating the characteristics of the electronic shutter to the characteristics of the mechanical shutter has been proposed. In order to realize such characteristics of the electronic shutter, in the technique described in Patent Document 1, it is proposed to incorporate a system that follows the operation of the mechanical shutter.

JP 2008-147799 A

  The system that follows the operation of the mechanical shutter proposed in Patent Document 1 may be increased in scale. For this reason, it is difficult to incorporate in an imaging apparatus that has been downsized in recent years, and the imaging apparatus becomes large and cannot be downsized by incorporating the imaging apparatus. Further, when the mechanical shutter operates at a high speed, the number of address decoders in the V driving device in the image sensor is limited, so that it is difficult for the pixel reset operation by address designation to follow the shutter operation.

  The present invention has been made in view of such a situation, and makes it possible to easily obtain characteristics close to a mechanical shutter by controlling the characteristics of an electronic shutter.

  An image processing apparatus according to an aspect of the present invention includes a generating unit that acquires and counts timing pulses for driving an electronic shutter, and generates a signal that specifies an address line for performing an electronic shutter operation according to the count value; Driving means for generating a pixel reset signal and driving an electronic shutter for the address row generated by the generating means based on the pixel reset signal, wherein the generating means is a high speed with a short interval between the timing pulses. When it is determined that the shutter operation is performed, a leading address row for performing the electronic shutter operation is designated, and a pixel reset signal for operating the electronic shutter for a plurality of rows including the leading row is transmitted by the driving unit. An instruction signal for instructing the generation is also generated.

  The driving unit includes a predecoder that decodes a predetermined number of lower bits of the address generated by the generating unit, and the instruction signal generated by the generating unit is supplied to the predecoder. Can be.

  Storage means for storing characteristics of a mechanical shutter used as a rear curtain is further provided, and the generation means generates the instruction signal for generating the pixel reset signal that matches the characteristics stored in the storage means. Can be.

  The plurality of rows may be 2N rows, and the predecoder may be configured such that circuits for controlling 2N row simultaneous shutters are vertically connected.

  An image processing method according to one aspect of the present invention is an image processing method of an image processing apparatus including an electronic shutter, acquires timing pulses for driving the electronic shutter, counts them, and performs an electronic shutter operation according to the count value. Generating a signal for designating an address row, generating a pixel reset signal, and driving an electronic shutter for the address row generated by the generating means based on the pixel reset signal, the timing pulse interval Is a short high-speed shutter operation, a head address line for performing the electronic shutter operation is designated, and a pixel reset signal for operating the electronic shutter is generated for a plurality of rows including the head row.

  The program according to one aspect of the present invention is a program readable by a computer that controls an image processing apparatus including an electronic shutter. The timing pulse for driving the electronic shutter is acquired and counted, and the electronic shutter is calculated based on the count value. Generating a signal designating an address row to be operated, generating a pixel reset signal, and driving an electronic shutter for the address row generated by the generating means based on the pixel reset signal, the timing In the case of a high-speed shutter operation with a short pulse interval, a head address row for performing the electronic shutter operation is designated, and a pixel reset signal for operating the electronic shutter is generated for a plurality of rows including the head row. A computer-readable program that executes processing.

  In the image processing apparatus and method, and the program according to one aspect of the present invention, the timing pulse for driving the electronic shutter is counted, and the address line for performing the electronic shutter operation is designated by the count value. In some cases, the electronic shutter is operated for a plurality of rows including the designated address row.

  According to one aspect of the present invention, the characteristics of the electronic shutter can be controlled, and characteristics close to that of a mechanical shutter can be easily obtained.

It is a figure explaining the characteristic of the conventional mechanical shutter and an electronic shutter. It is a figure explaining the characteristic of the conventional mechanical shutter and an electronic shutter. It is a figure which shows the structure of one Embodiment of the drive device to which this invention is applied. It is a figure which shows the structural example of an image sensor. It is a figure which shows the structural example of V drive device. It is a figure which shows the structural example of a predecoder. It is a figure explaining the timing pulse of an electronic shutter. 6 is a flowchart for explaining the operation of the timing generation circuit. It is a figure for demonstrating a recording medium.

  Embodiments of the present invention will be described below with reference to the drawings.

[Configuration of image processing apparatus]
FIG. 3 is a diagram showing a configuration of an embodiment of an image processing apparatus to which the present invention is applied. The image processing apparatus 10 illustrated in FIG. 3 is incorporated into an imaging apparatus such as a digital still camera, for example. The image processing apparatus 10 uses a mechanical shutter (hereinafter referred to as a mechanical shutter) and an electronic shutter (hereinafter referred to as an electronic shutter) built in the sensor, and controls the electronic shutter. Mainly done.

  Here, the mechanical shutter and the electronic shutter will be described. The electronic shutter is a shutter used in a digital camera that takes an image with an image sensor such as a CCD. In contrast, in a silver salt camera, a plate serving as a shutter is installed between a lens and a film, and exposure is performed by opening and closing the plate. A shutter using such a physical plate is referred to as a mechanical shutter (mechanical shutter).

  Since the electronic shutter controls the time for taking out an electric signal, the shutter speed can be made faster than the mechanical shutter with operation. Also, unlike a silver salt film, an image sensor does not take an image if it does not operate even if it is always exposed to light, so a physical plate is not necessary, and a digital camera does not have a mechanical shutter. can do.

  However, the electronic shutter in the CMOS image sensor is a rolling shutter due to its characteristics, and there is a problem that a subject with intense movement is distorted. A mechanical shutter is used to realize a global shutter operation that avoids this. Here, a description will be given of the image processing apparatus 10 that uses both such a mechanical shutter and an electronic shutter and mainly controls the electronic shutter.

  The image processing apparatus 10 shown in FIG. 3 includes a control unit 11, an image processing unit 12, a ROM (Read Only Memory) 13, an image sensor 14, and a mechanical shutter 15. The control unit 11 receives the release signal and transmits the start of the shutter operation to the image processing unit 12 by a signal 16 and controls the rear curtain operation to close the mechanical shutter 15 after a certain exposure time by the signal 18.

  The image processing unit 12 receives the shutter operation start signal 16, reads the timing information of the nonlinear shutter operation from the ROM 13, generates a timing pulse signal 17 of the nonlinear shutter operation, and transmits it to the image sensor 14. The image processing unit 12 also has a function of capturing and processing the imaging data 19 output from the image sensor 14. The image sensor 14 starts imaging by applying an electronic shutter based on the timing pulse signal 17, and outputs the captured data to the image processing unit 12. A detailed description of the nonlinear shutter operation will be described later.

  FIG. 4 is a diagram in which blocks related to the operation of a non-linear electronic shutter inside the image sensor 14 and control signals are extracted. In the image sensor 14 shown in FIG. 4, a configuration in which two, four, and eight rows can be simultaneously shuttered is shown. However, the number of rows of the simultaneous shutter is not limited to these numbers. . For example, the simultaneous shutter means that the two-line simultaneous shutter controls the electronic shutter that reads out two lines at the same time.

  The image sensor 14 illustrated in FIG. 4 includes a timing generation circuit 31, a V drive device 32, and a pixel array 33. The timing generation circuit 31 (TG = Timing Generator) counts the number of pulses of the timing pulse signal 17 and designates an address line for performing the operation of the electronic shutter by ADR <m: 0> according to the number of pulses.

  The timing generation circuit 31 has a function of outputting enable signals SHT2_EN, SHT4_EN, and SHT8_EN for realizing the simultaneous shutter operation. The V driving device 32 performs a shutter operation by driving the pixels in the row specified by the address information ADR <m: 0> instructed by the timing generation circuit 31 with the reset signal RST <n: 0>. Start pixel exposure. Further, the V driving device 32 is a mechanism capable of simultaneously resetting pixels of 2, 4, or 8 rows according to the values of the simultaneous shutter operation enable signals SHT2_EN, SHT4_EN, SHT8_EN so that the pixels can be reset simultaneously. It has.

  In the image sensor 14 having such a configuration, the timing generation circuit 31 obtains and counts timing pulses for driving the electronic shutter, and designates an address row for performing the electronic shutter operation based on the count value. (Address information ADR <m: 0> is generated. Then, the V driving device 32 generates a pixel reset signal, and based on the pixel reset signal, an electronic shutter is applied to the address row generated by the timing generation circuit 31. Drive.

  When the timing generation circuit 31 determines that the high-speed shutter operation has a short timing pulse interval, the timing generation circuit 31 designates a leading address row for performing the electronic shutter operation, and electronically operates a plurality of rows including the leading row. An instruction signal (simultaneous shutter operation enable signals SHT2_EN, SHT4_EN, SHT8_EN) for instructing the driving means to generate a pixel reset signal for operating the shutter is also generated, and the V driving device 32 corresponds to the instruction signal. Control is performed so that the number of rows is simultaneously shuttered.

  FIG. 5 is a part of the address decoder in the V drive device 32. Here, as an example, the word length of the address information is 12 bits (m = 12). The V drive device 32 is configured to supply the address signal ADR <11: 3> for the upper 9 bits of the input address as it is to the pixel array 33 and also to the pixel array 33 via the NOT circuit 52. It is said that.

  The V driving device 32 includes a decoding circuit for asserting RST <n: 0> at the address specified by the address signal ADR <m: 0>. The circuit size of each row becomes large. Accordingly, the address signal for the lower 3 bits is configured to include a predecoder 51 that decodes in advance and then distributes the decode signal DEC <7: 0> to each row.

  The pre-decoder 51 has the simultaneous shutter operation enable signals SHT2_EN, SHT4_EN, and SHT8_EN as inputs, and in accordance with the enable signal, it is in a state where multiple rows of DEC <7: 0> can be asserted simultaneously, and the address of the upper bit is designated Multiple reset signals are asserted simultaneously. By adding a function for realizing the simultaneous shutter to the predecoder 51, there is an effect that an increase in the circuit is extremely small.

  FIG. 6 is a detailed circuit diagram of the predecoder 51. The predecoder 51 outputs an 8-row simultaneous shutter portion 72, 4 rows to the output of the normal address decoding portion 71 that generates one asserted signal from the supplied lower 3-bit address signal ADR <2: 0>. The simultaneous shutter unit 73 and the two-row simultaneous shutter unit 74 are vertically connected. Here, the description is continued assuming that the circuits for controlling the 2-row, 4-row, and 8-row simultaneous shutters are vertically connected, but the circuits for controlling the 2N (N is an integer) row simultaneous shutter are vertically connected. The present invention can be applied even in the case of a configuration.

  The address decoder unit 71 includes NOT circuits 81 to 83 and AND circuits 84 to 91. The 8-row simultaneous shutter unit 72 includes OR circuits 111 to 117 and an AND circuit 118. The 4-row simultaneous shutter unit 73 includes OR circuits 131 to 136 and AND circuits 137 and 138. The two-row simultaneous shutter unit 74 includes OR circuits 151 to 154 and AND circuits 155 to 158.

  An address signal ADR <2: 0> is supplied to the address decoder unit 71 of the predecoder 51. Among them, the address signal ADR <2> is supplied to the NOT circuit 81, the address signal ADR <1> is supplied to the NOT circuit 82, and the address signal ADR <2> is supplied to the NOT circuit 83. The AND circuit 84 is supplied with the address signal ADR <2>, the address signal ADR <1>, and the address signal ADR <0> supplied to the predecoder 51 (the address signal ADR <2: 0> is supplied). ).

  The AND circuit 85 is supplied with the address signal ADR <2> and the address signal ADR <1> supplied to the predecoder 51, and is further supplied with an output from the NOT circuit 83. The AND circuit 86 is supplied with the address signal ADR <2> and the address signal ADR <0> supplied to the predecoder 51, and is further supplied with an output from the NOT circuit 82. The AND circuit 87 is supplied with the address signal ADR <2> supplied to the predecoder 51, and further supplied with outputs from the NOT circuit 82 and the NOT circuit 83, respectively.

  The AND circuit 88 is supplied with the address signal ADR <1> and the address signal ADR <0> supplied to the predecoder 51 and further supplied with an output from the NOT circuit 81. The AND circuit 89 is supplied with the address signal ADR <1> supplied to the predecoder 51 and further supplied with the outputs from the NOT circuit 81 and the NOT circuit 83. The AND circuit 90 is supplied with the address signal ADR <0> supplied to the predecoder 51, and further supplied with outputs from the NOT circuit 81 and the NOT circuit 82, respectively. Each output from the NOT circuit 81, the NOT circuit 82, and the NOT circuit 83 is supplied to the AND circuit 91.

  The output from the AND circuit 91 of the address decoder unit 71 and the 8-row simultaneous shutter enable signal SHT8_EN are supplied to the AND circuit 118 of the 8-row simultaneous shutter unit 72. The 8-row simultaneous shutter enable signal SHT8_EN is “1” when the 8-row simultaneous shutter is instructed (the signal when not instructing is “0”), and is a signal supplied from the timing generation circuit 31. The outputs from the AND circuit 118 are supplied to the OR circuits 111 to 117 constituting the 8-row simultaneous shutter unit 72, respectively.

  An output from the AND circuit 84 of the address decoder unit 71 is also supplied to the OR circuit 111, an output from the AND circuit 85 of the address decoder unit 71 is also supplied to the OR circuit 112, and an address decoder is supplied to the OR circuit 113. An output from the AND circuit 86 of the unit 71 is also supplied. The OR circuit 114 is also supplied with an output from the AND circuit 87 of the address decoder unit 71, the OR circuit 115 is also supplied with an output from the AND circuit 88 of the address decoder unit 71, and the OR circuit 116 has An output from the AND circuit 89 of the address decoder unit 71 is also supplied, and an output from the AND circuit 90 of the address decoder unit 71 is also supplied to the OR circuit 117.

  An output from the AND circuit 91 of the address decoder unit 71 and a 4-row simultaneous shutter enable signal SHT4_EN are supplied to the AND circuit 138 of the 4-row simultaneous shutter unit 73. The 4-row simultaneous shutter enable signal SHT4_EN is “1” when the 4-row simultaneous shutter is instructed (the signal when not instructing is “0”), and is a signal supplied from the timing generation circuit 31. The output from the AND circuit 138 is supplied to the OR circuits 134 to 136 constituting the 4-row simultaneous shutter unit 73, respectively.

  The output from the OR circuit 115 of the 8-row simultaneous shutter section 72 and the 4-row simultaneous shutter enable signal SHT4_EN are supplied to the AND circuit 137 of the 4-row simultaneous shutter section 73. The output from the AND circuit 137 is supplied to the OR circuits 131 to 133 constituting the 4-row simultaneous shutter unit 73, respectively.

  An output from the OR circuit 111 of the 8-row simultaneous shutter unit 72 is also supplied to the OR circuit 131, and an output from the OR circuit 112 of the 8-row simultaneous shutter unit 72 is also supplied to the OR circuit 133. The output from the OR circuit 113 of the 8-row simultaneous shutter section 72 is also supplied. The OR circuit 134 is also supplied with the output from the OR circuit 115 of the 8-row simultaneous shutter unit 72, and the OR circuit 135 is also supplied with the output from the OR circuit 116 of the 8-row simultaneous shutter unit 72. The output from the OR circuit 117 of the 8-row simultaneous shutter unit 72 is also supplied to 136.

  The AND circuit 158 of the two-row simultaneous shutter unit 74 is supplied with an output from the AND circuit 91 of the address decoder unit 71 and a two-row simultaneous shutter enable signal SHT2_EN. The two-row simultaneous shutter enable signal SHT2_EN is “1” when the two-row simultaneous shutter is instructed (the signal when not instructing is “0”) and is a signal supplied from the timing generation circuit 31. An output from the AND circuit 158 is supplied to an OR circuit 154 constituting the two-row simultaneous shutter unit 74. The OR circuit 154 is also supplied with an output from the OR circuit 136 of the 4-row simultaneous shutter unit 73. An output from the OR circuit 154 is output as a decode signal DEC <1>. The output from the AND circuit 91 of the address decoder unit 71 is output as a decode signal DEC <0>.

  The output from the OR circuit 135 of the 4-row simultaneous shutter unit 73 and the 2-row simultaneous shutter enable signal SHT2_EN are supplied to the AND circuit 157 of the 2-row simultaneous shutter unit 74. An output from the AND circuit 157 is supplied to an OR circuit 153 constituting the two-row simultaneous shutter unit 74. The output from the OR circuit 134 of the 4-row simultaneous shutter unit 73 is also supplied to the OR circuit 154. An output from the OR circuit 153 is output as a decode signal DEC <3>. The output from the OR circuit 135 of the 4-row simultaneous shutter unit 73 is output as a decode signal DEC <2>.

  The output from the OR circuit 114 of the 8-row simultaneous shutter section 72 and the 2-row simultaneous shutter enable signal SHT2_EN are supplied to the AND circuit 156 of the 2-row simultaneous shutter section 74. An output from the AND circuit 156 is supplied to an OR circuit 152 constituting the two-row simultaneous shutter unit 74. The output from the OR circuit 133 of the 4-row simultaneous shutter unit 73 is also supplied to the OR circuit 152. An output from the OR circuit 152 is output as a decode signal DEC <5>. The output from the OR circuit 114 of the 8-row simultaneous shutter unit 72 is output as a decode signal DEC <4>.

  The output from the OR circuit 132 of the 4-row simultaneous shutter unit 73 and the 2-row simultaneous shutter enable signal SHT2_EN are supplied to the AND circuit 155 of the 2-row simultaneous shutter unit 74. An output from the AND circuit 155 is supplied to an OR circuit 151 constituting the two-row simultaneous shutter unit 74. The output from the OR circuit 131 of the 4-row simultaneous shutter unit 73 is also supplied to the OR circuit 151. An output from the OR circuit 151 is output as a decode signal DEC <7>. The output from the OR circuit 132 of the 4-row simultaneous shutter unit 73 is output as a decode signal DEC <6>.

  In the predecoder 51 having such a configuration, when the 8-row simultaneous shutter enable signal SHT8_EN is “1”, the 8-row simultaneous shutter unit 72 enables the AND circuit 118 when the address of the first row is designated, The signal is input to each of the OR circuits 111 to 117 connected to the next and subsequent seven rows. Since each of the OR circuits 111 to 117 is asserted by a signal from the AND circuit 118, when the first row enters, the subsequent rows are asserted simultaneously. Thereby, an 8-row simultaneous shutter operation is realized.

  The 4-row simultaneous shutter section 73 and the 2-row simultaneous shutter section 74 are also configured as described above. Like the 8-row simultaneous shutter section 72, each of the OR circuits is all asserted by a signal from the AND circuit, When a row enters, the subsequent row is also asserted simultaneously. With such a configuration, a simultaneous shutter operation of 4 rows or 2 rows is realized.

  Tables 1 to 3 show the relationship between the address signal ADR <2: 0> as an input signal and the decode signal DEC <7: 0> as an output signal in the predecoder 51 having such a configuration. Table 1 shows that when the 8-row simultaneous shutter enable signal SHT8_EN is input to the 8-row simultaneous shutter unit 72, that is, when the 8-row simultaneous shutter is instructed, the address signal ADR <2: 0> is decoded. It is a table | surface which shows the relationship with signal DEC <7: 0>. At this time, the 4-row simultaneous shutter enable signal SHT4_EN and the 2-row simultaneous shutter enable signal SHT2_EN are both “0”.

  Table 2 shows the decoding of the address signal ADR <2: 0> when “1” is input to the 4-row simultaneous shutter unit 73 as the 4-row simultaneous shutter enable signal SHT4_EN, that is, when 4-row simultaneous shutter is instructed. It is a table | surface which shows the relationship with signal DEC <7: 0>. At this time, the 8-row simultaneous shutter enable signal SHT8_EN and the 2-row simultaneous shutter enable signal SHT2_EN are both “0”.

  Table 3 shows that the address signal ADR <2: 0> is decoded when “1” is input to the two-row simultaneous shutter unit 74 as the two-row simultaneous shutter enable signal SHT2_EN, that is, when the two-row simultaneous shutter is instructed. It is a table | surface which shows the relationship with signal DEC <7: 0>. At this time, the 8-row simultaneous shutter enable signal SHT8_EN and the 4-row simultaneous shutter enable signal SHT4_EN are both “0”.

  Here, with reference to FIG. 1 and FIG. 2 again, the operation of the shutter that can be realized by applying the present embodiment will be described. FIG. 1 is a diagram showing characteristics of the operation of each shutter when a conventional mechanical shutter and an electronic shutter are used. The mechanical shutter (front curtain) is physically accelerating because it is driven by a spring, and its operation is shown by a high-order curve as shown by a thin line in FIG. On the other hand, since the electronic shutter drives the shutter by sequentially specifying addresses (rolling shutter), its operation is linear as shown by a bold line in FIG.

  In the control of the exposure time using the mechanical shutter, the exposure time T0 is the same in every row because the characteristics of the front curtain and the rear curtain are the same. On the other hand, if the mechanical shutter of the front curtain is replaced with an electronic shutter, the exposure time T1 varies depending on the row due to the difference between the linear characteristics of the electrons and the higher-order characteristics of the rear curtain. The exposure time is preferably equal for each row. Therefore, in order to eliminate the difference in exposure time due to the use of the electronic shutter for the front curtain and the mechanical shutter for the rear curtain, the characteristics of the electronic shutter are combined with a plurality of linear characteristics, as shown by the bold lines in FIG. The exposure time can be made equal for each row by approximating the broken line to operate nonlinearly.

  Therefore, in the present embodiment, the electronic shutter is operated non-linearly by the image processing device 10, the image sensor 14, the V driving device 32, and the predecoder 51 having the above-described configuration.

  FIG. 7 is a timing chart for explaining the operation of the shutter in the image processing apparatus 10 shown in FIG. In other words, FIG. 7 is a timing chart for explaining the operation of the nonlinear shutter.

  The timing pulse signal 17 (FIG. 4) of the operation of the non-linear shutter is negated at the timing when the shutter is desired to be driven. FIG. 7A shows the drive timing pulse signal 17 of the electronic shutter. The difference between the pulse of the electronic shutter drive timing pulse signal 17 and the pulse interval T2 is controlled with different widths, thereby realizing a non-linear shutter operation.

  For example, when the pulse interval T2 is long as shown in FIG. 7B, every time a pulse is generated, the timing generation circuit 31 counts the pulse and sequentially increments ADR <m: 0>. Control is performed so that the interval between the pulses of the reset signals RST <i> and RST <i + 1> in the row and the (i + 1) -th row becomes the interval T2.

  As shown in FIG. 7C, as the pulse interval T2 of the timing pulse signal 17 becomes shorter, the interval between the reset signals RST <j> and RST <j + 1> in the j-th and j + 1-th rows also becomes shorter. Become. When the pulse interval T2 becomes shorter than the time required for the reset operation for one row, a high-speed shutter operation is supported by simultaneously resetting a plurality of rows.

  In the two-row simultaneous shutter mode shown in FIG. 7D, the timing generation circuit 31 designates an address of k = 2x (a multiple of 2), so that the V driving device 32 can perform the k-th and k + 1-th rows. Reset signals RST <k> and RST <k + 1> are asserted simultaneously. Similarly, in the 4-row simultaneous shutter mode shown in FIG. 7E, by specifying an address of l = 4y (a multiple of 4) from the timing generation circuit 31, the V driving device 32 is in the 1st row and the 1 + 1st row. , L + 2 line, l + 3 line reset signals RST <l>, RST <l + 1>, RST <l + 2>, RST <l + 3> are asserted at the same time to reset 4 lines simultaneously Call.

  Thus, by providing a multiple-row simultaneous shutter operation, a non-linear shutter operation approximating a polygonal line is realized. Such a nonlinear shutter operation can be realized by the image processing apparatus 10 having the above-described configuration.

[Non-linear shutter operation]
In order to realize such a nonlinear shutter operation, the timing generation circuit 31 needs to generate a timing pulse as described with reference to FIG. Here, generation of timing pulses performed by the timing generation circuit 31 will be described with reference to a flowchart of FIG.

  In step S11, the timing generation circuit 31 (FIG. 4) captures the timing pulse signal 17 supplied from the image processing unit 12 (FIG. 3). In step S12, it is determined whether or not the interval T2 is equal to or smaller than the interval T3 (whether or not the interval T2 <the interval T3).

  The interval T <b> 2 is the timing pulse signal 17 supplied from the image processing unit 12, and is an interval of pulses for driving the electronic shutter supplied from a portion external to the timing generation circuit 31. The interval T2 is stored in the ROM 13 (FIG. 3). In other words, the ROM 13 stores the characteristics of the mechanical shutter used as the rear curtain, for example, the characteristics shown by the thin lines in FIG. 1, and the following processing (control of the electronic shutter) is performed according to the characteristics. Done.

  The interval T3 is a minimum time required for the V driving device 32 to operate a one-row shutter (an electronic shutter that reads out one row at a time). If it is determined in step S12 that the interval T2 <the interval T3 is not satisfied, the process proceeds to step S13.

  In step S13, an address to start reading is designated. That is, the address signal ADR <11: 0> is supplied to the V driving device 32. When the address signal ADR <11: 0> is supplied, the V driving device 32 performs a shutter operation in step S14. The shutter operation executed in step S14 is a one-line simultaneous shutter operation. In the case of one-row simultaneous shutter, the two-row simultaneous shutter enable signal SHT2_EN, the four-row simultaneous shutter enable signal SHT4_EN, and the 8-row simultaneous shutter enable signal SHT8_EN are set to “0” and supplied to the V driving device 32. Is done.

  Such processing is repeated until it is determined in step S12 that the interval T2 <the interval T3. If it is determined in step S12 that the interval T2 <the interval T3, the process proceeds to step S15. In step S15, the mode is shifted to the two-line simultaneous shutter mode. By shifting to the two-row simultaneous shutter mode, the value of the two-row simultaneous shutter enable signal SHT2_EN is set to “1” and is supplied from the timing generation circuit 31 to the V driving device 32. At this time, the respective signals of the 4-row simultaneous shutter enable signal SHT4_EN and the 8-row simultaneous shutter enable signal SHT8_EN are set to “0” and supplied to the V driving device 32.

  When the mode is shifted to the two-line simultaneous shutter mode, in step S16, it is determined whether or not the interval T2 is equal to or smaller than the interval T4 (whether or not the interval T2 <the interval T4). The interval T4 is set to a half time of the interval T3. If it is determined in step S16 that the interval T2 <the interval T4 is not satisfied, the process proceeds to step S17.

  In step S17, an address for starting execution of the two-line simultaneous shutter is designated. That is, the address signal ADR <11: 0> is supplied to the V driving device 32. When the address signal ADR <11: 0> is supplied, the V driving device 32 executes a two-row simultaneous shutter operation in step S18. In step S19, the timing generation circuit 31 captures the timing pulse signal 17.

  Such processing is repeated until it is determined in step S16 that the interval T2 <the interval T4. If it is determined in step S16 that the interval T2 <the interval T4, the process proceeds to step S20. In step S20, the mode is shifted to the four-line simultaneous shutter mode. By shifting to the four-row simultaneous shutter mode, the value of the four-row simultaneous shutter enable signal SHT4_EN is set to “1” and supplied from the timing generation circuit 31 to the V driving device 32. At this time, the two-row simultaneous shutter enable signal SHT2_EN and the 8-row simultaneous shutter enable signal SHT8_EN are set to “0” and supplied to the V driving device 32.

  When the four-line simultaneous shutter mode is entered, in step S21, it is determined whether or not the interval T2 is equal to or smaller than the interval T5 (whether or not the interval T2 <the interval T5). The interval T5 is set to a half time of the interval T4. If it is determined in step S21 that the interval T2 <the interval T5 is not satisfied, the process proceeds to step S22.

  In step S22, an address for starting execution of the four-line simultaneous shutter is designated. That is, the address signal ADR <11: 0> is supplied to the V driving device 32. When the address signal ADR <11: 0> is supplied, the V drive device 32 performs a four-row simultaneous shutter operation in step S23. In step S24, the timing generation circuit 31 captures the timing pulse signal 17.

  Such processing is repeated until it is determined in step S21 that the interval T2 <the interval T5. If it is determined in step S21 that the interval T2 <the interval T5, the process proceeds to step S25. In step S25, the 8-line simultaneous shutter mode is entered. By shifting to the 8-row simultaneous shutter mode, the value of the 8-row simultaneous shutter enable signal SHT8_EN is set to “1” and supplied from the timing generation circuit 31 to the V driving device 32. At this time, the two-row simultaneous shutter enable signal SHT2_EN and the four-row simultaneous shutter enable signal SHT4_EN are set to “0” and supplied to the V driving device 32.

  When the mode is shifted to the 8-line simultaneous shutter mode, an address for starting execution of the 8-line simultaneous shutter is designated in step S26. That is, the address signal ADR <11: 0> is supplied to the V driving device 32. When the address signal ADR <11: 0> is supplied, the V drive device 32 performs a four-row simultaneous shutter operation in step S27. In step S28, it is determined whether all rows have been read. In step S28, the process returns to step S26 until it is determined that all the rows have been read, and the subsequent processes are repeated. On the other hand, if it is determined in step S29 that all rows have been read, the processing shown in FIG. 8 is terminated.

  In this embodiment, the case where the two-row simultaneous shutter mode, the four-row simultaneous shutter mode, and the eight-row simultaneous shutter mode are installed has been described as an example, so that the processing shown in FIG. 8 is performed. If the 16-line simultaneous shutter mode is also installed, for example, processing basically similar to the processing in steps S16 to S20 is further performed. That is, a process is performed in which the mode is changed according to the comparison with the interval T2 and the comparison result, or the start address is designated and the shutter is executed.

  That is, the present invention is not applied only to the case where the above-described two-row simultaneous shutter mode, four-row simultaneous shutter mode, and eight-row simultaneous shutter mode are installed, and it is assumed that another simultaneous shutter mode is provided. Can also be applied by executing basically the same processing as the processing described above. Further, when another simultaneous shutter mode is provided, the configuration of the predecoder 51 shown in FIG. 6 can be applied by reconfiguring it so as to correspond to another simultaneous shutter mode.

  As described above, the present invention has been described by taking the embodiment in which the 2, 4, 8 row simultaneous shutter mode is mounted as an example. However, if the number of simultaneous shutters is 2N, the simultaneous shutter mode is reduced in the same configuration. It can be expanded and non-linear shutter operation at any speed can be realized.

  As described above, according to the present invention, it is possible to cope with any shutter speed only by inserting a simple circuit in the address decoder of the V driving device. Since the address decoder can be realized by adding a circuit to the predecoder, an increase in circuit scale can be suppressed.

  It is also possible to approximate various quadratic curves of the mechanical shutter depending on the address drive timing from the set side.

[About recording media]
The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software is installed in the computer. Here, the computer includes, for example, a general-purpose personal computer capable of executing various functions by installing various programs by installing a computer incorporated in dedicated hardware.

  FIG. 9 is a block diagram illustrating a hardware configuration example of a computer that executes the above-described series of processing by a program. In a computer, a CPU (Central Processing Unit) 201, a ROM (Read Only Memory) 202, and a RAM (Random Access Memory) 203 are connected to each other via a bus 204. An input / output interface 205 is further connected to the bus 204. An input unit 206, an output unit 207, a storage unit 208, a communication unit 209, and a drive 210 are connected to the input / output interface 205.

  The input unit 206 includes a keyboard, a mouse, a microphone, and the like. The output unit 207 includes a display, a speaker, and the like. The storage unit 208 includes a hard disk, a nonvolatile memory, and the like. The communication unit 209 includes a network interface and the like. The drive 210 drives a removable medium 211 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory.

  In the computer configured as described above, the CPU 201 loads, for example, the program stored in the storage unit 208 to the RAM 203 via the input / output interface 205 and the bus 204 and executes the program, and the series described above. Is performed.

  The program executed by the computer (CPU 201) can be provided by being recorded in, for example, a removable medium 211 such as a package medium. The program can be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

  In the computer, the program can be installed in the storage unit 208 via the input / output interface 205 by attaching the removable medium 211 to the drive 210. The program can be received by the communication unit 209 via a wired or wireless transmission medium and installed in the storage unit 208. In addition, the program can be installed in advance in the ROM 202 or the storage unit 208.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

  DESCRIPTION OF SYMBOLS 10 Image processing apparatus, 11 Control part, 12 Image processing part, 13 ROM, 14 Image sensor, 15 Shutter, 31 Timing generation circuit, 32 V drive device, 33 Pixel array, 51 Predecoder

Claims (6)

Generating means for acquiring a timing pulse for driving the electronic shutter, counting, and generating a signal designating an address row for performing the electronic shutter operation according to a value of the count;
Driving means for generating a pixel reset signal and driving an electronic shutter for the address row generated by the generating means based on the pixel reset signal;
When determining that the high-speed shutter operation has a short interval between the timing pulses, the generating means designates a leading address row for performing the electronic shutter operation, and sets the electronic shutter to a plurality of rows including the leading row. An image processing apparatus for generating an instruction signal for instructing the driving means to generate a pixel reset signal for operation. The driving means includes a predecoder that decodes a predetermined number of lower bits of the address generated by the generating means,
The image processing apparatus according to claim 1, wherein the instruction signal generated by the generation unit is supplied to the predecoder. A storage means for storing characteristics of a mechanical shutter used as the rear curtain;
The image processing apparatus according to claim 1, wherein the generation unit generates the instruction signal for generating the pixel reset signal that matches the characteristics stored in the storage unit. The plurality of rows are 2N rows;
The image processing apparatus according to claim 2, wherein the predecoder is configured such that a circuit that controls a 2N-line simultaneous shutter is vertically connected. In an image processing method of an image processing apparatus including an electronic shutter,
A timing pulse for driving the electronic shutter is acquired, counted, and a signal for designating an address row for performing the electronic shutter operation is generated according to the value of the count,
Generating a pixel reset signal, and driving an electronic shutter for the address row generated by the generating means based on the pixel reset signal;
In the case of a high-speed shutter operation in which the timing pulse interval is short, a top address row for performing the electronic shutter operation is designated, and a pixel reset signal for operating the electronic shutter for a plurality of rows including the top row is provided. Generated image processing method. In a computer-readable program for controlling an image processing apparatus including an electronic shutter,
A timing pulse for driving the electronic shutter is acquired, counted, and a signal for designating an address row for performing the electronic shutter operation is generated according to the value of the count,
Generating a pixel reset signal, and driving an electronic shutter for the address row generated by the generating means based on the pixel reset signal;
In the case of a high-speed shutter operation in which the timing pulse interval is short, a top address row for performing the electronic shutter operation is designated, and a pixel reset signal for operating the electronic shutter for a plurality of rows including the top row is provided. Occurs A computer-readable program that performs the processing that occurs.

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