KR20130065478A - The light emitting device package and the method for manufacturing the same - Google Patents

The light emitting device package and the method for manufacturing the same Download PDF

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Publication number
KR20130065478A
KR20130065478A KR1020110132357A KR20110132357A KR20130065478A KR 20130065478 A KR20130065478 A KR 20130065478A KR 1020110132357 A KR1020110132357 A KR 1020110132357A KR 20110132357 A KR20110132357 A KR 20110132357A KR 20130065478 A KR20130065478 A KR 20130065478A
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KR
South Korea
Prior art keywords
light emitting
semiconductor layer
device package
pad
layer
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KR1020110132357A
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Korean (ko)
Inventor
배석훈
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엘지이노텍 주식회사
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Priority to KR1020110132357A priority Critical patent/KR20130065478A/en
Publication of KR20130065478A publication Critical patent/KR20130065478A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

The present invention relates to a light emitting device package, the package includes a light emitting structure, a device pad on a lower surface of the light emitting structure, a metal protrusion on the device pad, the device pad, and has a top surface higher than the top surface of the metal protrusion, The present invention provides a light emitting device package including an insulating substrate including a via hole exposing an upper surface of the metal protrusion, and a substrate pad formed on the exposed upper surface of the metal protrusion. Therefore, a metal protrusion may be formed, and a substrate may be formed without variation in thickness by exposing an upper surface of the metal protrusion through laser drilling.

Description

The light emitting device package and the method for manufacturing the same

The present invention relates to a light emitting device package and a method of manufacturing the same.

A light emitting diode (LED) may form a light emitting source using compound semiconductor materials such as GaAs series, AlGaAs series, GaN series, InGaN series, and InGaAlP series.

Such a light emitting diode is packaged and used as a light emitting device that emits a variety of colors, and the light emitting device is used as a light source in various fields such as a lighting indicator for displaying a color, a character display, and an image display.

1 is a cross-sectional view of a conventional light emitting device package.

Referring to FIG. 1, in the conventional light emitting device package 10, a pad 3 is formed on a light emitting structure 2, and a pad 6 of a printed circuit board is formed using a metal ball 4 on the pad 3. Electrically bond with.

In this case, an insulating material 5 is embedded between the light emitting structure and the pads 3 and 6 of the printed circuit board to form a supporting member.

In the light emitting device package of FIG. 1, when the pad 6 is formed on the insulating material 5, the pad 6 may be formed by printing or sputtering using a conductive paste.

However, when printing, the pad 6 adhesion may be a problem, and when sputtering, the cost is high and the process time becomes long.

The embodiment provides a light emitting device package having a new structure and a method of manufacturing the same.

The embodiment may include a light emitting structure, a via pad exposing a device pad on the bottom surface of the light emitting structure, a metal protrusion on the device pad, the device pad, and having a top surface higher than the top surface of the metal protrusion and exposing the top surface of the metal protrusion. Provided is a light emitting device package including an insulating substrate including and a substrate pad formed on an exposed upper surface of the metal protrusion.

On the other hand, the embodiment is a step of forming a light emitting structure having an active layer between the first and second conductivity-type semiconductor layer on the substrate, forming a device pad on the light emitting structure, applying a solder paste on the device pad and metal projections Soldering a metal layer; applying an insulating material to the light emitting structure to cover the metal protrusion; forming an insulating layer; forming a via hole in the insulating layer to expose an upper surface of the metal protrusion; and exposing the metal. It provides a method of manufacturing a light emitting device package comprising forming a substrate pad on the upper surface of the projection.

According to the present invention, the pad may be formed on the light emitting structure, the metal protrusion may be formed on the pad, and the substrate may be formed without variation in thickness by exposing the upper surface of the metal protrusion through laser drilling. In addition, the degree of freedom can be increased by processing to a desired depth, and the cost can be reduced by electroless plating or OSP treatment on the exposed upper surface of the metal protrusion to form a pad.

1 is a cross-sectional view of a conventional light emitting device package.
2 is a cross-sectional view of a light emitting device package according to the present invention.
3 to 9 are process diagrams for describing a method of manufacturing the light emitting device package illustrated in FIG. 2.
10 is a cross-sectional view of a light emitting device package according to another embodiment of the present invention.
11 is a cross-sectional view of a light emitting device package according to an application example of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Hereinafter, a light emitting device package 100 according to the present invention will be described with reference to FIG. 2.

Referring to FIG. 2, the light emitting device package 100 includes a light emitting structure 50 and a printed circuit board electrically connected to the light emitting structure 50 under the light emitting structure 50.

The light emitting structure 50 is flip chip bonded to the printed circuit board and is disposed in a top-view manner to emit light upward.

The light emitting structure 50 has a layered structure of the first conductive semiconductor layer 120, the active layer 130, and the second conductive semiconductor layer 140, and the first conductive semiconductor layer 120 is disposed thereon. do.

The lower second conductive semiconductor layer 140 may be formed of at least one of a group III-V compound semiconductor, for example, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, or AlInN. The second conductive semiconductor layer 140 may be doped with a second conductive dopant, and the second conductive dopant is a p-type dopant and includes Mg, Zn, Ca, Sr, and Ba.

 The second conductive semiconductor layer 140 may be formed of a p-type GaN layer having a predetermined thickness by supplying a gas including a p-type dopant such as NH 3, TMGa (or TEGa), and Mg.

 The second conductive semiconductor layer 140 includes a current spreading structure in a predetermined region. The current spreading structure includes semiconductor layers in which the current spreading speed in the horizontal direction is higher than the current spreading speed in the vertical direction.

The second conductivity-type semiconductor layer 140 may supply a carrier diffused in a uniform distribution to another layer, for example, the active layer 130 thereon.

 The active layer 130 is formed on the second conductive semiconductor layer 140. The active layer 130 may be formed in a single quantum well or multiple quantum well (MQW) structure. One period of the active layer 130 may optionally include a period of InGaN / GaN, a period of AlGaN / InGaN, a period of InGaN / InGaN, or a period of AlGaN / GaN.

 A second conductive cladding layer (not shown) may be formed between the second conductive semiconductor layer 140 and the active layer 130. The second conductive cladding layer may be formed of a p-type GaN-based semiconductor. The second conductivity type clad layer may be formed of a material having a band gap higher than that of the well layer.

 The first conductivity type semiconductor layer 120 is formed on the active layer 130. The first conductive semiconductor layer 120 may be implemented as an n-type semiconductor layer doped with a first conductive dopant. The n-type semiconductor layer may be formed of any one of compound semiconductors such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, and the like. The first conductivity type dopant is an n-type dopant, and at least one of Si, Ge, Sn, Se, Te, and the like may be added.

 The first conductive semiconductor layer 120 may supply a gas including an n-type dopant such as NH 3, TMGa (or TEGa), and Si to form an n-type GaN layer having a predetermined thickness.

In addition, the second conductivity-type semiconductor layer 140 may be implemented as a p-type semiconductor layer, and the first conductivity-type semiconductor layer 120 may be implemented as an n-type semiconductor layer. The light emitting structure 50 may be implemented as any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure. Hereinafter, for the purpose of description, the first conductive semiconductor layer will be described as an example of the uppermost layer of the semiconductor layer.

Meanwhile, a step in which a portion of the first conductive semiconductor layer 120 is exposed by etching a region from the surface of the second conductive semiconductor layer 140 is formed under the light emitting structure 50. Accordingly, the lower portion of the light emitting structure 50 includes a first upper surface through which the second conductive semiconductor layer 140 is exposed and a second upper surface through which the first conductive semiconductor layer 120 is exposed.

The device pad 160 is formed on the first upper surface of the second conductive semiconductor layer 140 and the second upper surface of the first conductive semiconductor layer 120.

The device pad 160 may be formed of a single layer, but may have a plurality of layered structures as shown in FIG. 2.

When the device pad 160 has a plurality of layered structures, first to third layers 161 to 163 may have a pattern having the same area from the surfaces of the semiconductor layers 120 and 140.

The first layer 161 formed on the first and second upper surfaces of the semiconductor layers 120 and 140 of the device pad 160 may be an alloy layer including titanium, and is formed on the first layer 161. The second layer 162 may be an alloy layer including copper, and the third layer 163 formed on the second layer 162 may be a nickel layer including nickel.

In this case, the heights of the device pads 160 on the first conductive semiconductor layer 120 and the device pads 160 on the second conductive semiconductor layer 140 may be different from each other.

That is, in order to compensate for the height difference between the first and second conductivity-type semiconductor layers 120 and 140, the first to the second pads forming the device pads 160 on the first conductivity-type semiconductor layer 120. The thickness of the three layers 161-163 may be greater than the first to third layers 161-163 of the device pad 160 on the second conductive semiconductor layer 140.

Preferably, the device pad 160 on the second conductivity-type semiconductor layer 140 is about 100 μm of a titanium alloy as the first layer 161, about 500 μm of a copper alloy as the second layer 162, and a third layer ( The nickel alloy 163 may be formed to have a thickness of about 100 μm, and the device pad 160 on the first conductive semiconductor layer 120 may be formed thicker than this.

The solder paste 181 is formed on the device pad 160, and the metal protrusions 180 are formed on the solder paste 181.

The solder paste 181 may be a gold-tin alloy.

Final heights of the metal protrusions 180 on the first conductive semiconductor layer 120 and the second conductive semiconductor layer 140 are the same.

The metal protrusion 180 is formed of an alloy including a metal having electrical conductivity, high thermal conductivity, high melting point, and low thermal expansion coefficient.

Preferably, the metal protrusions 180 are formed of copper or an alloy including copper, and the metal protrusions 180 may be spherical metal balls.

 An insulating layer 185 is formed to expose the top surface of the metal protrusion 180 and cover the lower portion of the light emitting structure 50.

The insulating layer 185 may include an epoxy-based insulating resin. Alternatively, the insulating layer 185 may include a polyimide-based resin.

The upper surface of the insulating layer 185 is formed higher than the upper surface of the metal protrusion 180, and the insulating layer 185 includes a via hole 186 that opens the upper surface of the metal protrusion 180.

The via hole 186 may have an inclination at a side surface as shown in FIG. 2, and may be different from each other.

An upper surface of the metal protrusion 180 exposed by the via hole 186 may be 1/2 or less of a total thickness.

A substrate pad 182 is formed on an upper surface of the metal protrusion 180 exposed to the insulating layer 185.

The substrate pad 182 may be formed of a plating layer, and the plating layer may be formed of an alloy including copper, titanium, nickel, or palladium. Alternatively, the substrate pad 182 may be formed by processing organic solderability preservatives (OSP).

A protective layer may be further formed on the upper portion of the light emitting device package 100 of FIG. 2 and on the light emitting surface of the light emitting structure 50, and the protective layer may be formed of a light-transmitting insulating layer.

As such, when the mounting printed circuit board is formed after the light emitting device is formed, an insulating layer having a via hole 186 forming a metal protrusion 180 on the light emitting device and opening the metal protrusion 180 ( After forming 185, the pad may be formed by plating or OSP treatment on the upper surface of the metal protrusion 180 to reduce costs.

Hereinafter, a method of manufacturing the light emitting device package 100 of FIG. 2 will be described with reference to FIGS. 3 to 9.

First, as shown in FIG. 3, the light emitting structure 50 is formed on the substrate 110.

The substrate 110 may use at least one of sapphire (Al 2 O 3 ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge, preferably a sapphire substrate 110. .

The first conductivity type semiconductor layer 120 may be formed on the substrate 110.

The first conductive semiconductor layer 120 may be formed in a multi-layered structure, and an undoped semiconductor layer (such as undoped GaN) is formed on the lower layer, and the first conductive semiconductor layer 120 is formed on the upper layer. Can be.

The first conductivity type semiconductor material having a composition formula of the semiconductor layer 120 is In x Al y Ga 1 -x- y N (0≤x≤1, 0 ≤y≤1, 0≤x + y≤1), For example, it may include at least one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN.

In addition, when the first conductivity-type semiconductor layer 120 is an n-type semiconductor layer, the first conductivity-type semiconductor layers 120 and 130 are doped with n-type dopants such as Si, Ge, Sn, Se, and Te. Can be.

The active layer 130 is formed on the first conductive semiconductor layer 120, and the active layer 130 has a single quantum well structure, a multi quantum well structure (MQW), and a quantum wire (Quantum-Wire). It may be formed of at least one of the structure, or the quantum dot (Quantum Dot) structure.

A clad layer (not shown) doped with an n-type or p-type dopant may be formed on and / or under the active layer 130, and the clad layer (not shown) may be implemented as an AlGaN layer or an InAlGaN layer. have.

The second conductivity type semiconductor layer 140 is formed on the active layer 130. The second conductivity-type semiconductor layer 140 may be implemented, for example, as a p-type semiconductor layer, wherein the p-type semiconductor layer is In x Al y Ga 1 -x- y N (0≤x≤1, 0 Semiconductor material having a composition formula of? P-type dopants such as Ba may be doped.

Meanwhile, p-type and n-type dopants may be doped into the first conductivity-type semiconductor layer 120 and the second conductivity-type semiconductor layer 140, but embodiments are not limited thereto. Although not shown, a third conductive semiconductor layer (not shown) may be formed on the second conductive semiconductor layer 140. Therefore, the light emitting structure may be formed of any one of pn, np, pnp, and npn junction structures.

The first conductive semiconductor layer 120, the active layer 130, and the second conductive semiconductor layer 140 may be formed of metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), or the like.

Next, as shown in FIG. 3, the first conductive semiconductor layer 120 is etched to a part of the height of the first conductive semiconductor layer 120 to expose the first conductive semiconductor layer 120.

Accordingly, the light emitting structure 50 on the substrate 110 may be formed of the first conductive semiconductor layer 120 having a step from the first upper surface and the first upper surface formed of the second conductive semiconductor layer 140. It has two top faces.

Next, as shown in FIG. 4, the device pads 160 are formed on the first and second surfaces, respectively.

The device pad 160 may be formed to have a plurality of layered structures, and may be formed of a titanium alloy, a copper alloy, or a nickel alloy of the first to third layers 161 to 163.

In this case, the device pad 160 on the second conductivity-type semiconductor layer 140 is 100 μm of a titanium alloy, which is the first layer 161, and a copper alloy of 500 μm, and the third layer 163, of the second layer 162. The nickel alloy may be formed to have a thickness of 100 μm, and the device pad 160 on the first conductive semiconductor layer 120 may be formed thicker than this.

The device pad 160 may be formed to cover most regions of the first upper surface and the second upper surface, and as shown in FIG. 5, one side of the second conductive semiconductor layer 140 may be etched to form a second upper surface. In this case, the device pads 160 of the first upper surface and the device pads 160 of the second upper surface may have the same length and have different widths.

The device pad 160 may be formed by plating, but may also be formed by sputtering or the like.

Next, as shown in FIG. 6, a solder paste 181 may be formed on a portion of the device pad 160, preferably in a region opposite to each other.

For example, when the device pad 160 is rectangular, the solder paste 181 of the first upper surface may be formed on the horizontal side of one side, and the solder paste 181 of the second upper surface may be formed on the horizontal side of the other side. .

When the two solder pastes 181 are formed to be spaced apart as described above, the metals may be prevented from contacting and shorting while flowing by the soldering.

In this case, the solder paste 181 may be a copper-silver-tin alloy.

The solder paste 181 is applied, the conductive metal protrusions 180 are formed, and heat is applied to the metal protrusions 180 and the device pads 160.

Next, as shown in FIG. 7, the insulating layer 185 is formed on the first and second upper surfaces of the light emitting structure 50 to cover the upper surface of the metal protrusion 180.

The insulating layer 185 may be an epoxy resin or an imide resin to function as a supporting substrate of a printed circuit board, and may be glass impregnated or filler impregnated resin.

The insulating material is coated on the light emitting structure 50 and then cured. The cured insulating layer 185 is formed to have a thickness covering the metal protrusion 180 to a predetermined height.

Next, as shown in FIG. 8, a via hole 186 is formed on the top surface of the insulating layer 185 to expose the top surface of the metal protrusion 180.

The via hole 186 may be formed by performing laser drilling, and the via hole 186 may be formed to expose 1/2 or less with respect to the height of the metal protrusion 180.

The via hole 186 may have an inclination at a side surface as shown in FIG. 2, and may be different from each other.

Next, after forming the plating layer by electroless plating on the exposed upper surface of the metal protrusion 180 as shown in FIG. 9, the substrate pad 182 is formed by etching so that only the plating layer on the metal protrusion 180 remains. .

The substrate pad 182 may be formed of an alloy including copper, nickel, palladium, or titanium.

However, the substrate pad 182 may be formed by selectively electroplating only on the upper surface of the metal protrusion 180.

Finally, the substrate 110 is removed so that the first conductive semiconductor layer 120 of the light emitting structure 50 is exposed, and the first conductive semiconductor layer 120 serving as the light emitting surface is disposed to face the upper surface. The light emitting device package 100 of FIG. 2 may be completed.

In this case, a protective layer may be further formed on the light emitting structure 50 of the second light emitting device package 100.

In the above description, the substrate pad 182 is formed using a metal. Alternatively, the substrate pad 182 may be formed by OSP treatment.

Hereinafter, another embodiment of the present invention will be described with reference to FIGS. 10 and 11.

10 and 11, the light emitting device packages 100A and 100B have a light emitting structure 50 and a printed circuit board electrically connected to the light emitting structure 50 under the light emitting structure 50.

The light emitting structure 50 is flip chip bonded to the printed circuit board and is disposed in a top-view manner to emit light upward.

The light emitting structure 50 has a layered structure of the first conductive semiconductor layer 120, the active layer 130, and the second conductive semiconductor layer 140, and the first conductive semiconductor layer 120 is disposed thereon. do.

Since the light emitting structure 50 is the same as FIG. 2, a description thereof will be omitted.

A step is formed in the lower portion of the light emitting structure 50 to expose the first conductive semiconductor layer 120 by etching a partial region from the surface of the second conductive semiconductor layer 140. Accordingly, the lower portion of the light emitting structure 50 includes a first upper surface through which the second conductive semiconductor layer 140 is exposed and a second upper surface through which the first conductive semiconductor layer 120 is exposed.

The device pad 160 is formed on the first upper surface of the second conductive semiconductor layer 140 and the second upper surface of the first conductive semiconductor layer 120.

In this case, the heights of the device pads 160 on the first conductive semiconductor layer 120 and the device pads 160 on the second conductive semiconductor layer 140 may be different from each other.

That is, in order to compensate for the height difference between the first and second conductivity-type semiconductor layers 120 and 140, the first to the second pads forming the device pads 160 on the first conductivity-type semiconductor layer 120. The thickness of the three layers 161-163 may be greater than the first to third layers 161-163 of the device pad 160 on the second conductive semiconductor layer 140.

Solder paste 181 is formed on the device pad 160, and metal protrusions 180A are formed on the solder paste 181.

The solder paste 181 may be a copper-silver-tin alloy.

The final heights of the metal protrusions 180A on the first conductive semiconductor layer 120 and the second conductive semiconductor layer 140 are the same.

The metal protrusion 180A is formed of an alloy including a metal having electrical conductivity, high thermal conductivity, high melting point, and low thermal expansion coefficient.

Preferably, the metal protrusions 180A may be formed of copper or an alloy including copper, and the metal protrusions 180A may have a columnar shape and may have a polygonal or circular cross section.

 An insulating layer 185 is formed to expose the top surface of the metal protrusion 180A and cover the lower portion of the light emitting structure 50.

The insulating layer 185 may include an epoxy-based insulating resin. Alternatively, the insulating layer 185 may include a polyimide-based resin.

The upper surface of the insulating layer 185 is formed higher than the upper surface of the metal protrusion 180, and the insulating layer 185 includes a via hole 186 that opens the upper surface of the metal protrusion 180.

The via hole 186 may have an inclination at a side surface as shown in FIG. 10, and may be perpendicular to the via hole 186.

An upper surface of the metal protrusion 180 exposed by the via hole 186 may be 1/2 or less of a total thickness.

A substrate pad 182A is formed on an upper surface of the metal protrusion 180 exposed to the insulating layer 185.

The substrate pad 182A may be formed of a plating layer, and the plating layer may be formed of an alloy including copper, titanium, nickel, or palladium. Alternatively, the substrate pad 182 may be formed by processing organic solderability preservatives (OSP).

A protective layer may be further formed on the light emitting device package 100A of FIG. 10 and on the light emitting surface of the light emitting structure 50, and the protective layer may be formed of a light-transmitting insulating layer.

Meanwhile, when the substrate pad 182A of FIG. 10 is formed by OSP processing, the solder ball 190 may be formed and packaged on the substrate pad 182A as in the light emitting device package 100B of FIG. 11.

The solder ball 190 may be an alloy of tin-silver-copper, and the bonding force with the substrate pad 182A formed by OSP treatment is enhanced to improve adhesion of the packaging.

In the above description, the thicknesses of the device pads 160 are different from each other to compensate for the difference in thickness between the first and second upper surfaces of the light emitting device packages 100, 100A, and 100B of FIGS. 2, 10, and 11. Alternatively, a conductive step portion for compensating for the thickness difference may be further formed, and the thicknesses of the device pads 160 of the first and second upper surfaces may be the same.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Light emitting device package 100, 100A, 100B
Element pads 160
Metal projection 180, 180A
Light-emitting structure 50
Board Pad 182, 182A

Claims (16)

Light emitting structure,
An element pad on a bottom surface of the light emitting structure,
A metal protrusion on the device pad,
An insulating substrate covering the device pad and having a top surface higher than the top surface of the metal protrusion and including a via hole exposing the top surface of the metal protrusion;
A substrate pad formed on the exposed upper surface of the metal protrusion
Light emitting device package comprising a. The method of claim 1,
The light emitting structure
A first conductivity type semiconductor layer on an upper surface of the light emitting structure,
A second conductive semiconductor layer on a lower surface of the light emitting structure, and
An active layer between the first and second conductivity-type semiconductor layers
Light emitting device package. The method of claim 2,
The lower surface of the light emitting structure
A first surface to which the second conductive semiconductor layer is exposed, and
A light emitting device package having a second surface exposing the first conductive semiconductor layer. The method of claim 3,
The device pads are formed on the first surface and the second surface, respectively. The method of claim 1,
The substrate pad is a light emitting device package formed of an alloy containing copper, nickel, palladium or titanium. The method of claim 1,
The metal protrusion is a light emitting device package is formed by the OSP process. The method of claim 1,
The via hole is a light emitting device package that exposes less than 1/2 of the thickness of the metal projection. The method of claim 1,
The metal protrusion is a light emitting device package having a columnar or spherical shape. Forming a light emitting structure having an active layer between the first and second conductivity-type semiconductor layers on the substrate,
Forming a device pad on the light emitting structure,
Applying solder paste on the device pads and soldering metal projections;
Forming an insulating layer by coating an insulating material on the light emitting structure to cover the metal protrusions;
Forming a via hole in the insulating layer to expose a top surface of the metal protrusion, and
Forming a substrate pad on an exposed upper surface of the metal protrusion;
Method of manufacturing a light emitting device package comprising a. 10. The method of claim 9,
Forming the light emitting structure,
And etching the portion of the second conductive semiconductor layer to expose the first conductive semiconductor layer. The method of claim 10,
And manufacturing the device pads on the second conductive semiconductor layer and the first conductive semiconductor layer, respectively. 10. The method of claim 9,
Forming the via hole
A method of manufacturing a light emitting device package performing laser drilling to expose an upper surface of the metal protrusion. 10. The method of claim 9,
Forming the via hole
Method of manufacturing a light emitting device package to expose 1/2 or less with respect to the thickness of the metal projections. 10. The method of claim 9,
Forming the substrate pad,
Electroless plating on the insulating layer to form a plating layer,
And etching the plating layer to selectively form the substrate pad only on an upper surface of the metal protrusion. 10. The method of claim 9,
Forming the substrate pad,
Method of manufacturing a light emitting device package to form the substrate pad by OSP treatment on the exposed upper surface of the metal projection. 16. The method of claim 15,
The method of manufacturing a light emitting device package further comprises attaching a solder ball on the OSP treated substrate pad.
KR1020110132357A 2011-12-09 2011-12-09 The light emitting device package and the method for manufacturing the same KR20130065478A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11355467B2 (en) 2020-01-15 2022-06-07 Samsung Electronics Co., Ltd. Semiconductor devices including thick pad

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11355467B2 (en) 2020-01-15 2022-06-07 Samsung Electronics Co., Ltd. Semiconductor devices including thick pad
US11652076B2 (en) 2020-01-15 2023-05-16 Samsung Electronics Co., Ltd. Semiconductor devices including thick pad

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