KR20130054772A - Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for an FFS(Fringe Field Switch) type LCD(Liquid Crystal Display) device is provided to improve an opening rate without forming a black matrix on a color filter substrate. CONSTITUTION: A color filter layer(117) is formed on a pixel area by crossing a gate line and a data line(113a). An organic insulation layer includes an opening unit which exposes a TFT(Thin Film Transistor). A pixel electrode(125a) is directly connected to the TFT through the opening unit. A passivation layer(131) is formed on the organic insulation layer including the pixel electrode. A plurality of common electrodes(137a) is formed on the passivation layer and is overlapped with the pixel electrode.

Description

TECHNICAL FIELD [0001] The present invention relates to an array substrate for an FFE-type liquid crystal display device and a method of manufacturing the array substrate.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an FFS (Fringe Field Switching) type liquid crystal display device and a method of manufacturing the same.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and moving picture performance, It is attracting attention.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field in which the common electrode and the pixel electrode are arranged in an up-down direction, and the characteristics such as transmittance and aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent. Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

The transverse type liquid crystal display device includes a color filter substrate and an array substrate facing each other, and a liquid crystal layer is interposed between the color filter substrate and the array substrate.

The array substrate includes a thin film transistor, a common electrode, and a pixel electrode for each of a plurality of pixels defined in a transparent insulating substrate.

In addition, the common electrode and the pixel electrode are configured to be spaced apart from each other in parallel on the same substrate.

In the color filter substrate, a black matrix is formed at a portion corresponding to a gate wiring, a data wiring, and a thin film transistor on a transparent insulating substrate, and a color filter is formed corresponding to the pixel.

Further, the liquid crystal layer is driven by the horizontal electric field of the common electrode and the pixel electrode.

In this case, the common electrode and the pixel electrode are typically formed of transparent electrodes in order to secure luminance.

Therefore, the proposed technique to maximize the effect of improving the brightness is the FFS (Fringe Field Switching) technology. The FFS technology has a characteristic that high contrast ratio can be obtained without color shift by precisely controlling the liquid crystal.

A method of manufacturing a FFS (Fringe Field Switching) type liquid crystal display device according to the related art will be described with reference to FIGS. 1 to 3.

1 is a schematic plan view of a FFS (Fringe Field Switching) type liquid crystal display device according to the prior art.

FIG. 2 is an enlarged plan view of a periphery of a thin film transistor in a conventional FFS (Fringe Field Switching) type liquid crystal display device.

FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1 and is a schematic cross-sectional view of a FFS (Fringe Field Switching) type liquid crystal display device.

As shown in FIGS. 1 to 3, a plurality of gates extending in one direction on the transparent insulating substrate 11 and spaced in parallel to each other are shown in FIG. 1 to FIG. 3. Wiring 13; A plurality of data wires 21 intersecting the gate wires 13 and defining pixel regions in the intersecting areas; A gate electrode 13a, a gate insulating film 15, an active layer 17, and a source electrode provided at an intersection point of the gate wiring 13 and the data wiring 21 and extending perpendicularly from the gate wiring 13. A thin film transistor (T) consisting of a 23 and a drain electrode 25; A first passivation film 29 formed on the entire surface of the substrate including the thin film transistor T; A large area common electrode 33 formed on the first passivation film 29; A second passivation film (35) formed on the first passivation film (29) including the common electrode (33) and exposing the drain electrode (25); The plurality of pixel electrodes 37 are formed on the passivation layer 35 to be spaced apart from each other and electrically connected to the drain electrode 25.

Here, a large area common electrode 33 is disposed in the pixel region where the gate wiring 13 and the data wiring 21 cross each other. In this case, the common electrode 33 is formed in an area excluding the upper portion of the thin film transistor T provided at the intersection of the gate line 13 and the data line 21.

In addition, the pixel electrode 37 overlaps the common electrode 33 with the second passivation layer 35 therebetween. In this case, the common electrode 33 and the plurality of pixel electrodes 37 are formed of indium tin oxide (ITO), which is a transparent conductive material.

The pixel electrode 37 is electrically connected to the drain electrode 25 through the drain contact holes 31 formed on the first and second passivation layers 29 and 35.

In addition, as shown in FIG. 3, the color filter layer 45 and the color filter layer 45 may be disposed on the color filter substrate 41 spaced apart and bonded to the insulating substrate 11 on which the common electrode 33 and the plurality of pixel electrodes 37 are formed. Black matrices 43 are disposed between the color filter layers 45 to block light transmission, and the black matrices 43 and the color filter layers 45 are disposed on the black matrices 43 and the color filter layers 45. An overcoat layer 47 is formed to achieve planarization between the layers. In this case, the black matrix 43 is formed on the color filter substrate 41 corresponding to the portion of the drain contact hole 31 including the gate wiring 13 and the data wiring 21.

A liquid crystal layer 51 is formed between the color filter substrate 41 and the insulating substrate 11 which are bonded to each other.

As described above, according to the FSF type liquid crystal display device according to the prior art, a drain contact hole must be formed in order to connect the pixel electrode and the drain electrode of the thin film transistor to the passivation film, and at the time of forming the drain contact hole, Light leakage occurs due to the occurrence of liquid crystal disclination areas around the contact hole.

Therefore, in order to block the light leakage caused by the liquid crystal disclination region around the drain contact hole, it is necessary to cover the entire area around the drain contact hole using the black matrix BM. As the area of the opening area, that is, the transmissive area is reduced, the transmittance of the pixel is reduced. In particular, in order to block light leakage caused by the declining region of the liquid crystal generated by the drain contact hole, the black matrix BM must be masked in consideration of the bonding margin, so that the transmittance region of the pixel is reduced accordingly. Will fall.

In addition, according to the FSF type liquid crystal display device according to the prior art, the number of manufacturing processes is increased because an overcoat layer must be formed in order to achieve flattening between the black matrix and the color filter layer.

In addition, according to the FSF type liquid crystal display device according to the related art, an amorphous silicon layer (n + or p +) and an amorphous silicon layer (a-Si) containing a conductive layer forming a source electrode and a drain electrode and impurities formed thereunder : H) is not patterned at the same time, so there is a risk of active tails.

Accordingly, an object of the present invention is to improve the above problems, and an object of the present invention is to form a drain contact hole in order to connect a drain electrode and a pixel electrode in a Fringe Field Switching (FFS) type liquid crystal display device. The present invention provides a Fringe Field Switching (FFS) type liquid crystal display device and a method of manufacturing the same, which can maximize the opening area of a pixel to increase transmittance.

According to an aspect of the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device includes: a gate wiring formed on one surface of a substrate in one direction; A data line crossing the gate line to define a pixel area; A thin film transistor formed at a point of intersection of the gate line and the data line; A color filter layer formed in the pixel region where the gate wiring and the data wiring cross each other; An organic insulating layer formed on an entire surface of the substrate including the thin film transistor and having an opening exposing the thin film transistor; A pixel electrode formed on the organic insulating layer and directly connected to the thin film transistor through the opening; A passivation film formed over the organic insulating film including the pixel electrode; And a plurality of common electrodes formed on the passivation layer and overlapping the pixel electrodes and spaced apart from each other.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device, the method including: forming a gate wiring on one surface of a substrate in one direction; Forming a data wiring on the substrate to define a pixel region crossing the gate wiring, and a thin film transistor at an intersection point of the data wiring and the gate wiring; Forming a color filter layer in the pixel region where the gate wiring and the data wiring cross each other; Forming an organic insulating layer having an opening exposing the thin film transistor on an entire surface of the substrate including the thin film transistor; Forming a pixel electrode directly on the organic insulating layer and directly connected to the thin film transistor through the opening; Forming a passivation film on the organic insulating film including the pixel electrode; And forming a plurality of common electrodes overlapping the pixel electrodes and spaced apart from each other on the passivation layer.

According to an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a manufacturing method thereof according to the present invention, the drain contact hole formed to electrically connect the existing drain electrode and the pixel electrode is omitted. An opening is formed in the organic insulating film to expose the upper portion of the thin film transistor, so that the exposed thin film transistor and the pixel electrode are electrically connected directly. Thus, the area used for forming the drain contact hole is used as the opening area, so transmittance is decreased. It is improved compared to the existing one.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a method of manufacturing the same, the color filter layer is formed on the thin film transistor array substrate, so that the upper substrate overlaps with the thin film transistor and the data wiring. That is, since the black matrix does not need to be formed on the color filter substrate, the aperture ratio increases accordingly.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a manufacturing method thereof do not need to separately form an overcoat layer previously formed to achieve flattening between the black matrix and the color filter layer. The number of manufacturing processes is reduced accordingly.

Furthermore, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a method of manufacturing the same are vertically formed by increasing the separation distance between adjacent pixels in the structure of forming a common electrode on the top of the liquid crystal display device. C / T can be reduced.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a manufacturing method thereof have reduced resistance of data wiring, thereby reducing driving voltage.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a manufacturing method thereof include the conductive layer corresponding to the source electrode and drain electrode forming region and the impurities under the data wiring. Since the amorphous silicon layer (n + or p +) and the amorphous silicon layer (a-Si: H) are patterned at the same time, there is no fear of an active tail.

1 is a schematic plan view of a FFS (Fringe Field Switching) type liquid crystal display device according to the prior art.
FIG. 2 is an enlarged plan view of a thin film transistor and a drain contact hole of FIG. 1 in a conventional FFS type liquid crystal display device. FIG.
3 is a cross-sectional view taken along line III-III of FIG. 1 and is a schematic cross-sectional view of a FFS (Fringe Field Switching) type liquid crystal display device according to the prior art.
4 is a schematic plan view of a Fringe Field Switching (FFS) type liquid crystal display device according to the present invention.
FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4 and is a schematic cross-sectional view of a FPS type liquid crystal display device according to the present invention.
6A through 6R are cross-sectional views illustrating manufacturing processes of an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device according to the present invention.

Hereinafter, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic plan view of a Fringe Field Switching (FFS) type liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4 and is a schematic cross-sectional view of a FPS type liquid crystal display device according to the present invention.

In accordance with an embodiment of the present invention, a Fringe Field Switching (FFS) type liquid crystal display device includes: a gate wiring 103 formed on one surface of an insulating substrate 101 in one direction; A data line 113a crossing the gate line 103 to define a pixel area; A thin film transistor (T) formed at an intersection point of the gate line 103 and the data line 113a; A first passivation film 118 formed on the entire surface of the substrate including the thin film transistor T; A color filter layer 117 formed in the pixel region where the gate wiring and the data wiring cross each other; An organic insulating layer 119 formed on an entire surface of the substrate including the thin film transistor T and having an opening 123 exposing the thin film transistor T; A pixel electrode 125a formed on the organic insulating layer 119 and directly connected to the thin film transistor T through the opening 123; A second passivation film 131 formed on the organic insulating film 119 including the pixel electrode 125a; A plurality of common electrodes 137a are formed on the second passivation layer 131 and overlap the pixel electrodes 125a and are spaced apart from each other.

The pixel electrode 125a is disposed in front of the pixel region where the gate wiring 103 and the data wiring 113a cross each other, and the passivation layer 131 is interposed between the pixel electrode 125a and the pixel electrode 125a. A plurality of rod-shaped transparent common electrodes 137a spaced apart from each other are disposed on the substrate.

In addition, as illustrated in FIG. 5, the pixel electrode 125a is directly connected to the drain electrode 113c through an opening 123 located above the thin film transistor T without a separate drain contact hole. do. In this case, the opening 123 is formed to expose the source electrode 113b and the drain electrode 113c constituting the thin film transistor T.

On the other hand, the color filter layer 117 formed on the first passivation film 118, which is a pixel region where the gate wiring and the data wiring intersect, is not shown in the figure, a red color filter layer (not shown), A green color filter layer (not shown) and a blue color filter layer (not shown) are included. In this case, since the color filter layer 117 is not formed on the upper substrate 141 and the color filter layer 117 is not formed on the upper substrate 141, it is not necessary to form a black matrix.

A column spacer 145 is formed on the upper substrate 141 to maintain a constant cell gap of the liquid crystal display device. The column spacer 145 has an opening formed in the insulating substrate 101. 123 is disposed correspondingly. In this case, the column spacer 145 is disposed to be inserted into the opening 123 when the insulating substrate 101 and the upper substrate 141 are bonded together, thereby preventing movement of the insulating substrate 101 and the upper substrate 141. To keep the bonding stable.

Therefore, in the case of the present invention, as shown in Fig. 5, the drain contact hole previously formed is removed, and the area of the region where the drain contact hole has been removed is used as the opening area, thereby improving the transmittance of the pixel.

In addition, the liquid crystal layer 151 is formed between the insulating substrate 101 and the upper substrate 141 to form a Fringe Field Switching (FFS) type liquid crystal display device according to the present invention.

Through the above configuration, the plurality of common electrodes 137a supplies a reference voltage for driving the liquid crystal, that is, a common voltage to each pixel.

The plurality of common electrodes 137a overlap the pixel electrode 125a of the large area with the passivation layer 131 interposed therebetween to form a fringe field.

When the data signal is supplied to the pixel electrode 125a through the thin film transistor T, the common electrode 137a supplied with the common voltage forms a fringe field to form a fringe field. As the liquid crystal molecules arranged in the horizontal direction between the filter substrates 141 are rotated by dielectric anisotropy, the light transmittance of the liquid crystal molecules passing through the pixel region is changed according to the degree of rotation, thereby realizing gradation.

Therefore, according to the array substrate for a Fringe Field Switching (FFS) type liquid crystal display device according to the present invention, the drain contact hole formed to electrically connect the existing drain electrode and the pixel electrode is omitted, and the passivation film is omitted. An opening is formed in the thin film transistor to expose the upper portion of the thin film transistor, so that the exposed thin film transistor and the pixel electrode are directly connected to each other. Is improved.

In addition, according to the present invention, the FSF (French Field Switching) array substrate for liquid crystal display device, since the color filter layer is formed on the thin film transistor array substrate, the upper substrate, that is, the color filter overlapping the thin film transistor and the data wiring Since the black matrix does not need to be formed on the substrate, the aperture ratio increases accordingly.

Further, according to the present invention, the FFC (French Field Switching) array substrate for liquid crystal display device, in the structure of forming a common electrode on the top of the liquid crystal display device, the vertical C / T according to the increase in the separation distance between adjacent pixels Can be reduced.

In addition, according to the present invention, the FSF (fringe field switching) array substrate for a liquid crystal display device can reduce the driving voltage because the resistance of the data wiring is reduced.

In addition, according to the array substrate for a Fnge (FFnge) type liquid crystal display device according to the present invention, an amorphous silicon layer containing the conductive layer corresponding to the source electrode and drain electrode forming region and the impurities under the data wiring Since (n + or p +) and the amorphous silicon layer (a-Si: H) are patterned at the same time, there is no fear of an active tail.

Meanwhile, a method of manufacturing an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device according to the present invention having the above configuration will be described with reference to FIGS. 6A to 6R.

6A through 6R are cross-sectional views illustrating manufacturing processes of an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device according to the present invention.

As shown in FIG. 6A, a plurality of pixel regions including a switching role are defined on the transparent insulating substrate 101, and the first conductive metal layer 102 is sputtered on the transparent insulating substrate 101 by a method of sputtering. Deposit. In this case, target materials for forming the first conductive metal layer 102 include aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and molybly tungsten. At least one selected from the group of conductive metals including (MoW), molybdenum (MoTi), copper / mortitanium (Cu / MoTi) is used. In this case, the first conductive metal layer 102 is formed of at least one laminated structure.

Next, a photoresist having high transmittance is coated on the first conductive metal layer 102 to form a first photoresist layer 105.

Subsequently, as shown in FIG. 6B, an exposure process is performed on the first photoresist film 105 through a photolithography process technique using an exposure mask (not shown), and then the first photoresist film 105 is subjected to a developing process. It is selectively removed to form the first photoresist pattern 105a.

Next, as shown in FIG. 6C, the first conductive metal layer 102 is selectively etched using the first photoresist pattern 105a as a blocking film, thereby forming a gate wiring 103 (see FIG. 4) and the gate wiring ( The gate electrode 103a extending from 103 and the common wiring 103b spaced apart from the gate wiring 103 are simultaneously formed.

Subsequently, as illustrated in FIG. 6D, after the first photoresist layer pattern 105a is removed, a gate insulating layer formed of silicon nitride (SiNx) or silicon oxide layer (SiO ₂ ) on the entire surface of the substrate including the gate electrode 103a ( 107).

Next, an amorphous silicon layer (a-Si: H) 109 and an amorphous silicon layer (n + or p +) 111 containing impurities are sequentially stacked on the gate insulating layer 107. In this case, the amorphous silicon layer (a-Si: H) 109 and the amorphous silicon layer (n + or p +) 111 containing impurities are deposited by a chemical vapor deposition method (CVD). In this case, instead of an amorphous silicon layer (a-Si: H) 109, an oxide-based semiconductor material such as IGZO may be formed on the gate insulating layer 107.

Subsequently, the second conductive metal layer 113 is deposited on the entire surface of the substrate including the amorphous silicon layer (n + or p +) 111 containing the impurities by a sputtering method. In this case, target materials for forming the second conductive metal layer 113 include aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and molybly tungsten. At least one selected from the group of conductive metals including (MoW), molybdenum (MoTi), copper / mortitanium (Cu / MoTi) is used.

 Subsequently, although not shown in the drawings, a second photosensitive film (not shown) is formed by applying a photo-resist having a high transmittance on the second conductive metal layer 113.

Next, an exposure process is performed on the second photoresist film (not shown) through a photolithography process technology using an exposure mask (not shown), and then the second photoresist film (not shown) is selectively removed through a developing process. 2 photosensitive film pattern 115 is formed.

Subsequently, as illustrated in FIG. 6E, the second photoresist layer pattern 115 is used as an etch mask and the second conductive layer 113 is selectively etched to cross the gate line 103 perpendicularly. A source electrode and a drain electrode formation region (not shown) are defined together with 113a).

Subsequently, an amorphous silicon layer including an impurity under a portion of the second conductive layer 113 corresponding to the source electrode and drain electrode formation region (not shown) and the data line 113a is formed through an etching process. n + or p +) 111 and the amorphous silicon layer (a-Si: H) 109 are sequentially etched to form an ohmic contact layer 111a and an active layer 109a. In this case, an amorphous silicon layer (n + or p +) 111 including the impurity under the portion of the second conductive layer 113 and the data wiring 113a corresponding to the source electrode and drain electrode formation region (not shown). Since the amorphous silicon layer (a-Si: H) 109 is patterned at the same time, there is no fear of an active tail.

Subsequently, a first layer of silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) is formed on the entire surface of the substrate including the conductive layer 113 corresponding to the source electrode and drain electrode forming region (not shown) and the data wiring 113a. The passivation film 118 is deposited.

Next, as shown in FIG. 6F, a red color filter layer (not shown) and a green color filter layer (not shown) are disposed in the pixel area where the data line 113a and the gate line 103 cross each other. ) And a color filter layer 117 including a blue color filter layer (not shown) are sequentially formed. In this case, one end of the red color filter layer (not shown), the green color filter layer (not shown), and the blue color filter layer (not shown) are overlapped on the data line 113a. .

Subsequently, an organic insulating layer 119 is sequentially deposited on the first passivation layer 118 including the color filter layer 117. In this case, as the organic insulating layer 117, a photo acryl material or other photosensitive organic insulating material exhibiting photosensitivity is used. In addition, since the photo acryl has photosensitivity, the exposure process may be performed without forming a photoresist during the exposure process. In this case, an inorganic insulating material may be used instead of the organic insulating layer 117.

Next, as shown in FIG. 6G, an exposure process is performed on the organic insulating layer 119 through a photolithography process technique using an exposure mask (not shown), and then developed to selectively remove the organic insulating layer 119. The organic insulating layer pattern 119a exposing portions of the first passivation layer 118 disposed on the conductive layer 113 corresponding to the source electrode and drain electrode forming region (not shown) and on the common wiring 103b. To form.

Subsequently, as illustrated in FIG. 6H, the exposed first passivation layer 118 is selectively etched using the organic insulating layer pattern 119a as an etch mask, and then formed on the source and drain electrode formation regions (not shown). First openings 123a and second openings 123b exposing the corresponding conductive layer 113 and the upper portion of the common wiring 103b are formed, respectively. In this case, the first opening 123a is positioned to correspond to the source electrode and drain electrode formation region (not shown), that is, the upper portion of the thin film transistor.

6I, a first transparent conductive material layer 125 is formed by depositing a transparent conductive material on the organic insulating film pattern 119 including the first and second openings 123a and 123b by a sputtering method. ). In this case, as the transparent conductive material, any one composition target may be used from a transparent conductive material group including indium tin oxide (ITO) and indium zinc oxide (IZO). In addition, the first transparent conductive material layer 125 is in direct contact with the surface of the conductive layer 113 corresponding to the source electrode and the drain electrode forming region (not shown).

Subsequently, a photoresist having a high transmittance is coated on the first transparent conductive material layer 125 to form a third photoresist layer 127.

Next, as shown in FIG. 6J, after performing an exposure process using a photolithography process technique using an exposure mask (not shown), the exposed third photoresist layer 127 is selectively removed to form a third photoresist pattern ( 127a). At this time, the upper surface of the first transparent conductive material layer 125 on the channel region of the thin film transistor is exposed to the outside.

Subsequently, as shown in FIG. 6K, the exposed first transparent conductive material layer 125, the second conductive metal layer 113 and the ohmic contact layer (below) are exposed using the third photoresist pattern 127a as an etch mask. 111a is sequentially etched to form the source electrode 113b and the drain electrode 113c, which are spaced apart from each other, together with the pixel electrode 125a and the dummy pattern 125b separated from each other. At this time, since the ohmic contact layer 111a is also etched and spaced apart, the channel region (not shown) of the active layer 109a under the exposed portion is exposed to the outside. In addition, the pixel electrode 125a is directly connected to the drain electrode 113c, and the source electrode 113b is directly connected to the dummy pattern 125b. At this time, since the dummy pattern 125b is only connected to the source electrode 113b, there is no need to separately etch the dummy pattern 125b.

Next, as shown in FIG. 6L, after removing the third photoresist pattern 127a, an inorganic insulating material or an organic insulating material is deposited on the entire surface of the substrate to form a second passivation layer 131. Subsequently, a fourth photoresist layer 133 is formed by applying a photo-resist having a high transmittance on the second passivation layer 131.

Next, as illustrated in FIG. 6M, the fourth photoresist layer 133a is removed by performing the exposure and development process by a photolithography process technique using an exposure mask (not shown) to remove the fourth photoresist layer pattern 133a. Form.

Subsequently, as illustrated in FIG. 6N, the second passivation layer 131 and the gate insulating layer 107 are sequentially etched using the fourth photoresist layer pattern 133a as an etching mask to expose the common wiring 103b. The common wiring contact hole 135 is formed.

6O, after the fourth photoresist layer pattern 133a is removed, a transparent conductive material is deposited on the passivation layer 131 including the common wiring contact hole 135 by sputtering. 2 to form a transparent conductive material layer (137). In this case, as the transparent conductive material, any one composition target from a group of transparent conductive materials including indium tin oxide (ITO) and indium zinc oxide (IZO) is used.

Subsequently, a fifth photoresist layer 139 is formed by applying a photo-resist having a high transmittance on the second transparent conductive material layer 137.

Subsequently, as illustrated in FIG. 6P, an exposure process is performed on the fifth photoresist film 139 through a photolithography process technology using an exposure mask (not shown), and then the fifth photoresist film 139 is formed through a development process. It selectively removes to form a fifth photoresist pattern 139a.

Next, as illustrated in FIG. 6Q, the second photoresist layer pattern 139a is selectively etched using the etching mask, and the second transparent conductive material layer 137 is selectively etched so as to overlap with the pixel electrode 123a and be spaced apart from each other. A plurality of common electrodes 137a are formed. In this case, the common electrode 137a is electrically connected to the common wiring 103b through the common wiring contact hole 135.

Subsequently, as shown in FIG. 6R, after removing the remaining fifth photoresist pattern 139a, a predetermined cell gap is formed on the second passivation layer 131 in the opening 123 of the upper portion of the thin film transistor T. A column spacer 145 is formed to hold the gap.

Next, although not shown in the drawing, a process of forming an alignment layer (not shown) is further formed on the entire surface of the substrate, thereby manufacturing an array substrate manufacturing process for a Fringe Field Switching (FFS) type liquid crystal display device according to the present invention. You are done.

Thereafter, as illustrated in FIG. 6R, the process of forming the alignment layer (not shown) on the upper substrate 141 is added, thereby completing the process of manufacturing the color filter array substrate.

Subsequently, a liquid crystal display (FFS) type liquid crystal display device according to the present invention is formed by performing a process of forming a liquid crystal layer 151 between the upper substrate 141 and the insulating substrate 101 bonded to each other. Complete the manufacturing process.

As described above, according to an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a method of manufacturing the same, a drain contact formed to electrically connect a conventional drain electrode and a pixel electrode is disclosed. The hole is omitted, and an opening is formed in the passivation film to expose the upper portion of the thin film transistor, so that the exposed thin film transistor and the pixel electrode are electrically connected directly, so that the area used to form the existing drain contact hole is changed to the opening area. As it is used, the transmittance is improved compared to the conventional one.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a method of manufacturing the same, the color filter layer is formed on the thin film transistor array substrate, so that the upper substrate overlaps with the thin film transistor and the data wiring. That is, since the black matrix does not need to be formed on the color filter substrate, the aperture ratio increases accordingly.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a manufacturing method thereof do not need to separately form an overcoat layer previously formed to achieve flattening between the black matrix and the color filter layer. The number of manufacturing processes is reduced accordingly.

Furthermore, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a method of manufacturing the same are vertically formed by increasing the separation distance between adjacent pixels in the structure of forming a common electrode on the top of the liquid crystal display device. C / T can be reduced.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a manufacturing method thereof have reduced resistance of data wiring, thereby reducing driving voltage.

In addition, according to the present invention, an array substrate for a Fringe Field Switching (FFS) type liquid crystal display device and a manufacturing method thereof include the conductive layer corresponding to the source electrode and drain electrode forming region and the impurities under the data wiring. Since the amorphous silicon layer (n + or p +) and the amorphous silicon layer (a-Si: H) are patterned at the same time, there is no fear of an active tail.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

101: insulating substrate 103: gate wiring
103a: gate electrode 107: gate insulating film
109a: active layer 111a: ohmic contact layer
113a: data wiring 113b: source electrode
113c: drain electrode 117: color filter layer
119: organic insulating film 123: opening
125a: pixel electrode 125b: dummy pattern
118 and 131: first and second passivation films 135: common wiring contact hole
137a: common electrode 141: upper substrate
145: column spacer 151: liquid crystal layer

Claims (8)

A gate wiring formed on one surface of the substrate in one direction;
A data line crossing the gate line to define a pixel area;
A thin film transistor formed at a point of intersection of the gate line and the data line;
A color filter layer formed in the pixel region where the gate wiring and the data wiring cross each other;
An organic insulating layer formed on an entire surface of the substrate including the thin film transistor and having an opening exposing the thin film transistor;
A pixel electrode formed on the organic insulating layer and directly connected to the thin film transistor through the opening;
A passivation film formed over the organic insulating film including the pixel electrode; And
And a plurality of common electrodes formed on the passivation layer and overlapping the pixel electrodes and spaced apart from each other. The array substrate of claim 1, wherein the opening is formed in the organic insulating layer overlapping the upper portion of the thin film transistor. The array substrate of claim 1, wherein a column spacer is formed in the opening. The array substrate of claim 1, wherein color filter layers of different colors overlap each other on the data line. Forming a gate wiring on one surface of the substrate in one direction;
Forming a data wiring on the substrate to define a pixel region crossing the gate wiring, and a thin film transistor at an intersection point of the data wiring and the gate wiring;
Forming a color filter layer in the pixel region where the gate wiring and the data wiring cross each other;
Forming an organic insulating layer having an opening exposing the thin film transistor on an entire surface of the substrate including the thin film transistor;
Forming a pixel electrode directly on the organic insulating layer and directly connected to the thin film transistor through the opening;
Forming a passivation film on the organic insulating film including the pixel electrode; And
And forming a plurality of common electrodes overlapping the pixel electrodes and spaced apart from each other on the passivation layer. 6. The method of claim 5, wherein the opening is formed in the organic insulating layer overlapping the upper portion of the thin film transistor. 6. The method of claim 5, further comprising forming a column spacer in the opening. 6. The method of claim 5, wherein the color filter layers having different colors overlap each other on the data line.

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